10-bit 125MSPS Converter Description CXA3197R high-speed converte
|
|
|
Top Searches for this datasheet
CXA3197R
10-bit 125MSPS Converter
Description CXA3197R high-speed converter which perform multiplexed input system 10-bit data. This realizes maximum conversion rate 125MSPS. Multiplexed operation possible inputing frequency-divided clock halving frequency clock internally with clock frequency divider circuit having reset pin. data input level, clock input reset input select either PECL level according application. Features Maximum conversion rate: During PECL operation: 125MSPS During operation: 100MSPS Resolution: bits power consumption: 480mW (typ.) Data input level: Clock, reset input level: PECL compatible multiplexed input function frequency-divided clock output possible built-in clock frequency divider circuit Voltage output load drive possible) Single power supply ±dual power supply operation Reset signal polarity switching function
AGND2 AOUTP AOUTN
LQFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING Structure Bipolar silicon monolithic Applications HDTV Communications (QPSK, QAM) Measuring devices
AGND2 VOCLP POLARITY DVCC1 N.C. DGND1 (MSB) RESETN/E RESETP/E RESET/T CLKN/E CLKP/E CLK/T DIV2OUT
DGND2
DIV2IN (LSB)
Configuration
AVCC2 VSET VREF
AVCCO
DVCC2
(MSB)
(LSB)
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
E97639A06-PS
CXA3197R
Absolute Maximum Ratings 25°C) Supply voltage AVCCO, AVCC2, DVCC2 AGND2, DGND2 DVCC1 AVCC2 AGND2 AVCCO AGND2 DVCC2 DGND2 -0.5 +6.0 -6.0 +0.5 -0.5 +6.0 -0.5 +6.0 -0.5 +6.0 -0.5 +6.0
Input voltage (Analog) (Digital)
VSET AGND2 AVCC2 input DGND1 DVCC1 PECL input DGND1 DVCC1 DGND1 DVCC1 (Others) VOCLP DGND1 DVCC1 Storage temperature Tstg +150 Allowable power dissipation (when mounted two-layer glass fabric base epoxy board with dimensions 76mm 114mm, 1.6mm) Recommended Operating Conditions [Single power supply] Supply voltage Min. Typ. Max. AVCCO +4.75 +5.0 +5.25 AVCC2 +4.75 +5.0 +5.25 AGND2 -0.05 +0.05 +4.75 +5.0 +5.25 DVCC1 DGND1 -0.05 +0.05 DVCC2 +4.75 +5.0 +5.25 DGND2 -0.05 +0.05 Input voltage (Analog) (Digital) VSET input PECL input
[Dual power supply] Min. Typ. Max. -0.05 +0.05 -0.05 +0.05 -5.50 -5.0 -4.75 +4.75 +5.0 +5.25 -0.05 +0.05 -0.05 +0.05 -5.50 -5.0 -4.75 Min. AGND2 0.65 DGND1 Typ.
Unit Max. Unit AGND2 1.03 DGND1 DVCC1 DVCC1 DVCC1 MSPS MSPS 1.05
DVCC1 1.05 DVCC1 VID1 (Others) VOCLP DGND1 pulse width (for RECL CLK) tpw1 tpw0 Maximum conversion rate During PECL operation During operation Load resistance Analog output full-scale voltage 0.75 Operating temperature
VID: Input Voltage Differential PECL input signal switching level
DVCC1 (Max.) (Min.) DGND1
CXA3197R
Description [Symbol] DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DGND2 DVCC2 AVCCO AOUTN AOUTP AGND2 VREF VSET [Pin No.] [Description]
Typical voltage level single power supply
Typical voltage level dual power supply PECL PECL PECL PECL (typ.) AVCCO AVCCO AGND2 1.25V AGND2 0.65V AGND2 1.03V Clamp voltage
Side data input. Side data input. frequency-divided clock input. frequency-divided clock output. clock input. PECL clock input. PECL PECL clock input. PECL reset input. PECL reset input. PECL PECL reset input. PECL Digital ground. Function setting. Function setting. Function setting. Digital power supply. Analog output power supply. (typ.) Negative analog output. AVCCO Positive analog output. Analog ground. Analog reference voltage. Full-scale adjustment. AVCCO AGND2 1.25V AGND2 0.65V AGND2 1.03V Clamp voltage
AVCC2 AGND2 VOCLP POLARITY DVCC1 N.C. DGND1
Analog power supply. Analog ground. High level clamp. Reset signal polarity switching. Analog output inversion. Power saving. Digital power supply. connected. Digital ground.
CXA3197R
Block Diagram
DVCC1
DVCC2
VOCLP
AVCC2
10bit
Input Latch
10bit 10bit Latch 10bit
AVCCO AOUTP
AOUTN 10bit Input Latch 10bit AGND2 DIV2OUT
Current Cont. VREF
DIV2IN
CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E POLARITY AGND2 VSET
DGND1
DGND2
CXA3197R
Description Equivalent Circuit Symbol Typical voltage level Equivalent circuit Description
DVCC1
Side data input.
DGND1 1.5V
Side data input.
DVCC1
DIV2IN
1.5V DGND1
frequency-divided clock input. this MUX.1A MUX.2 mode. Leave open other modes.
DVCC1
DIV2OUT
100K
DGND1
frequency-divided clock output. frequencydivided clock signal (DIV2OUT) output MUX.1A mode. high impedance other modes.
DVCC1
CLK/T
1.5V DGND1
Clock input. this when clock input level. this time, leave Pins open.
CXA3197R
Symbol
Typical voltage level
Equivalent circuit
Description Clock input. this when clock input PECL level. this time, leave open. CLKP/E CLKN/E complementary should used together. CLKP/E complementary input. Reset signal input. When multiple CXA3197R operated same time MUX.1A MUX.1B mode, start timing internal frequency divider circuits should matched. this time, reset signal used; when reset signal level, used Pins left open. When reset signal PECL level, Pins used left open. reset signal polarity POLARITY). Leave reset open when other modes used. RESETP/E RESETN/E complementary should used together.
DVCC1
CLKP/E
PECL
DGND1
CLKN/E
PECL
DVCC1
RESET/T
1.5V DGND1
RESETP/E
PECL
DVCC1
RESETN/E
PECL
DGND1
DGND2
Single power supply: Dual power supply:
DVCC1
Digital power supply.
Function setting.
1.5V
Function setting.
DGND1
Function setting.
CXA3197R
Symbol
Typical voltage level Single power supply: Dual power supply:
Equivalent circuit
Description
DVCC2
Digital power supply.
AVCCO
Single power supply: Dual power supply:
Analog output power supply. AVCCO voltage varied within range that satisfies analog output compliance voltage. Negative analog output. inverse positive analog output output. When positive output terminated with inverse output should also terminated with even inverse output used. Positive analog output.
AVCCO
AOUTN
AVCCO
AGND2
AOUTP
AVCCO Single power supply: Dual power supply:
AVCC2
AGND2
Analog ground.
VREF
AGND 1.25V (Typ.)
Reference voltage output.
AGND2
AVCC2
VSET
AGND2 0.65V AGND2 1.03V
Analog output full-scale adjustment.
AGND2
AVCC2
Single power supply: Dual power supply:
Analog power supply.
CXA3197R
Symbol
Typical voltage level Single power supply: Dual power supply:
Equivalent circuit
Description
AGND2
Analog power supply.
DVCC1
VOCLP
Clamp voltage
DGND1
output High level clamp. level signal output from DIV2OUT MUX.1A mode. High level voltage clamped value approximately equivalent voltage applied this pin. Leave VOCLP open other modes.
DVCC1
POLARITY
1.5V DGND1
Reset signal polarity switching. High level, reset polarity active Low; level, active High.
DVCC1
1.5V DGND1
Analog output polarity inversion. analog output inverted level.
DVCC1
Power saving. Power saving mode activated level. Normally pull High level this open Low.
DGND1
DVCC1 N.C. DGND1
Digital power supply. connected.
Digital ground.
CXA3197R
Electrical Characteristics (DVCC1, DVCC2, AVCC2, AVCCO +5V, DGND1, DGND2 25°C) Item Resolution Differential linearity error Integral linearity error Digital input (PECL) Digital input voltage Digital input current Digital input capacitance Digital input (TTL) Digital input voltage Threshold voltage Digital input current Digital input capacitance Digital output (TTL) Digital output voltage Leak current high impedance Digital output rise time Digital output fall time input (PS) input voltage input current Clamp (VOCLP) VOCLP input current Analog output characteristics Output full-scale voltage Output zero offset voltage Analog output resistance Analog output capacitance Absolute amplitude error Absolute amplitude error temperature characteristics Analog output rise time Analog output fall time Settling time Glitch energy Compliance voltage IVOCLP IVOCLP -2.0mA 1.0mA When When 2.4V 10pF) 2.4V 10pF) 3.5V 0.2V VOCLP DVCC1 VOCLP 2.4V 3.5V 0.2V Symbol DVCC1 1.05 DVCC1 1000mV Conditions Min. Typ. Max. -0.85/+0.5 -1.2/+0.5 ±1.2 DVCC1 DVCC1 Unit
DVCC1 0.8V DVCC1 1.6V
0.75
1.05
F.S. ppm/°C
AGND2 937.5mV
VSET AGND2 937.5mV 1000mV 25°C When 1V,1050,
-4.0 0.85 0.75
1.05 0.85
tSET
Mesured DVCC2 -2.1
CXA3197R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Reference/control amplifier characteristics VREF output voltage VREF VREF output voltage VREF mode VREF voltage drift coefficient ISET VSET input current Multiplying bandwidth Current consumption DICC1 DICC2 AICC2 AICCO Current consumption mode DICC1
REFOUT
AGND2 1.18 AGND2 1.25 AGND2 1.32 AGND2 1.18 AGND2 1.25 AGND2 1.32 15.5 0.432
ppm/°C
100mVp-p, SIN, -3dB Total current consumption DIcc1 current consumption DIcc2 current consumption AIcc2 current consumption AIccO current consumption Total current consumption mode DIcc1 current consumption mode DIcc2 current consumption mode AIcc2 current consumption mode AIccO current consumption mode
0.38
DICC2
0.001
AICC2
0.05
AICCO
0.001
64-step D.L.E.
This indicates D.L.E. when High data input code changes between: (MSB) (LSB) (MSB) (LSB) 0001000000 0000111111 AOUTP side output between: (MSB) (LSB) (MSB) (LSB) 1110111111 1111000000 AOUTN side output.
When using analog output within compliance voltage range, AVCCO that satisfies following equations. (min) (AVCCO VFS) DVCC2 -2.1V (max) (AVCCO VOF) DVCC2 1.5V
CXA3197R
current consumption power saving mode does include VREF output current. When grounding VREF AGND2 level using external resistance, voltage 1.18 1.32V generated VREF even power saving mode. Therefore, current indicated following equation flows from AVCC2 VREF pin. This value must added obtain actual current consumption power saving mode. VREF voltage IREFOUT External resistance
AVCC2
VREF power saving mode: IREFOUT VREF voltage External resistance
AGND2
signal level PECL Max. Min. Typ. Min. Typ. Unit MSPS MSPS 12.0 Max. Max. PECL PECL Reset signal level Symbol Conditions Min. Typ. 10pF Tpw1 Tpw0 ts-rst th-rst td-DIV 2T-tm Tpw1 Tpw0 ts-rst th-rst
Item
Maximum conversion rate
Clock High pulse width
Clock pulse width
Reset signal setup time
Reset signal hold time
DIV2OUT output delay
DIV2OUT DIV2IN maximum delay time
MUX.1A mode
Data input setup time
Data input hold time
Analog output pipeline delay
Switching characteristics
MUX.1B mode
Analog output delay
Maximum conversion rate
Clock High pulse width
Clock pulse width
Reset signal setup time
Reset signal hold time
Data input setup time
Data input hold time
Analog output pipeline delay
Analog output delay
CXA3197R
signal level Reset signal level Symbol Conditions Min. Typ. MSPS MSPS Max. Max. Tpw1 Tpw0 ts-DIV th-DIV Tpw1 Tpw0 ts-C2 th-C2 Min. Typ. Unit PECL
Item
Maximum conversion rate
Clock High pulse width
Clock pulse width
DIV2IN setup time
DIV2IN hold time
MUX.2 mode
Data input setup time
Data input hold time
Analog output pipeline delay
Analog output delay
Switching characteristics
SELE.A, SELE.B modes
Maximum conversion rate
Clock High pulse width
Clock pulse width
signal setup time
signal hold time
Data input setup time
Data input hold time
Analog output pipeline delay
Analog output delay
reset signal input MUX.2, SELE.A SELE.B mode.
CXA3197R
CXA3197R
Electrical Characteristics Measurement Circuits Differential Linearity Error Integral Linearity Error
10-bit Data input CLK/T 1MHz
DVCC1
DGND1 DVCC2 AVCC2 AVCCO AOUTP AOUTN VSET DGND2 AGND2 937.5mV
CXA3197R
(Digital Voltmeter)
Current Consumption
DVCC1 DVCC2 AVCC2 AVCCO High side data CXA3197R CLK/T 1MHz DIV2IN DIV2OUT DGND1 DGND2 AGND2 VSET AOUTP
DICC1 DICC2 AICC2 AICCO
side data
AOUTN
937.5mV
Analog Output Characteristics Output Full-Scale Absolute Amplitude Error Output Zero Offset Voltage
High side data
DVCC1 CLK/T
DGND1 DVCC2 AVCC2 AOUTP AVCCO
side data
CXA3197R AOUTN VSET
1MHz
DGND2 AGND2
937.5mV
CXA3197R
Analog Output Rise Time Analog Output Fall Time Settling Time Glitch Energy
Oscilloscope
DVCC1 (Digital Pattern Generator) CLKP/E CLKN/E 100MHz PECL VSET DGND2 AGND2 DGND1 DVCC2 AVCC2 AOUTP AVCCO AOUTN CXA3197R VREF
Reference/Control Amplifier Characteristics VREF Output Voltage VREF Output Voltage Power Saving Mode Multiplying Bandwidth
Oscilloscope
DVCC1 High side data CLKP/E CLKN/E 20MHz PECL
DGND1 DVCC2 AVCC2 AVCCO AOUTP
High side data
AVCCO AOUTP output 0.1µF VSET output 100mVp-p AGND2 937.5mV
AOUTN CXA3197R VREF VSET
DGND2 AGND2
CXA3197R
AVCCO AVCCO
AOUTP output (INV
AVCCO
(AVCCO VOF) (AVCCO VFS) 1023 1LSB 1LSB 1LSB
1LSB
D.L.E.
I.L.E.
(MSB)
(LSB)
Data input code
Data input code (MSB) (LSB) (MSB) (LSB)
Analog output level AOUTP AVCCO AVCCO AOUTN AVCCO AVCCO
Table Correspondence Table
CXA3197R
Description Operation CXA3197R four types operation modes support various applications. operation mode switching function setting pins (C1, C3). Operation Mode Table Mode SELE.B High impedance 62.5 Data AOUT (MSPS) (Mbps) (Mbps) DIV2OUT Outputs CLK/2 level High impedance High impedance High impedance Description operation operation internal CLK/2 operation internal CLK/2 operation DIV2IN conversion side data input conversion side data input
MUX.1A MUX.1B MUX.2
SELE.A
CXA3197R input data divided into systems: (DA0 DA9) (DB0 DB9), internally multiplex data, output analog signal, making possible halve data rate. This lets CXA3197R support data input level contrast data input level conventional high-speed converters. clock signal reset signal input levels selected from either PECL according application. (However, setting both signals either PECL input level recommended.) MUX.1A mode this mode. MUX.1A mode, frequency clock input from clock input halved internally, frequency-divided signal output level from DIV2OUT pin. Data synchronized with DIV2OUT signal (the signal output from DIV2OUT pin) obtained operating CXA3197R front-end system with DIV2OUT signal. timing which data output delay CXA3197R front-end system matches with hold time during CXA3197R data input easily inputting this synchronized data data input pins DIV2OUT signal DIV2IN pin. data divided input systems: (DA0 DA9) (DB0 DB9), internally multiplexed, extracted analog output.
Clock input Clock input DIV2OUT (DIV2OUT signal) DIV2IN CXA3197R (MUX.1A mode)
10bit Data. CXA3197R front-end system 10bit 10bit Data. 10bit
Data input pins
Front-end system data output delay CXA3197R data input hold time
CXA3197R
When using multiple CXA3197R MUX.1A mode, start timing frequency-divided clocks becomes phase, producing operation such that shown example below. countermeasure, MUX.1A mode function that matches start timing frequency-divided clocks with reset signal. When using PECL level reset signal, input reset signal Pins (RESETP/E, RESETN/E) leave (RESET/T) open. When using level reset signal, input reset signal (RESET/T) leave Pins (RESETP/E, RESETN/E) open. reset polarity switched POLARITY (Pin 39). When POLARITY High open, reset active Low; when Low, reset active High. timing chart detailed timing.
Example when using reset signal
CXA3197R DIV2OUT DIV2OUT
CXA3197R DIV2OUT DIV2OUT
Example when using reset signal
Reset signal (when active Low) DIV2OUT
CXA3197R DIV2OUT RESET CXA3197R DIV2OUT Reset signal RESET
DIV2OUT
CXA3197R
MUX.1B mode High this mode. MUX.1B mode, frequency clock input from clock input halved internally, data loaded this frequency-divided signal. frequency-divided signal cannot observed this time, data actually loaded observing clock reset signals estimate rising edge internally frequency-divided signal. data divided input systems: (DA0 DA9) (DB0 DB9). data internally multiplexed, then system data output analog signal with 2-clock pipeline delay, system data analog signal with 3-clock pipeline delay after loading clock.
Clock input Clock th-rst Reset signal (when active Low) Internally frequency-divided signal (This signal cannot observed.) ts-rst Reset input
CXA3197R (MUX.1B mode)
Data input signal
After reset released, internal frequency-divided signal commences first clock edge, sure input data manner that satisfies setup time (ts) hold time (th) with respect this clock edge.
CXA3197R
Like MUX.1A mode, when using multiple CXA3197R MUX.1B mode, start timing frequency-divided clocks becomes phase, producing operation such that shown example below. countermeasure, MUX.1B mode also function that matches start timing frequency-divided clocks with reset signal. When using PECL level reset signal, input reset signal Pins (RESETP/E, RESETN/E) leave (RESET/T) open. When using level reset signal, input reset signal (RESET/T) leave Pins (RESETP/E, RESETN/E) open. reset polarity switched POLARITY (Pin 39). When POLARITY High open, reset active Low; when Low, reset active High. timing chart detailed timing.
Example when using reset signal
CXA3197R Internally frequency-divided signal
CXA3197R
Internally frequency-divided signal
Example when using reset signal
Reset signal (when active Low) Internally frequency-divided signal
CXA3197R RESET CXA3197R RESET signal RESET
Internally frequency-divided signal
CXA3197R
MUX.2 mode High this mode. MUX.2 mode, clock input clock input pin, signal with cycle half that clock (hereafter, DIV2IN signal) input DIV2IN level. DIV2IN signal internally latched clock, consideration must given setup time (ts_DIV) hold time (th_DIV) with respect clock. addition, data loaded DIV2IN signal, consideration must also given setup time (ts) hold time (th) with respect DIV2IN signal. data divided input systems: (DA0 DA9) (DB0 DB9). data internally multiplexed, then system data output analog signal with 2-clock pipeline delay, system data analog signal with 3clock pipeline delay from clock that loads DIV2IN signal. timing chart detailed timing.
Clock ts_DIV DIV2IN signal System data th_DIV
CXA3197R (MUX.2 mode) Clock input
DIV2IN input
System data
Analog output signal
CXA3197R
SELE.A mode SELE.B mode High SELE.A mode. SELE.A mode, clock input clock input pin, data input system (DA0 DA9) data input pins. High SELE.B mode. SELE.B mode, clock input clock input pin, data input system (DB0 DB9) data input pins. either mode, consideration must given setup time (ts) hold time (th) with respect clock. Also, data output analog signal with 1-clock pipeline delay after loading clock. Switching between SELE.A mode SELE.B mode done switching between High levels. Also, mode switched high speed sync with clock inputting switching signal signal) pin. signal internally latched clock, consideration must given setup time (ts_C2) hold time (th_C2) with respect clock. timing chart detailed timing.
Clock
ts_C2 th_C2
CXA3197R (SELE.A mode/SELE.B mode) Clock input
input signal System data Select System data
Analog output signal
CXA3197R
Block Diagram Timing Chart (MUX.1A Mode)
RESET DIV2OUT DIV2IN Input Data Input Latch Latch Input Data Input Latch Latch Latch Analog CLK/2 (Internal)
Tpw1 Tpw0 ts-rst th-rst (Active High) (Active Low) td-DIV
RESET
DIV2OUT DIV2IN 2T-tm Input Data Input Data
MUX.1A mode, Data Data internally multiplexed then resulting signal analog output. frequency clock halved built-in clock frequency divider circuit CLK/2 output level (DIV2OUT). CLK/2 reset reset signal.
(Timing judgment points)
PECL
±1/2LSB
2.0V 0.8V
2.0V 0.8V
Analog output
±1/2LSB
tSET
CXA3197R
Block Diagram Timing Chart (MUX.1B Mode)
RESET CLK/2 (Internal)
Input Data
Input Latch Latch Analog
Input Data
Input Latch
Tpw1 Tpw0 RESET (Active High) CLK/2 (Internal) Input Data Input Data ts-rst th-rst (Active High) (Active Low) D-FF
MUX.1B mode, Data Data internally multiplexed then resulting signal analog output. frequency clock halved built-in clock frequency divider circuit. CLK/2 reset reset signal.
CXA3197R
Block Diagram Timing Chart (MUX.2 Mode)
DIV2IN CLK/2 (Internal)
Input Data
Input Latch
Latch Latch Analog
Input Data
Input Latch
Latch
Tpw1 Tpw0 ts-DIV th-DIV DIV2IN Input Data Input Data
MUX.2 mode, frequency-divided clock signal (DIV2IN) Data Data which synchronized with DIV2IN, provided simultaneously. These signals internally multiplexed resulting signal analog output.
CXA3197R
Block Diagram Timing Chart (SELE.A, SELE.B Mode)
Latch
Input Data
Input Latch Select Latch Analog
Input Data
Input Latch
Tpw1
Tpw0
Input Data
th-C2
ts-C2
Input Data
Latch
SELE.
SELE.
SELE.A SELE.B modes, input Data Data selected selected data analog output. When Data selected Data selected
CXA3197R
Application Circuit circuit shown below basic circuit when analog output terminated with external resistance operation with dual power supply MUX.2 mode. analog output uses AVCCO reference. analog output full-scale voltage obtained with following equation. VSET RO//RL Output impedance External termination resistance
Here, VSET
VREF (VREF 1.2V) 1.2k)
+5V(D)
0V(D)
-5V(A)
0V(A)
(MSB)
DVCC1
DGND1
POLARITY
AGND2
VOCLP
Latch
AVCC2 VSET VREF AGND2 AOUTP AOUTN AVCCO DVCC2
0V(A) -5V(A) -5V(A) 0V(A)
(LSB)
0V(A) 0V(A) 0V(D) 0V(A) -5V(D)
(MSB)
(LSB)
RESETP/E
RESETN/E
DIV2OUT
+5V(D)
CLKP/E
CLKN/E
0V(D)
CLK/2 PECL
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
RESET/T
DGND2
DIV2IN
CLK/T
CXA3197R
Notes CXA3197R PECL input pins clock reset inputs. When clock input PECL level, recommended also input reset signal PECL level. Likewise, when clock input level, recommended also input reset signal level. input signal impedance should properly matched ensure stable CXA3197R operation high speed. Particularly when ringing appears input clock MUX.1A MUX.1B modes, this ringing exceeds clock input threshold value, internal frequency divider circuit misoperate. input pins CXA3197R except High level when left open, only goes level when left open. High level operate When PECL input pins left open, (positive) side goes High level (negative) side goes level. PECL input pins complementary, sure sides together. When clock reset input signal level TTL, pins should used pins left open. When clock reset input signal level PECL, pins should used pins left open. power supply grounding have profound influence converter characteristics. power supply grounding method particularly important during high-speed operation. General points caution follows. ground pattern should wide possible. recommended make power supply ground wider inner layer using multi-layer board. prevent offset from being generated between analog digital power supply patterns, recommended connect patterns point ferrite-bead filter, etc. When using CXA3197R with single power supply, connect DGND1 DGND2 common digital ground, AGND2 analog ground. Also, DVCC1 DVCC2 should common digital power supply, AVCC2 should connected analog power supply. AVCCO serves analog output reference, while does need share analog power supply, should used within range that satisfies analog output compliance voltage. When using CXA3197R with dual power supply, connect DGND1 DVCC2 digital ground, AVCC2 analog ground. DVCC1 uses positive digital power supply (+5V, typ.), DGND2 uses negative digital power supply (-5V, typ.), AGND2 uses negative analog power supply (-5V, typ.). Like when using single power supply, AVCCO used within range that satisfies analog output compliance voltage. However, connecting analog ground using analog ground reference analog output recommended. Ground power supply pins close each possible with 0.1µF more ceramic chip capacitor. When using single power supply, connect DVCC1 DVCC2 digital ground, AVCC2 AVCCO analog ground. When using dual power supply, connect DVCC1 DGND2 digital ground, AGND2 analog ground. this case, when using AVCCO within range that satisfies compliance voltage, sure also connect AVCCO analog ground using ceramic chip capacitor. CXA3197R designed with analog output impedance analog outputs wired with characteristic impedance waveforms free reflection obtained terminating analog outputs with Even when using only either AOUTP AOUTN, analog output terminated with sure also terminate other analog output with (See Application Circuit.)
CXA3197R
Example Representative Characteristics
Output full-scale voltage VSET voltage
1100
Output full-scale voltage Ambient temperature
1100 VSET AGND2 937.5mW 1050
1000
Output full-scale voltage [mV]
1.03
Output full-scale voltage [mV]
1000
0.65 0.84 VSET voltage
Ambient temperature [°C]
VREF voltage Ambient temperature
Output zero offset voltage Ambient temperature
VSET AGND2 937.5mW
1280
1260
Output zero offset voltage [mV]
VREF voltage [mV]
1240
1220
Ambient temperature [°C]
Ambient temperature [°C]
Multiplying bandwidth
Analog output amplitude [dB]
VSET input frequency [MHz]
CXA3197R
Package Outline
Unit:
48PIN LQFP (PLASTIC)
(8.0)
0.08 0.08 0.18 0.03
(0.22)
0.05 0.127 0.02
NOTE: Dimension does include mold protrusion. DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
NOTE PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
Sony Corporation
Other recent searches
Q25A - Q25A Q25A Datasheet
Q25AM - Q25AM Q25AM Datasheet
MA2X073 - MA2X073 MA2X073 Datasheet
DAC5672 - DAC5672 DAC5672 Datasheet
CAS02X-068 - CAS02X-068 CAS02X-068 Datasheet
AH108RU - AH108RU AH108RU Datasheet
2SK3438 - 2SK3438 2SK3438 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
