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CXA3250N
Band Tuner with On-chip availability this product, please contact sales office.
Description CXA3250N monolithic tuner which integrates local oscillator mixer circuits band, local oscillator mixer circuits band, amplifier tuning onto single chip, enabling further miniaturization tuner. Features power consumption typ.) Superior cross modulation Balanced oscillator pins) with excellent oscillation stability Supports both 3-wire modes Automatic identification 27-bit control (during 3-wire mode) On-chip converter (during mode) On-chip high voltage drive transistor charge pump Reference frequency selectable from 31.25, 62.5 (when using crystal) Low-phase noise synthesizer On-chip 4-output band switch (supports output voltages from Applications tuners tuners CATV tuners Structure Bipolar silicon monolithic SSOP (Plastic)
Absolute Maximum Ratings (Ta=25 Supply voltage VCC1, VCC2 -0.3 +5.5 VCC3 -0.3 +10.0 Storage temperature Tstg +150 Allowable power dissipation (when mounted printed circuit board) Operating Conditions Supply voltage VCC1, VCC2 4.75 5.30 VCC3 4.75 9.45 Operating temperature Topr
This pins whose electrostatic discharge strength weak operating frequency high high-frequency process used this Take care handling Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
E98X34-TE
CXA3250N
Block Diagram Configuration
VCC3 ADSW Mode Select V.REG Bias Programmable Divider 14/15bit Band Driver Phase Detector Charge Pump LOCK /ADC Interface Shift Register Divider 1/64, REFOSC
LOCK
IFOUT
VCC1
GND2
Buffer
VCC2
MIXout1 MIXout2 GND1
UOSCB2 UOSCE2 UOSCE1 UOSCB1
Buffer BYP/MS VHFin
VOSC2 Buffer UHFin1 UHFin2 VOSC1
CXA3250N
Description Symbol CE/ADSW VCC1 MIXOUT1 MIXOU2 GND1 BYP/MS VHFIN UHFIN1 UHFIN2 VOSC1 VOSC2 UOSCB1 UOSCE1 UOSCE2 UOSCB2 VCC2 GND2 IFOUT LOCK/ADC REFOSC VCC3 Description CLOCK/SCL (I2C bus) DATA/SDA (I2C bus) Enable/address selection (I2C bus) Band switch output Band switch output Band switch output Band switch output Analog circuit output output Analog circuit input control switching input input input oscillator (base input) oscillator (collector output) oscillator (base pin) oscillator (emitter pin) oscillator (emitter pin) oscillator (base pin) circuit circuit output LOCK signal output/ADC input (I2C bus) drive voltage output (open collector) Charge pump output (loop filter connection) Crystal connection Band switch power supply
CXA3250N
Description Equivalent Circuit Symbol voltage
Equivalent circuit
Description
5.1k
Clock input.
5.1k
Data input.
150k
ADSW/CE
1.25 (when open)
setting Address selection. Bits address byte controlled. 3-wire setting Enable input.
Band switch outputs. corresponding selected band goes High.
VCC1
Analog circuit power supply.
CXA3250N
Symbol
voltage
Equivalent circuit
Description
MIXOUT1
MIXOUT2
Mixer output. These pins output signal with open collector, they must connected power supply load.
GND1
during reception during reception during reception during reception during reception during reception during reception during reception during reception during reception during reception during reception
Analog circuit GND.
BYP/MS
input grounding control switching. input. Input format unbalanced input.
VHFin
UHFin1
UHFin2
inputs. Input signal Pins symmetrically ground either with capacitor input signal rest.
VOSC1
External resonance circuit connection oscillator.
VOSC2
separating analog systems.
CXA3250N
Symbol
UOSCB1
UOSCE1
UOSCE2
UOSCB2
VCC2 GND2
voltage during reception during reception during reception during reception during reception during reception during reception during reception
Equivalent circuit
Description
External resonance circuit connection oscillator.
circuit power supply. circuit GND.
IFOUT
output.
LOCK/ADC
500k
setting 5-level converter input. 3-wire setting Lock detection. when locked, High when unlocked.
CXA3250N
Symbol
voltage
Equivalent circuit
Description Varicap drive voltage output. This outputs signal with open collector, this must connected tuning power supply load.
Charge pump output. Connects loop filter.
REFOSC
Crystal connection reference oscillator.
VCC3
Power supply external supply.
CXA3250N
Electrical Characteristics Circuit Current Item Circuit current Symbol AICCV AICCU Circuit current DICC Measurement conditions VCC1 current, band switch output open during operation VCC1 current, band switch output open during operation VCC2 current Min. Typ.
(VCC=5 Ta=25 Max. Unit
OSC/MIX/IF Amplifier Block Item Conversion gain Symbol Maximum output Pomax power Switch drift fsw1 fsw2 fsw3 fsw4 Measurement conditions operation fRF=55 operation fRF=360 operation fRF=360 operation fRF=800 operation fRF=55 operation fRF=360 operation fRF=360 operation fRF=800 operation fD=55 MHz, fUD=±12 operation fD=360 MHz, fUD=±12 operation fD=360 MHz, fUD=±12 operation fD=800 MHz, fUD=±12 load saturation output operation fOSC=100 from after switch operation fOSC=405 from after switch operation fOSC=405 from after switch operation fOSC=845 from after switch Min. Typ. ±300 ±600 ±350 ±350 Max. Unit
Noise figure
cross modulation
CXA3250N
Item Supply voltage drift
Symbol fst1 fst2 fst3 fst4
Oscillator phase noise Reference leak Lock-up time
REFL
Measurement conditions operation fOSC=100 when changes operation fOSC=405 when changes operation fOSC=405 when changes operation fOSC=845 when changes offset offset Phase comparison frequency 62.5 kHz, operation fOSC=95 fOSC=395 operation fOSC=413 fOSC=847
Min.
Typ.
Max. ±200 ±250 ±150 ±150
Unit dBc/Hz
Value measured with untuned input. meter direct-reading value (DSB measurement). Value with desired reception signal input level dBm, interference signal kHz/30 interference signal level where S/I=46 measured with spectrum analyzer. Value when operating.
CXA3250N
Block Item pins level input voltage level input voltage level input current level input current (charge pump) Output current Leak current Output current Leak current voltage output) Maximum output voltage Minimum output voltage LOCK output voltage output voltage REFOSC Oscillation frequency range Input capacitance Negative resistance Band Output current Saturation voltage Leak current timing (I2C bus) clock frequency Start waiting time Start hold time hold time hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time timing (3-wire bus) Data setup time Data hold time Enable waiting time Enable setup time Enable hold time Symbol ICPO1 LeakCP1 ICPO2 LeakCP2 VLOCKH VLOCKL FXTOSC CXTOSC RNEG VSAT LeakBS fSCL tWSTA tHSTA tLOW tHIGH tSSTA tHDAT tSDAT tSSTO -10- When locked When unlocked VCC-0.5 Crystal source impedance When When Source current=20 When 1300 1300 VIH=VCC VIL=GND Byte4/bit6=0 Byte4/bit6=0 Byte4/bit6=1 Byte4/bit6=1 ±140 Measurement conditions Min. ±200 Typ. Max. -0.1 ±300 -0.7 Unit
-1.4
CXA3250N
Electrical Characteristics Measurement Circuit (I2C control)
+30V
8200p 1.2k 6.8k 0.047µ 100p 2.2µ 2.5t 5.5t 2.5t
0.75p
1T363
0.5p 0.5p
1T363
150p
1T363
XTAL 4MHz 100p VCC3 REFOSC LOCK/ADC
UOSCE2 UOSCE1 UOSCB1 VOSC2
1T362
IFOUT
GND2
VCC2
UOSCB2
VOSC1
CXA3250N CE/ADSW
out1
out2
BYP/MS
VCC1
4.5t
4.5t
ADSW
2.2µ
-11-
GND1
CXA3250N
Electrical Characteristics Measurement Circuit (3-wire control)
+30V
8200p 1.2k 6.8k 0.047µ 100p 2.2µ 2.5t 5.5t 2.5t
0.75p
1T363
0.5p 0.5p
1T363
150p
1T363
XTAL 4MHz 100p VCC3 REFOSC LOCK/ADC
UOSCE2 UOSCE1 UOSCB1 VOSC2
1T362
IFOUT
GND2
VCC2
UOSCB2
VOSC1
CXA3250N CE/ADSW
out1
out2
BYP/MS
4.5t
4.5t
ENABLE
2.2µ
-12-
GND1
VCC1
CXA3250N
Application Circuit (I2C control)
+30V
2.2µ
100p 8200p
5.5t 1T363 1.5t 2.5t 1.2k 2.2n 2.2n
6.8k 0.047µ
1.2µ
1.2k 0.75p
0.5p
100p
1T363
XTAL 4MHz 2.2n 100p VCC3 REFOSC LOCK/ADC
UOSCE2 UOSCE1 UOSCB1 VOSC2
1T362 VOSC1
IFOUT
GND2
VCC2 CXA3250N
UOSCB2 out1
CE/ADSW
out2
BYP/MS
450nH
6.8µH
2.2µ ADSW
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
-13-
100P
GND1
VCC1
CXA3250N
Application Circuit (3-wire control)
+30V
2.2µ
100p 8200p
5.5t 1T363 1.5t 2.5t 1.2k 2.2n 2.2n
6.8k 0.047µ
1.2µ
1.2k 0.75p
0.5p
100p
1T363
XTAL 4MHz 2.2n 100p VCC3 REFOSC LOCK/ADC
UOSCE2 UOSCE1 UOSCB1 VOSC2
1T362 VOSC1
IFOUT
GND2
VCC2 CXA3250N
UOSCB2 out1
CE/ADSW
out2
BYP/MS
VCC1
450nH
6.8µH
2.2µ ENABLE
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
-14-
100P
GND1
CXA3250N
Description Functions CXA3250N ground wave broadcast tuner which converts frequencies order tune detect only desired reception frequency VHF, CATV band signals. addition mixer, local oscillation amplifier circuits required frequency conversion this also integrates circuit local oscillation frequency control onto single chip. functions various circuits described below. Mixer circuit This circuit outputs frequency difference between signal input VHFIN UHFIN local oscillation signal. Local oscillation circuit formed externally connecting resonance circuit composed varicap diode inductance. amplifier circuit This circuit amplifies mixer output, consists amplifier stage impedance output stage. circuit This circuit fixes local oscillation frequency desired frequency. consists programmable divider, reference divider, phase comparator, charge pump reference oscillator. control format supports both 3-wire formats. During control, frequency steps 31.25, 62.5 selected data-based reference divider frequency division setting value. During 3-wire control, these frequency steps selected combination communication word length bits) voltage applied BYP/MS pin. Band switch circuit CXA3250N four sets built-in transistors switching between bands switching trap, etc. These transistors controlled data. emitters these transistors connected independent power supply (VCC3) from oscillator, mixer circuits, support either amplifier power supply.
-15-
CXA3250N
Description Analog Block Operation (See Electrical Characteristics Measurement Circuit.) oscillator circuit This circuit differential amplifier type oscillator circuit. output input. Oscillation performed connecting resonance circuit including varicap coupled capacitance, inputting with feedback capacitance, applying positive feedback. amplifier between Pins extremely high gain. Therefore, care should taken avoid creating parasitic capacitance, resistance other feedback loops this produce abnormal oscillation. mixer circuit mixer circuit employs double balanced mixer with little local oscillation signal leakage. input format base input type, with grounded capacitor signal input (Pin also used switch mode according applied voltage value.) signal from oscillator, converted frequency output from Pins oscillator circuit This oscillator circuit designed that collector ground type Colpitts oscillators perform differential oscillation operation resonance circuit including varicap. Resonance capacitance connected between Pins Pins Pins resonance circuit including varicap connected between Pins mixer circuit This circuit employs double balanced mixer like mixer circuit. input format base input type, with Pins input pins. input method selected from balanced input consisting differential input Pins unbalanced input consisting grounding capacitor input Pins mixer outputs. amplifier circuit signals frequency converted mixer output from Pins same time coupled inside input amplifier. Single-tuned filters connected Pins order improve interference characteristics amplifier. signal amplified amplifier output from output impedance approximately
-16-
CXA3250N
Description Block This supports both 3-wire control. conforms standard format, bidirectional control possible consisting write mode which various data received read mode which various data sent. 3-wire equipped with 19-bit auto identify function, frequency step switched according voltage applied BYP/MS pin. this does have fixed frequency division circuit performs high-speed phase comparison, providing reference leak quick lock-up time characteristics. During power-on (VCC2), power-on reset circuit operates initialize frequency data band data "OFF". Power-on reset performed when Vcc2=2.5 room temperature (Ta=25 °C). Function Table Symbol ADSW/CE LOCK/ADC input Address selection input 3-wire CLOCK input DATA input ENABLE input LOCK output
Mode Setting Method selected control according BYP/MS (Pin voltage. BYP/MS OPEN Control 3-wire 3-wire
During 3-wire control, transferred length (18, bits) automatically identified. During 19-bit transfer, frequency steps table below according combination BYP/MS voltage length. This does have fixed frequency division circuit, phase comparison frequency becomes frequency step. BYP/MS voltage OPEN OPEN OPEN Reference divider Selectable from Phase comparison frequency 62.5 31.25 62.5 kHz/ 50.0 kHz/ 31.25 50.0 50.0 Frequency step 62.5 31.25 62.5 kHz/ 50.0 kHz/ 31.25 50.0 50.0
Transfer length
Phase comparison frequency frequency step when crystal oscillation=4 MHz. -17-
CXA3250N
Programming lock frequency obtained according following formula. fosc=fref fosc local oscillator frequency fref phase comparison frequency main divider frequency division ratio swallow counter frequency division ratio variable frequency division ranges follows, binary. 1023 during 18-bit transfer)
Control This conforms standard format, bidirectional control possible consisting write mode which various data received read mode which various data sent. Write read modes recognized according setting final (R/W bit) address byte. Write mode when read mode when "1".
-18-
CXA3250N
3-1) Address settings four addresses selected hardware settings, that multiple exist within system. responding address according ADSW/CE voltage. Address
Hardware bits voltage OPEN
3-2) Write mode Write mode used receive various data. this mode, byte contains address data, bytes contain frequency data, byte contains control data, byte contains band switch data. These data latch transferred manner byte byte byte byte byte When correct address received acknowledged, data recognized frequency data first next byte "0", control data band switch data this "1". Also, when data transmission stopped part-way, previously programmed data valid. Therefore, once control band switch data have been programmed, 3-byte commands consisting address frequency data possible. Further, even stop conditions met, data input sending start conditions address.
-19-
CXA3250N
control format shown table below. Write-mode Slave Receiver bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
MODE Address byte Divider byte Divider byte Control byte Band byte Don't care
MA0,
Acknowledge address setting main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump (when "1") varicap output (when "1") charge pump current switching (200 when "1", when "0") band switch control (output transistor when "1") reference divider frequency division ratio setting. Reference Divider Frequency Division Ratio Table.
Reference Divider Frequency Division Ratio Table Don't care Reference divider
-20-
CXA3250N
3-3) Read mode read mode, phase comparator locked/unlocked status 5-level converter input voltage status transmitted output master. read data format shown table below. Read mode Slave Transmitter bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
MODE Address byte Status byte MA0,
Acknowledge address setting lock detection signal locked, unlocked) converter (See table below.)
5-level Converter Output Table Voltage applied LOCK/ADC VCC2 VCC2 0.45 VCC2 VCC2 VCC2 0.45 VCC2 0.15 VCC2 VCC2 0.15 VCC2
-21-
CXA3250N
3-Wire Control following transfer length formats automatically identified during 3-wire control. bits Band data bits) frequency data bits) bits Band data bits) frequency data bits) bits Band data bits) frequency data bits) test data bits) 4-1) 18-bit data transfer Data loaded rising edge clock signal while enable signal high, latched falling edge enable signal. clocks during enable period counted, when bits have been loaded, programmable divider "M9" data reference divider frequency division ratio automatically "1/80" when BYP/MS voltage "1/64" when BYP/MS open.
18-bit data format
Invalid data Band switch data DATA CLOCK Frequency data Invalid data
ENABLE Time Latch
4-2) 19-bit data transfer Data loaded rising edge clock signal while enable signal high, latched falling edge enable signal. clocks during enable period counted, when bits have been loaded, reference divider frequency division ratio automatically "1/80" when BYP/MS voltage "1/128" when BYP/MS open.
19-bit data format
Invalid data Band switch data DATA CLOCK Frequency data Invalid data
ENABLE Time Latch
-22-
CXA3250N
4-3) 27-bit data transfer 3-wire also automatically supports 27-bit format which various control data transferred addition band frequency data. Data loaded rising edge clock signal while enable signal high, latched falling edge enable signal. clocks during enable period counted, bits data counted from rising edge enable signal loaded valid data. 27-bit data format
Invalid data Band switch data DATA CLOCK Frequency data Test data Invalid data
ENABLE Time Latch
main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump (when "1") varicap output (when "1") charge pump current switching (200 when "1", when "0") band switch control (output transistor when "1") Reference divider frequency division ratio setting.
Reference Divider Frequency Division Ratio Table Don't care Reference divider
-23-
CXA3250N
Timing Chart
tWSTA
tSSTO
tSSTA
tHSTA START
tLOW
tHIGH
tSDAT
tHDAT STOP
CLOCK
DATACHANGE
tSSTA=Start setup time tWSTA=Start waiting time tHSTA=Start hold time tLOW=LOW clock pulse width tHIGH=HIGH clock pulse width
tSDAT=Data setup time tHDAT=Data hold time tSSTO=Stop setup time =Rise time =Fall time
3-Wire Timing Chart
DATA
1.5V
CLOCK
1.5V
ENABLE
1.5V
tSD=Data setup time tHD=Data hold time tSE=Enable setup time tHE=Enable hold time tWE=Enable waiting time
-24-
CXA3250N
Example Representative Characteristics
Circuit current Supply voltage DICC-Circuit current [mA] AICC-Circuit current [mA] Circuit current Supply voltage
VCC1-Supply voltage Band output voltage Output current (BS1, BS2, BS3, BS4) Output current [mA] characteristics (Untuned input)
VCC2-Supply voltage Band output voltage Output current Output current [mA] VCC3=5V VCC3=9V
VCC3=9V Output voltage
Output voltage
VCC3=5V
output level [dBm]
fRF=100MHz (VHF) fRF=450MHz (UHF) both f=45MHz
level [dBm]
-25-
CXA3250N
Conversion gain Reception frequency (Untuned input) fIF=45MHz CG-Conversion gain [dB]
Noise figure Reception frequency (Untuned input, DSB) fIF=45MHz
(Low)
NF-Noise figure [dB]
(Low) (High)
(High)
Reception frequency [MHz] Next adjacent cross modulation Reception frequency (Untuned input) CM-Cross modulation [dBµ] Reception frequency [MHz] fIF=45MHz fUD=fD+12MHz fUD=fD-12MHz (100kHz, 30%AM)
Reception frequency [MHz]
Oscillation frequency power supply fluctuation (PLL off) (Low) (High) drift [kHz] -100 -200 -300 -400 Oscillation frequency [MHz] VCC+5% VCC-5% (VCC=5V)
beat characteristics output level [dBm] output level [dBm] level) fLocal=129MHz fP=83.25MHz fC=86.83MHz (fP-12dB) fS=87.75MHz (fP-1.7dB) fIF=45.75MHz fBeat=fIF±920kHz
fBeat
-26-
CXA3250N
Tuning Response Time
(Low) 95MHz (High) 395MHz CP=1
T=34msec 5.0V/div offset 10.0V -40,0000ms 10,0000ms 10,0ms/div 60,0000ms real time
CP=0
T=68msec 5.0V/div offset 10.0V -130,000ms 20,0000ms 30,0ms/div 170,000ms real time
-27-
CXA3250N
Tuning Response Time
413MHz 847MHz CP=1
T=36msec 5.0V/div offset 10.0V -40,0000ms 10,0000ms 10,0ms/div 60,0000ms real time
CP=0
T=87msec 5.0V/div offset 10.0V -70,0000ms 30,0000ms 20,0ms/div 130,000ms real time
-28-
CXA3250N
Tuning Response Time
(High) 395MHz (Low) 95MHz CP=1 T=22msec
5.0V/div offset 10.0V -40,0000ms 10,0000ms 10,0ms/div 60,0000ms real time
CP=0
T=34msec
5.0V/div offset 10.0V -100,000ms 0,00000s 20,0ms/div 100,000ms real time
-29-
CXA3250N
Tuning Response Time
847MHz 413MHz CP=1
T=20msec 5.0V/div offset 10.0V -90,0000ms 10,0000ms 20,0ms/div 110,000ms real time
CP=0
T=50msec 5.0V/div offset 10.0V -100,000ms 0,00000s 20,0ms/div 100,000ms real time
-30-
CXA3250N
output spectrum 10dB/div
(Low) fRF=55MHz fL.0=100MHz input level -40dBm
CENTER 45.0MHz #RES 1.0kHz
#VBW 10Hz
SPAN 100.0kHz 30.0
output spectrum 10dB/div
(High) fRF=350MHz fL.0=395MHz input level -40dBm
CENTER 45.0MHz 1.0kHz
#VBW 10Hz
SPAN 100.0kHz 30.0
-31-
CXA3250N
output spectrum 10dB/div
fRF=800MHz fL.0=845MHz input level -40dBm
CENTER 45.0 270MHz #RES 1.0kHz
#VBW 10Hz
SPAN 100.0kHz 30.0
-32-
CXA3250N
Input Impedance
j100
BYP/MS
50MHz 1000p
VHFin UHFin2
350MHz -j100
-j25
-j50
Input Impedance
j100
350MHz
-j25
-j100 800MHz -j50
-33-
UHFin1
CXA3250N
Output Impedance
j100
45MHz 38MHz
-j25
-j100
-j50
-34-
CXA3250N
Package Outline
Unit
30PIN SSOP (PLASTIC)
1.25
0.10
0.22 0.05 0.13
0.65 0.05 0.15 0.02
NOTE: Dimension does include mold protrusion. DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-30P-L01 SSOP030-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g
NOTE PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
-35-

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