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APEX Devices Quartus Software: System-on-a-Programmable-Chip Solution
Designing system-level integration requires devices with density flexibility support design methodology enhance productivity. Altera's APEXdevice family Quartussoftware have launched this programmable logic design. With over million typical gates (2.67 million system gates), APEX devices first PLDs designed with MultiCorearchitecture, which integrates RAM, product-term logic, look-up table (LUT) logic single device. meet challenges designing multimillion-gate devices, powerful Quartus software offers features never before seen
Figure APEX Device Architecture
64-Bit, 66-MHz Flexible Continuous Interconnect Column FastTrack Interconnect MegaLAB Interconnect Local Interconnect Embedded Embedded Dual-Port Embedded First-In-First-Out (FIFO) Buffer IEEE Std. 1149.1 (JTAG) Controller SignalTap Interface MultiVolt Phase-Locked Loop (PLL) User-Selectable Embedded Content-Addressable Memory (CAM) Embedded Product-Term Support Embedded Array Logic Array
programmable logic development tool. Together, APEX devices Quartus software offer designers ideal solution implementing high-performance
Matching Architecture Software
Altera's high-density, high-performance APEX MultiCore architecture designed systemlevel integration (see Figure MultiCore architecture combines logic, product-term logic, memory features into embedded architecture. Designers integrate complex system design onto single APEX device,
Inside This Issue:
Simplified Designs through Selectable Standards, Design Tips: Hierarchical Instantiation Organizes Your Design,
continued page
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SignalTap Embedded Logic Analyzer,
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APEXDevice Family Offering Million Gates
Cutting-Edge Software
Quartusand MAX+PLUS® Software Industry's Best Development Tools
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Table
Contents
FineLine Packages Coming Soon FLEX 6000 Devices 7000S Device Availability 7000A Device Availability 7000B Device 3000A Devices Download Quartus Preview Today Quartus Simulator Features Quartus Static Timing Analyzer Features Quartus License Files MAX+PLUS BASELINE Version 9.23 Available Discontinued Devices Update Technical Articles Simplified Designs through Selectable Standards Accelerates Applications APEX Devices Design Tips: Hierarchical Instantiation Organizes Your Design Questions Answers Every Issue Current Software Version Altera Publications Altera Programming Support Altera Device Selection Guide Contact Altera.
Features APEX Devices Quartus Software: System-on-a-Programmable-Chip Solution Customer Application: Bright Star Engineering FLEX 6000 Devices Connect Products Internet Altera News $20K APEX Provides SDRAM Controller Integration with PCI/C Synplify/Quartus Integration Streamlines APEX Designs Design Flows SignalTap Embedded Logic Analyzer Provides Visibility Internal Signals Altera Tools Training Program Other Interface Megafunctions Devices Tools EP20K400 Devices Available 0.22-µm EPF10K100E Devices Available Introducing EPF10K200S EPF10K50S Devices Software Support FLEX 10KE Packages FLEX Device Availability FLEX Product Transitions FLEX 10KE Industrial-Temperature Devices FLEX 10KE Devices Available with PLLs Industrial-Temperature FLEX 6000 Devices Available
Altera, APEX, APEX 20K, ASCEND, ACCESS, AMPP, BitBlaster, ByteBlaster, ByteBlasterMV, Classic, ClockBoost, ClockLock, ClockShift, CoreSyn, EPC2, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Jam, MasterBlaster, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 7000AE, 7000B, 5000, 3000A, MAX, MAX+PLUS, MAX+PLUS MegaCore, MegaLAB, MegaWizard, MultiCore, MultiVolt, NativeLink, nSTEP, OpenCore, Quartus, SignalTap, System-on-a-Programmable-Chip, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Boulder Creek Engineering registered trademark Boulder Creek Engineering. Bright Star Engineering registered trademark Bright Star Engineering, Inc. Motorola registered trademark Motorola, Inc. Northwest Logic Design registered trademark Northwest Logic Design. Palm trademark 3Com Corporation. Rochester Electronics registered trademark Rochester Electronics, Inc. Synplicity Synplify registered trademarks Synplicity, Inc. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. actual availability Altera's products features could differ from those projected this publication provided solely estimate reader. Copyright 1999 Altera Corporation. rights reserved. Printed recycled paper.
Erica Heidinger, Publisher Greg Steinke, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 n_v@altera.com
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Features APEX Devices Quartus Software: Systemon-a-Programmable-Chip Solution, continued from page eliminating need multiple devices. only does APEX architecture save valuable board space, also simplifies design implementation. APEX architecture composed series MegaLABstructures connected fast, continuous FastTrack® Interconnect. Each MegaLAB structure contains logic array blocks (LABs), embedded system block (ESB), MegaLAB local interconnect that connects LABs ESB. configured logic, product-term logic, memory, including dual-port RAM, first-in first-out (FIFO) buffers, ROM, contentaddressable memory (CAM). ensure that logic mapped correctly APEX architecture, Quartus Compiler uses CoreSyncapability. Compiler analyzes design implements functions using optimal technology that block: LUT-based logic elements, product-term-based macrocells, ESBs APEX architecture. shown Figure logic options block-by-block. Assignment Organizer allows designer specify whether blocks
Figure Technology Mapper Quartus Software
modules project hierarchy should mapped logic, product-term logic, memory. Alternatively, designers AUTO mode Quartus Technology Mapper, which instructs Quartus software determine best implementation.
Attaining Clock Rates
help designers verify performance their APEX designs, Quartus software offers extensive timing information. Timing analysis performed automatically during each compilation because Timing Analyzer incorporated into Quartus Compiler. Designers monitor device's actual system operating frequency, internal operating frequency, other timing parameters. System fMAX takes into account times external devices well offchip delays (where they have been specified). Figure page shows fMAX design displayed Quartus Report Window. increase system clock rates, APEX devices feature four phase-locked loops (PLLs) with output frequencies reaching MHz. These PLLs support performance-based ClockLockTM, ClockBoostTM, ClockShiftclock management circuitry. ClockLock circuitry reduces clock delay skew minimizes clock-to-output times while maintaining zero hold times. ClockBoost circuitry offers flexible-rate clock multiplication division. ClockShift circuitry allows clock phase delay adjusted. These features provide significant improvements system performance bandwidth. Quartus Timing Analyzer supports APEX clock management circuitry perform timing analysis designs with multiple related clocks.
APEX Devices: First PLDs with
APEX device family first programmable logic device (PLD) family offer CAM. When mode, APEX implements 32-word, 32-bit CAM. Wider deeper CAMs implemented combining multiple CAMs. create larger CAMs, CoreSyn synthesis capability Quartus software automatically combines ESBs necessary logic elements (LEs). Because logic integrated into
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Features device, APEX provides much faster system performance than traditional discrete CAM. APEX accelerates fast search applications integrating parallel comparators into single block eliminating on-chip offchip delays.
Figure System fMAX Quartus Software
Million-Gate Designs Require Innovative Approaches
Because their density performance, APEX devices give designers flexibility address much larger designs broader range applications than traditionally possible PLDs. However, deal with such density bring complex designs market time, teams designers often need work separate sections project. Quartus software designed specifically collaborative design projects. Integrated into Quartus software centralized object-oriented database that accessed multiple engineers across network. Quartus software lets industrystandard revision control systems track changes each project file link them database. Users check files, work them, then check them back documenting changes that have been made. tracks users changes they make file. Using revision control system together with Quartus software safeguards integrity project; users cannot overwrite work others, changes documented, easy roll back previous version design need arises. Another consideration when designing large devices time needed full compilation. Complex designs often require several iterations before desired results achieved. Quartus software includes features speed design processing: multi-processor support nSTEPCompiler. Quartus software designed from start multi-processor support. Processorintensive tasks like compilation distributed multiple processors locally, across network, across multiple operating systems. Tying together power several workstations considerably reduce time needed compilation.
Before Quartus software, each design iteration required full compilation. Now, nSTEP Compiler permits incremental recompilation. Designers make changes obtain results without running full compilation without affecting placement timing rest design. This process allows easily evaluate changes, saving valuable time.
LVDS Support
APEX devices offer support multiple highbandwidth, low-voltage interfacing standards. APEX family first family support low-voltage differential signaling (LVDS) standard with performance Mbits second. Other standards supported APEX devices include low-voltage transistor-to-transistor logic (LVTTL), stubseries terminated logic (SSTL-3/2), advanced graphics port (AGP), high-speed transceiver logic (HSTL), Gunning transceiver logic (GTL+). Designers Quartus software specify high-speed interfaces between SDRAMs, processors, system backplanes APEX devices achieve desired performance.
APEX JTAG Circuitry Connects SignalTap Embedded Logic Analyzer
verification multi-million gate designs most time-consuming part design continued page
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Features APEX Devices Quartus Software: Systemon-a-Programmable-Chip Solution, continued from page process. However, APEX device family Quartus software simplify process reduce verification time. APEX device family dedicated IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that used monitor internal logic operation devices with software-implemented Quartus SignalTaplogic analyzer (see Figure SignalTap logic analyzer allows designers perform hardware debugging while circuit running speed, significantly enhancing board-level verification process. MasterBlastercommunications cable connects platform running Quartus software printed circuit board (PCB), allowing SignalTap
Figure SignalTap Embedded Logic Analyzer
logic analyzer monitor APEX device. details SignalTap logic analyzer, "SignalTap Embedded Logic Analyzer Provides Visibility Internal Signals" page
Conclusion
powerful features Quartus software allow designers realize full potential state-of-the-art APEX devices, shortening design time increasing productivity. Together, Altera's Quartus software APEX devices provide real solution implementing System-on-a- Programmable-Chip designs. APEX devices Quartus software available now. further details, visit Altera site (http://www.altera.com) contact your local sales representative.
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Devices
APEX
Tools APEX devices fully 64-bit, 66-MHz peripheral component interconnect (PCI) compliant deliver clock rates MHz. EP20K400 device phaselocked loop (PLL), which features enhanced ClockLockand ClockBoostcircuitry. circuitry offers multiplication over extended frequency range. device also provides MultiVoltI/O interface, which ideal mixed-voltage systems, supports hot-socketing. EP20K400 devices available 652-pin ball-grid array (BGA) 655-pin pin-grid array (PGA) packages, will available soon 672-pin FineLine BGApackage. latest information APEX devices, Altera site http://www.altera.com.
EP20K400 Devices Available
first APEXdevice available (see Table 400,000-gate million maximum system gates) EP20K400 device features MultiCorearchitecture, which includes integrated look-up table (LUT) logic, productterm logic, flexible memory. APEX MultiCore architecture offers designers complete system-level integration single device, eliminating need multiple devices, saving board space, simplifying implementation complex designs. flexible memory structure supports dual-port with independent read/write ports, synchronous asynchronous operation, 161-MHz first-in first-out (FIFO) performance wide range widths depths.
Table APEX Device Availability Device
EP20K100
FLEX
0.22-µm EPF10K100E Devices Available
EPF10K100E devices available. These devices state-of-the-art 0.22-µm, 5-layermetal process that provides high-performance low-power advantages. addition 4,992 logic elements (LEs) 49,152 bits on-chip dual-port RAM, EPF10K100E devices also feature programmable delay support 64-bit, 66-MHz compliance improved pin-to-pin timing. EPF10K100E devices offered 208-pin PQFP, 240-pin PQFP, 256-pin FineLine BGA, 484-pin FineLine BGA, 356-pin packages.
Package
144-pin TQFP 208-pin PQFP 240-pin PQFP 196-pin FineLine 324-pin FineLine 356-pin
Availability
June 1999
1999
EP20K200
208-pin RQFP 240-pin RQFP 356-pin 484-pin FineLine
1999
EP20K400
652-pin 655-pin 672-pin FineLine
1999 1999
EP20K400E
208-pin RQFP 240-pin RQFP 652-pin 672-pin FineLine
1999
Introducing EPF10K200S EPF10K50S Devices
Enhanced versions EPF10K200E EPF10K50E devices, called EPF10K200S EPF10K50S devices, respectively, include migration from 0.25-µm process 0.22-µm process increased performance lower power consumption, programmable delay provide full 64-bit, 66-MHz compliance. (EPF10K100E, EPF10K130E, EPF10K30E devices feature programmable delay
EP20K600E
652-pin 672-pin FineLine 784-pin FineLine
1999
EP20K1000E
784-pin FineLine 984-pin
1999
Note: PQFP: plastic quad flat pack, RQFP: power quad flat pack, TQFP: thin quad flat pack.
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Devices Tools Devices Tools, continued from page
fabricated 0.22-µm process.) EPF10K200S EPF10K50S devices offer ClockLock ClockBoost features. addition 600-pin 672-pin FineLine packages already offered EPF10K200E devices, EPF10K200S devices will offered 240-pin RQFP, 356-pin BGA, 484-pin FineLine packages. EPF10K50S devices will available same packages EPF10K50E device. Advanced support EPF10K200S EPF10K50S devices available MAX+PLUS software version 9.24.
process. Additionally, selected 5.0-V FLEX devices moving from 0.50-µm process 0.42-µm process. Table outlines process migration schedule lists reference documentation associated with this migration. download these documents from Customer Notifications page Altera site http://www.altera.com.
FLEX 10KE Industrial-Temperature Devices
Table lists availability industrialtemperature FLEX 10KE devices.
Table FLEX 10KE Availability Device Package
144-pin TQFP 208-pin PQFP 256-pin FBGA 484-pin FBGA EPF10K50E 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin 484-pin FBGA
Software Support FLEX 10KE Packages
Altera offering many device-package combinations, including 1.27-mm packages cost efficient quad flat pack (QFP) packages. Advanced software support shown Table obtain software updates from Altera site http://www.altera.com.
Table FLEX 10KE Device Software Support Device Package MAX+PLUS Software Version
9.23 9.23 9.23 9.24 9.25 9.25
Speed Grade
Availability
July July August August August July July July September August August June June June
EPF10K30E
EPF10K50S
144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin 484-pin FBGA
EPF10K50S EPF10K130E EPF10K130E EPF10K200S EPF10K200S EPF10K200S
356-pin 356-pin 600-pin 240-pin RQFP 356-pin 484-pin FineLine
EPF10K100E 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin 484-pin FBGA
EPF10K130E 240-pin PQFP 356-pin 484-pin FBGA 600-pin 672-pin FBGA EPF10K200E 599-pin 600-pin 672-pin FBGA EPF10K200S 240-pin RQFP 356-pin 484-pin FBGA 600-pin 672-pin FBGA
June June June June June August August August August
FLEX Device Availability
With introduction EPF10K50V devices 484-pin FineLine packages, FLEX® 10KA devices have been introduced. Table shows expected availability 2.5-V FLEX 10KE devices. MAX+PLUS® design support currently available device package options.
FLEX Product Transitions
Altera migrating selected 3.3-V FLEX 10KA devices from 0.35-µm process 0.30-µm
Notes: FBGA: FineLine packages. dates refer calendar-year 1999.
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Devices Tools
FLEX 10KE Devices Available with PLLs
FLEX 10KE devices will offered with feature speed grades. These devices will have "-X" suffix (e.g., EPF10K200EBC600-1X). Table lists availability FLEX 10KE devices with PLLs.
Table FLEX Device Migration Device Core Voltage
Industrial-Temperature FLEX 6000 Devices Available
Altera provides broad range FLEX 6000 devices industrial-temperature grades. Seven device package combinations shipping variety packages, including TQFP, PQFP, packages. Table lists available industrialtemperature grade FLEX 6000 devices. FLEX 10KE devices will offered with feature speed grades.
Date
Reference Process (µm)
9810 0.30
FineLine Packages Coming Soon FLEX 6000 Devices
FLEX 6000 devices FineLine packages planned available August 1999. These area-efficient packages require less than half board space traditional packages. Table page shows FLEX 6000 device expected availability.
Table FLEX 10KE Devices with PLLs Device
EPF10K30E
EPF10K10A
July 1999
EPF10K30A EPF10K50V EPF10K100A EPF10K10
Done Done Done
9810 9810 9810
0.30 0.30 0.30 0.42
October 9901 1999 9909 9901 9909 9901 9909
EPF10K20
July 1999
0.42
EPF10K30
July 1999
0.42
Package
144-pin TQFP, 208-pin PQFP, 256-pin FBGA, 484-pin FBGA
Availability
August 1999 August 1999 Sept. 1999 July 1999 August 1999 August 1999
EPF10K40
October 9901 1999 9909 9901 9909
0.42
EPF10K50S
0.42
144-pin TQFP, 208-pin PQFP, 240-pin PQFP, 356-pin 256-pin FBGA, 484-pin FBGA
EPF10K50
July 1999
EPF10K70
October 9901 1999 9909
0.42
EPF10K100E 208-pin PQFP, 240-pin PQFP 256-pin FBGA, 356-pin BGA,
EPF10K100
October 9901 1999 9909
0.42
484-pin FBGA EPF10K130E 240-pin PQFP, 356-pin BGA, 484-pin FBGA, 600-pin BGA, 672-pin FBGA EPF10K200S 240-pin RQFP, 356-pin BGA, 484-pin FBGA, 600-pin BGA, 672-pin FBGA
Table FLEX 10KE Industrial-Temperature Device Availability Device
EPF10K50ETI144-2 EPF10K50EQI240-2 EPF10K50EFI256-2 EPF10K50SQI208-2 EPF10K50SBI356-2 EPF10K50SFI484-2 EPF10K100EQI208-2 EPF10K100EFI256-2 EPF10K100EFI484-2 EPF10K130EQI240-2 EPF10K130EBI356-2 EPF10K130EFI484-2 EPF10K200EBI600-2 EPF10K200SRI240-2 EPF10K200SBI356-2 EPF10K200SFI672-2
Sept. 1999
Availability
1999 1999 1999 1999 1999 1999 1999 1999 1999 1999 1999
Note: FBGA: FineLine packages.
Table Industrial-Temperature FLEX 6000 Device Availability Device
EPF6016TI144-3 EPF6016QI208-3 EPF6016ATI100-2 EPF6016ATI144-3 EPF6016AQI208-3 EPF6024AQI208-3 EPF6024ABI256-2
Package
144-pin TQFP 208-pin PQFP 100-pin TQFP 144-pin TQFP 208-pin PQFP 208-pin PQFP 256-pin
Availability
continued page
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Devices Tools Devices Tools, continued from page
Table FLEX 6000 Device Availability Package EPF6010A
100-pin TQFP 100-pin FineLine 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin 256-pin FineLine August 1999 August 1999 August 1999
7000A Device Availability
7000A devices available. 7000A devices range from macrocells with propagation delays fast 7000A devices support ISP, MultiVolt pins, hot-socketing, compatibility with industry-standard 7000 devices. 7000A devices available industrial-temperature grades. Table shows 7000A device commercial package speed grade options.
Table 7000A Commercial-Temperature Device Packages Device
EPM7032AE
Device EPF6016 EPF6016A
August 1999 August 1999
EPF6024A
Package
44-pin PLCC 44-pin TQFP
Speed Grade
-10, -10, -10, -10, -10,
7000S Device Availability
MAX® 7000S devices available. These devices feature speed grades insystem programmability (ISP), open-drain output option, IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry devices with more macrocells. 7000S devices available industrial-temperature grades. Table shows packages speed grades available commercial-temperature grade.
EPM7064AE
44-pin PLCC 44-pin TQFP 100-pin TQFP 100-pin FineLine
EPM7128A
84-pin PLCC 100-pin TQFP 100-pin FineLine 144-pin TQFP 256-pin FineLine
EPM7128AE
84-pin PLCC 100-pin TQFP 100-pin PQFP 144-pin TQFP 256-pin FineLine
EPM7256A
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin FineLine
-10, -10, -10, -10, -10, -10, -10, -10,
Table Commercial-Temperature 7000S Device Packages Device
EPM7032S
Package
44-pin PLCC 44-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10,
EPM7256AE
100-pin TQFP 100-pin FineLine 144-pin TQFP 208-pin PQFP 256-pin FineLine
EPM7064S
44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
EPM7512AE
144-pin TQFP 208-pin PQFP 256-pin 256-pin FineLine
EPM7128S
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP
7000B Device
7000B devices 2.5-V, product-term-based programmable logic devices (PLDs). devices support standards, such Gunning transceiver logic (GTL+), stub-series terminated logicAltera Corporation News Views 1999
EPM7160S
84-pin PLCC 100-pin TQFP 160-pin PQFP
EPM7192S EPM7256S
160-pin PQFP 208-pin PQFP
Devices Tools (SSTL-) SSTL-3, offer propagation delays fast range density from macrocells (see Table 11). 7000B devices support ISP, MultiVolt pins, socketing, compatibility with industry-standard 7000 devices.
Table 7000B Commercial-Temperature Device Packages Device
EPM7032B
TOOLS
Download Quartus Preview Today
early look Altera's fourth-generation design software visit Altera site http://www.altera.com download Quartus Preview. Quartus Preview presents self-running demos Quartus software's latest features. Quartus Preview demonstrates seamless integration NativeLinkfeature accelerated verification process using SignalTapembedded logic analyzer. also ease submitting service request Altera Applications directly from Quartus software, first fully Internet-aware software. device densities increase, design methodologies PLDs must continue evolve. Download Quartus Preview first-hand Quartus software reshaping programmable logic design.
Package
44-pin PLCC 44-pin TQFP
Speed Grade
EPM7064B
44-pin PLCC 44-pin TQFP 100-pin FineLine 100-pin TQFP
EPM7128B
100-pin FineLine 100-pin TQFP 144-pin TQFP 256-pin FineLine
EPM7256B
100-pin FineLine 100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin FineLine
Quartus Simulator Features
Quartus Simulator several features, including support testbenches. Simulator supports both waveform entry (which provides compatibility with existing MAX+PLUS simulation files) testbench entry. multiple time bars Waveform Editor. Quartus Simulator supports nine different signal level values DC). Node Finder allows users create customized filters extract nodes from post-synthesis floorplan netlist, making easy locate nodes. Node Finder also output pins Vector Waveform Files (.vwf) check output values against expected values simulation. continued page
EPM7512B
144-pin TQFP 208-pin PQFP 256-pin FineLine
3000A Devices
3000A device family 3.3-V product-term-based family targeted high-volume, low-cost applications. devices have enhanced support densities from macrocells (see Table 12). With propagation delays fast 3000A devices provide customers with highest performance lowest price macrocell.
Table 3000A Devices Device
EPM3032A
Package
44-pin PLCC 44-pin TQFP
Speed Grade
EPM3064A
44-pin PLCC 44-pin TQFP 100-pin TQFP
EPM3128A
100-pin TQFP 144-pin PQFP
EPM3256A
144-pin TQFP 208-pin PQFP
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Devices Tools Devices Tools, continued from page Quartus software users with current software subscription. your license.dat file Quartus FEATURE line, your license will enable Quartus software. Figure shows sample license file that enables both Quartus MAX+PLUS software. have current software subscription, obtain license file that enables both Quartus MAX+PLUS software from Altera web-based license server http://www.altera.com.
Quartus Static Timing Analyzer Features
Quartus static Timing Analyzer several features. Multi-clock frequency analysis allows analyze timing designs containing register-to-register paths that controlled different clocks. ability detect combinatorial loops drastically reduces analysis times designs that contain combinatorial loops. Timing Analyzer display either system fMAX internal fMAX. system fMAX ability include delays device. Timing critical paths broken down into data path, clock path, setup time. Each delay path also broken down into increments. perform pin-to-pin combinatorial timing analysis. This process analogous delay matrix MAX+PLUS software.
MAX+PLUS BASELINE Version 9.23 Available
MAX+PLUS BASELINE software version 9.23 includes full-featured functional timing gate-level simulator, making industry's complete free development software. software available free download from Altera site http://www.altera.com. MAX+PLUS BASELINE software version 9.23 supports wide range programmable logic devices including EPF10K10, EPF10K10A, EPM9320, EPM9320A, EPF8452A, EPF8282A, EPF6010A, EPF6016, EPF6016A, 7000, 7000E, 7000S, 7000A, 7000AE, 5000, Classic devices. Features supported include schematic text-based (AHDL) design entry; full-featured timing simulation, static timing analysis. ideal development tool low- mid-density programmable logic design.
Quartus License Files
have current software subscription, will automatically receive Quartus software when released. However, need license file enable software. ensure smooth transition release Quartus software, April 1999, Altera web-based license server started issuing license files that enable both MAX+PLUS
Figure Example License File
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Technical
Articles
622-MBPS data rates. APEX 20KE devices first programmable logic devices (PLDs) support low-voltage differential signaling (LVDS) standard. Combined with highest densities available, APEX devices perfect programmable solution. Programmable standards help simplify your board design. example, need dedicated devices such LVDS drivers interface APEX PLDs backplanes. With programmable standards supported APEX 20KE devices, single device interface with highspeed, low-voltage memory buses backplanes.
Simplified Designs through Selectable Standards
High-performance, low-voltage standards have been introduced into market keep pace with increasing clock speeds lowvoltage levels. These standards must support memory, microprocessors, backplanes, peripheral devices. Designers want these standards with programmable logic need flexible, high-performance, multi-standard buffers. Altera's revolutionary APEX20KE devices meet this challenge providing highest density, highest performance programmable logic solution with necessary standards communication computer industries. With programmable standards supported APEX 20KE devices, single device interface with high-speed, lowvoltage memory buses backplanes
Table APEX 20KE Supported Standards Standard
LVTTL LVCMOS LVDS GTL+ SSTL-2 Class SSTL-3 Class HSTL Class HSTL Class HSTL Class HSTL Class
Supported APEX 20KE Standards
APEX 20KE blocks support standards. APEX 20KE buffers meet voltage, drive strength, characteristics necessary comply with standards listed Table
Type
Single-ended Single-ended Single-ended Single-ended Single-ended Differential Open-drain Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced
Reference Voltage (VREF)
1.25 0.75 0.75 1.32
Output Supply Voltage (VCCIO)
Board Termination Voltage (VTT)
1.25 0.75 0.75
Notes: AGP: advanced graphics port, CTT: center-tap-terminated, GTL+: Gunning transceiver logic, HSTL: high-speed transceiver logic, LVCMOS: low-voltage complementary metal-oxide semiconductor, LVTTL: low-voltage transistor-to-transistor logic, PCI: peripheral component interconnect, SSTL: stub-series terminated logic. values shown VREF, VCCIO, typical values.
continued page
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Technical Articles Simplified Designs through Selectable Standards, continued from page APEX 20KE devices have programmable blocks dedicated LVDS blocks. LVDS blocks also support other standard. Figure shows representation blocks.
Figure APEX 20KE Blocks
LVDS
LVDS standard high-speed, lowvoltage swing, low-power, general-purpose interface standard that independent process architecture. LVDS requires differential input, does need input reference voltage. Typical uses LVDS interfaces high-bandwidth data transfer, backplane driver, clock distribution applications. industry standards define LVDS: IEEE Std. 1596.3 SCI-LVDS ANSI/TIA/EIA-644. Both standards have similar features, IEEE standard supports maximum data transfer MBPS. APEX 20KE devices designed meet ANSI/TIA/EIA-644 standard MBPS.
Individual Power
LVDS Output Block
Regular Blocks GTL+ HSTL Class III, LVCMOS LVTTL 3.3-V SSTL-2 Class SSTL-3 Class
LVDS Input Block
Conclusion
Individual Power
programmable blocks have individual power planes with separate VCCIO pins each block. Each VCCIO plane supports 3.3-V, 2.5-V, 1.8-V levels.
Altera remains programmable solutions leader offering devices that meet designers' needs. standards features allow programmers interface APEX 20KE devices directly with microprocessors, memory devices, backplanes, without using interface logic. This process saves board space, decreases timeto-market, increases profits.
Accelerates Applications APEX Devices
Most memory devices store retrieve data addressing specific memory locations. Searching item memory take many clock cycles. time required find item stored memory reduced identified access data content, rather than address. Content-addressable memory (CAM) works this way, making ideal high-speed search applications. Altera® APEX20KE devices contain integrated blocks CAM. implemented individual device. designer wanted device their printed circuit board (PCB), which increased design time reduced amount useable space. Discrete also reduced system performance because introduced additional on-chip off-chip delays. APEX 20KE devices, which contain on-chip CAM, eliminate disadvantages discrete CAM. Because embedded inside APEX 20KE devices, provides faster system performance than traditional discrete CAM.
Because embedded inside APEX 20KE devices, provides faster system performance than traditional discrete CAM.
Integration
Traditionally, most applications have used discrete CAM, which
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Technical Articles
Using APEX 20KE
Each embedded system block (ESB) APEX 20KE devices implement 32-word 32-bit CAM. searches data parallel flags address which particular word stored. pre-loaded with data during configuration, written during system operation. design write "don't care" bits into words CAM; bits "don't care" affect matching. Output from either encoded unencoded. output encoded address data location, which better suited designs without duplicate data memory. Reading this type output only takes clock cycle. Figure
Figure Encoded Outputs
addr[] data[] Match addr[4.0] Encoded Outputs
Internet Protocol Filters Applications
Data Compression Data compression removes redundancy piece information, producing equivalent shorter message (see Figure lookup performed after each word presented. specific code found CAM, another word shifted When code found, outputs appropriate symbol input register flushed. generates result single transaction regardless table size length search list.
Figure Data Compression Using Tokens
Token
used optimize telecommunications, file-storage management, table look-up, pattern recognition, other applications.
Contents Uncompressed Data Compressed Data
Address
Data
Sequence
data[31.0]
Switch Applications necessary duplicate data written multiple locations, unencoded output should used. this mode, uses outputs reads outputs cycles, bits each cycle, 32-bit word line. Each output represents word goes high data matches that word CAM. Figure
Figure Unencoded Outputs
data[31.0]
2712 9743 7461
used switch applications extract process address information from incoming packets. switch packet correct outgoing port, incoming network address compared with table network addresses stored CAM. outputs destination each data packet. Figure
Figure Network Switch
Unencoded Outputs
6541
Switch
9811 Network Address
Applications
used optimize telecommunications, file-storage management, table look-up, pattern recognition, other applications. This section describes APEX used following applications: Data Compression Network Switches
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Contents Address
Port
Data
6541 2712 9743 7461 9811
continued page
1999
Design
Tips
Hierarchical Instantiation Organizes Your Design
Hierarchical instantiation plays particularly large role VHDL designs large digital designs. should consider using hierarchical design methodology maximize your design's effectiveness focus your project. Hierarchical instantiation involves dividing projects into extensive tree smaller design entities. Each entity specific purpose carefully declared method interacting with other entities. principal benefit hierarchical instantiation organization. Each block serves specific purpose considered entity, allowing designers focus design functionality time. This design technique also permits high-level view design's overall structure, making easier uncover critical paths potential trouble spots. well-defined purpose carefully monitored fully documented.
This article last four-part series that discusses practical design tips from Altera Applications, focuses importance hierarchical instantiation.
Error Detection
Hierarchical instantiation facilitate error detection assembled projects. Simulated nodes easier find because they referenced their hierarchical location. Critical paths timing analysis also stand out, especially within parallel modules that instantiated multiple locations.
Hierarchical Methodologies
fundamental design practices critical hierarchical design include top-down design bottom-up design methodology. Both methodologies contain their strengths break large designs into more manageable pieces. best designs often mixture these design methodologies. Top-Down Designs Top-down designs start with high-level understanding design's overall flow. Each design block's general functionality described prior developing building blocks themselves. Top-down methodologies tend create more organized designs, because designers must first evaluate design's overall structure. addition, focusing structure leaving details design undefined, designers delay technical considerations until they more manageable levels. Bottom-Up Designs bottom-up methodology, designers first create lower-level blocks then integrate these blocks into higher-level structures. Designers focus their attention individual
Labor Division
Well-divided projects lend themselves proper labor division. Designers must often split project between multiple engineers, welldefined barriers ease this task. Designers easily separate projects assign sections individual attention.
Documentation Revision Control
organized nature hierarchical designs creates benefits documentation revision control. Individual, well-focused modules lead creation complete documentation describing each block's functionality interfaces with others. Thorough documentation also aids debugging process helps bring engineers speed quickly. Revision control also improved, because each change serves
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Design Tips sub-blocks rather than design whole. Thus, individual blocks verified prior building entire design. Bottom-up designs also highlight benefits reusable code. Splitting projects into smaller modules helps designers find redundant sections project. Designers then reuse individual blocks code, which saves time. addition, designers assemble commonly used functions into their regular design library, allowing blocks code reused from project project. Re-useable code also lends itself more efficient synthesis, seen third article this series, Using Arithmetic Operators MAX+PLUS VHDL. that example, careful placement multiplexers allowed adder module where might have been required otherwise. However, adder located instantiated block, would have been difficult discern this optimization. Finally, parameterizable code enhance design reuse. creating parameterizable code, specific blocks targeted multiple uses same design. This ability what makes library parameterized modules (LPM) functions, well numerous Altera functions, effective. more information creating effective hierarchical design, contact Altera Applications sos@altera.com (800) 800-EPLD.
Designers assemble commonly used functions into their regular design library, allowing blocks code reused from project project.
Accelerates Applications APEX Devices, continued from page Internet Protocol Filters Internet protocol filter security feature that allows keep unauthorized users from accessing local-area network (LAN) resources. feature also restrict Internet protocol traffic over wide-area network (WAN) link. With Internet protocol filter, users restricted specific applications Internet (such e-mail). works filter block access except packets that have permission. addresses with certain permissions written into CAM; when address sent memory, reports whether contains address. address resides within CAM, permission particular activity. Figure Applications power-up, peripheral component interconnect (PCI) must configured that each device's memory functions occupy mutually exclusive address ranges. Therefore, system must able detect
Figure Using Filter
Contents Address
Data
Routed Packet
Permission
Permit Permit Denied Denied
many memory address ranges device requires size each. base address registers permit this relocation provide mechanism mapping devices into address spaces. Each interface have registers. used report which register being accessed. Using application speeds register search, while using fewer logic elements (LEs).
Speeds Applications
Altera's APEX devices have integrated into architecture. searching data instead location, minimizes search times, allowing designers make full APEX device speed features.
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Customer
Application
Bright Star Engineering FLEX 6000 Devices Connect Products Internet
Internet revolution entering phase. Manufacturers everywhere want their embedded products "network-enabled"-that have ability connect Internet. Users communicate with product that linked Internet through their browser from anywhere world, offering significant benefits wide range applications. example, engineer troubleshoot networkenabled manufacturing equipment, solve problems, production back track- from remote location using laptop. With network-enabled diagnostic equipment, doctor evaluate vital data give qualified advice patient hundreds miles away. large portion lives will soon affected addition network-enabled products. Although adding network connectivity product enticing, expensive time-consuming, especially manufacturer chooses develop hardware software house. Development long-term maintenance costs prohibitive, crucial time-to-market advantages lost. Bright Star Engineering (BSE) developed solution eliminate these problems: ipEngine-1. ipEngine-1 miniature network computer board that comes complete with hardware, software, development environment required networkenable product. Altera® FLEX® 6000 device integral piece this product, shown Figure
"Unlike traditional board-level products with fixed interfaces, ipEngine-1 capable adapting itself user's hardware requirements. Altera EPF6016 device provides extraordinary flexibility." Stuart Adams, President, Bright Star Engineering
Credit-Card-Size Board with Built-in Operating System Server
ipEngine-1 network computer uses Motorola PowerPC MPC823 processor central processing unit (CPU). This device board only inches wide inches long (see Figure processor features variety on-chip peripherals including: 10Base-T Ethernet interface Universal serial (USB) host/slave controller serial ports Liquid-crystal display (LCD) video controller serial
Figure ipEngine-1 Compares Size Credit Card
MPC823 processor also supports variety low-power operating modes, making suitable battery-powered applications. ipEngine-1 16-Mbyte DRAM 2-Mbyte FLASH memory system provide storage operating system well original equipment manufacturer's (OEM's) application software data. users need real-time operating system, ipEngine-1 ensures full connectivity from PowerPC processor local area networks (LANs) Internet. ipEngine-1 includes POSIX-based pKernel real-time network operating system (OS). pKernel integrate following elements:
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Customer Application TCP-IP networking Embedded Apache server Local file system Access Internet files HTTP Interactive command shell Software development small network-command-processor module PowerPC processor that translates network commands into matrix keyboard "presses." matrix keyboard information then sent through EPF6016 virtual interface control device. product ready.
Alternatively, those prefer non-realtime Embedded Linux configuration fits full Linux kernel plus network utilities, Apache server, Java Virtual Machine into ipEngine-1 onboard FLASH memory.
Altera EPF6016 Device Provides Extraordinary Flexibility
external interface from ipEngine-1 product, chose Altera EPF6016QC240-3 programmable logic device (PLD). "Unlike traditional board-level products with fixed interfaces, ipEngine-1 capable adapting itself user's hardware requirements. Altera EPF6016 device provides extraordinary flexibility," said Stuart Adams, President BSE. been working with Altera devices several years appreciates abundance features cost. company chose EPF6016 device ipEngine-1 primarily because these continued page
Using ipEngine-1
ipEngine-1 makes converting existing product into network-enabled simple, two-step process. example, manufacturer might want re-work small control device with matrix keypad into with network command interface. first step remove original matrix keypad, define virtual matrix keypad EPF6016 device, connect connector pins keypad input product. second step write
Figure ipEngine-1 Architecture
To/From Debug
To/From Clocks
XTAL CLOCK_GEN
Switching Power Supply
LCD_CTRL
Motorola MPC823
Universal Serial
Ethernet
Serial1
Serial2 EPF6016 Device Hardware Interface
XCVR FLASH XCVR
RS-232
DRAM
64KB Synchronous SRAM
RS-232
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Customer Application Bright Star Engineering FLEX 6000 Devices Connect Products Internet, continued from page reasons. "The EPF6016 device lowest cost flipflop industry, lends itself volume production, unlike expensive FPGAs from other companies," said Stuart Adams. "With freely available easy-touse BASELINE software sample code from BSE, developers started right away." EPF6016 device forms 88-pin "virtual interface" that configured according manufacturer's particular needs. used either communicate with existing product control monitor product's hardware. EPF6016 device emulate variety architectures well implement peripheral functions such universal asynchronous receiver/transmitters (UARTs), pulse width modulation (PWM) controls, memory emulation, data capture synthesis, interfaces variety devices. synchronous 128-Kbyte SRAM connected EPF6016 device. SRAM used high-speed shared buffer storage data coming from going virtual interface. ipEngine-1 Altera MAX+PLUS® BASELINE development software. downloading software free charge from Altera site, http://www.altera.com, developer configure EPF6016 device. Sample configuration files Altera Hardware Description Language (AHDL) VHDL found site http://www.brightstareng.com. "With freely available easy-to-use Altera BASELINE software sample code from BSE, developers started right away," said Stuart Adams. further simplify process configuring EPF6016 device defining virtual interface, developing library precompiled configurations ipEngine-1 that will available their site.
Conclusion
future, network-enabled products will change that interact with devices homes workplaces. integrating Altera FLEX 6000 device into ipEngine-1 using MAX+PLUS BASELINE software configuration, Bright Star Engineering able offer miniature, highly flexible, cost-effective network computer that connect third-party products Internet today.
Bright Star Engineering, Inc. Enfield Drive Andover 01810 sales@brightstareng.com http://www. brightstareng.com
MAX+PLUS BASELINE Software Makes Configuration Free Easy
their customers, added advantage using Altera device
Current Software Version
latest version Altera software MAX+PLUS® version 9.24. MAX+PLUS development system available Windows-based PCs, SPARCstation, 9000 Series 700/800, RISC System/6000 platforms.
$20K APEX
$20,000 charity Palm yourself. Altera celebrating release APEX device family giving away $20,000 charity. winner $20K APEX sweepstakes will able choose recipient from list approved organizations, will also receive Palm keep. your chance more information about speepstakes, visit Altera site
purchase necessary. Void where prohibited. Open only legal residents Continental U.S. years older 6/15/99, engineers engineering management currently employed company that uses programmable logic devices (semiconductors) manufactured Altera Corporation. Internet entries must received p.m. 7/15/99. Mail entries must postmarked 7/15/99 received 7/22/99. complete rules enter send self addressed stamped envelope P.O. 2032, Hollywood, 90078.
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Figure SDRAM Controller Extensions
Local
sd_ctrl ppc_ctrl ppc_addr Power SDRAM Controller Logic Core
Provides SDRAM Controller Integration with PCI/C
Northwest Logic Design (NWL), Altera Megafunction Partners Program (AMPPSM) partner, developed SDRAM controller with three important characteristics intellectual property (IP) solution: performance, extensibility, ease use. function also offers full integration with Altera® pci_c 64-bit, 66-MHz peripheral component interconnect (PCI) MegaCorefunction. This controller offers upwards 100-MHz performance when implemented Altera FLEX® 10KE devices while providing high degree flexibility through multiple interface modules user-defined parameters. SDRAM controller features include: Clock speeds FLEX 10KE devices 64-bit wide data support Full byte enable support Variable burst lengths Memory depths Mbytes 168-pin DIMM 144-pin SO-DIMM support Redundant large memory systems Parameterized timing specifications Pipelined access maximize throughput Efficient bank management Automatic SDRAM initialization Automatic refresh
sd_addr sd_ctrl
ALTERA MEGAFUNCTION PARTNERS PROGRAM
vb_ctrl vb_din vb_dout
Video Buffer
SDRAM Controller Logic Core
sd_addr sd_data sd_ctrl
pci_ctrl pci_a/d
Target
SDRAM Controller Logic Core
sd_addr sd_data
Motorola PowerPC 60x/750 interface, video frame buffer interface, target interface Altera pci_c MegaCore function. Table describes performance utilization these three extensions using SDRAM controller Altera FLEX 10KE devices.
Ease
SDRAM controller includes many features that make easy use. Currently, SDRAM controller available OpenCoremegafunction. design fully parameterized. Support available help customers integrate NWL's SDRAM controller quickly easily. future, MegaWizardPlug-In support will available this megafunction.
Table SDRAM Controller Performance FLEX 10KE Devices Interface Performance Device Speed (MHz)
PowerPC Video Buffer EPF10K200E-1 EPF10K50E-1 EPF10K50E-1
Performance
SDRAM controller achieves performance most FLEX 10KE devices. Utilizing latest timing models MAX+PLUS® software, provides solution systems requiring high-speed memory access.
Extensibility
natural addition design, SDRAM controller features interface modules- blocks that help integrate SDRAM controller into system. Figure illustrates extensions that currently available, including
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Utilization
2,041
EABs
Northwest Logic Design 1905 169th Place Suite Beaverton, 97006 (503) 533-5800 ip@nwlogic.com http://www.nwlogic.com
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Synplify/Quartus Integration Streamlines APEX Designs Design Flows
APEXdevices allow designers implement complex designs while achieving system performance requirements. Quartusdevelopment system addresses designers' needs supporting larger devices, enabling workgroup computing, incremental compilation. Synplify software builds these capabilities providing HDL-enhanced synthesis graphical debugging. This article describes this integration help APEX designers.
Figure APEX Logic Element Mapping
Under-the-Hood Integration
Quartus software provides under-the-hood integration NativeLinkfeature, improving synthesis power Synplify software. Enhancements Quartus development system allow Synplify software synthesized logic more efficiently into APEX architecture. understanding exact structures used with this enhanced mapping, Synplify software optimize design meet system requirements. Quartus software provides more powerful mapping element called ATOM primitive that controls mapping aspects APEX architecture, from logic elements (LEs) memory elements cells. Synplify software uses ATOM primitives netlist files, resulting improved performance logic utilization (see Figure ATOM primitive automated within Synplify software does require extra effort from designers. real impact quality results. addition general improvements quality results, precise control over logic implementation APEX devices gives Synplify software more accurate timing estimates. Synplify software uses these timing estimates timing constraints user make synthesis decisions affecting
utilization performance. Underconstraining overconstraining could cause inefficiencies that reduce overall system performance. interpreting timing delays, Synplify software accurately constrain optimize design.
Streamlined Design Flow Designers
addition improved optimization, there number integration features that enable Quartus Synplify software operate seamlessly together. Quartus software ability launch Synplify software automatically default synthesis tool; Synplify software launched batch mode perform synthesis. Synplify compile messages displayed Quartus Message Window. After successful synthesis Synplify software, Quartus software will place route design. Alternatively, Quartus development system allows Synplify application launch, compile, access Quartus databases. Additionally, Synplify software provides
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Altera News information that allows Quartus software cross-probe original Verilog HDL/VHDL code instead intermediate netlists. example, Synplify software both launch compile APEX designs Quartus software. After launching Quartus development system, user start Quartus project compile post-synthesis netlist file created Synplify. Productivity increased speeding enhancing communication between Synplify Quartus software. Additionally, "Quartus compile" step within Synplify software automatically goes through entire Altera place-and-route flow generates files static timing analysis information. Figure This process saves time combining multiple setup steps makes entire design flow more user friendly. After Quartus compile step done, Synplify software access post-placeand-route information evaluate results make further refinements, necessary. enhance designers debug improve designs using both tools, Synplify software links Quartus software back source code. Designers longer need worry about tracing signals through intermediate netlists such EDIF.
Summary
Through NativeLink integration, Quartus software provides powerful interface that allows Synplify software improve design flow well overall synthesis. combination Quartus Synplify software create smaller, faster designs with less work designer. Synplicity will release version Synplify software June 1999 that supports Quartus development system. This release will Quartus integration that provides streamlined design flows efficient mapping APEX devices. Synplicity committed providing APEX designers highest level integration with Quartus software.
Figure Using Quartus Compiler through Synplify Software
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SignalTap Embedded Logic Analyzer Provides Visibility Internal Signals
With introduction SignalTapembedded logic analyzer, Altera takes leadership role provider development tools multi-million gate designs. While these large devices enable they also create challenges. System devices containing several "virtual components" make difficult design engineers access signals from internal programmable logic device (PLD) nodes debugging verification. Traditional tools cannot used because they have access internal nodes. solution: place debugging tools inside device megafunction. Design engineers SignalTap logic analyzer access internal nodes signals pins. Integration with Quartussoftware- analyzer controls display integrated within Quartus development software.
Scalable Architecture
SignalTap parameterized megafunction lets choose many internal signals capture. Input channels selected power two, limited only number logic elements (LEs) embedded system blocks (ESBs) available. Table shows impact channel count usage.
Table Usage Analyzer Channels
EP20K400 Usage
0.82% 0.87% 0.96% 1.15% 1.54% 2.31% 3.85%
Bench-Top Logic Analyzer Inside APEX Devices
SignalTap embedded logic analyzer powerful debugging tool that provides nonintrusive visibility signals from internal nodes running speed. functions like bench-top logic analyzer inside APEXdevice, includes following features: Channel width acquisition depth-Users specify number input channels depth sample buffer. speed" acquisition-The embedded logic analyzer captures signals synchronous internal global clock. Powerful triggering-The SignalTap logic analyzer contains four-level trigger "sequencer" triggering complex sequence events. Selective data storage-Users specify which data save which ignore.
Acquisition data saved internal memory blocks, then transferred off-chip IEEE Std. 1149.1 Joint Test Action Group (JTAG) port. number ESBs used SignalTap logic analyzer depends number input channels used depth sample buffer. Table shows usage based channel width buffer depth. SignalTap logic analyzer synchronous (state) analyzer, capturing internal signals synchronous user-selected internal global clock. acquisition data represents "states" internal circuitry running speed.
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Table Embedded System Block Usage Channels
Multiple Analyzer Configurations
SignalTap logic analyzer been designed handle types problems. used several configurations match debugging task hand. entire analyzer contained within APEX device (see Figure Acquisition data saved internal RAM, then streamed off-chip after being triggered.
Figure Embedded Logic Analyzer
APEX Device
Unused Pins
Buffer Samples
1,024 2,048
Powerful Triggering
Internal Nodes Trigger Embedded Logic Analyzer Trigger JTAG
biggest challenges while debugging design isolating improper circuit operation. SignalTap logic analyzer provides powerful multi-level triggering with selective data storage locate problem capture information interest. SignalTap trigger resources include: Four pattern recognizers-Patterns define logic events based combination high, low, rising edge, falling edge, "don't care" conditions across input channels. Time count qualification-Each pattern further qualified duration (time) number occurrences (count). Delayed trigger-A trigger delay used postpone triggering specified period after pattern recognized. Four-level trigger sequence-Patterns linked together using IF/THEN/ ELSE/STORE structure create sequence events that must occur before analyzer triggers. Selective data storage-This feature, which each trigger level, lets save important data ignores meaningless information. Trigger I/O-External trigger input trigger output signals used synchronize logic analyzer with external test equipment vice versa).
Memory (ESB)
connect analyzer trigger input output signals unused pins synchronization external devices events. debugging port configuration routes internal signals unused pins acquisition external logic analyzer (see Figure
Figure Debug Port
Unused Pins
APEX Device
Acquisition Data Embedded Logic Analyzer Trigger Trigger JTAG
Internal Nodes
one-wire equivalent mode, trigger logic SignalTap function generates output based occurrence internal event (see Figure page 26). width trigger output pulse represent duration pattern trigger level. continued page
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Altera News SignalTap Embedded Logic Analyzer Provides Visibility Internal Signals, continued from page SignalTap logic analyzer integral part Quartus development software, providing single environment development, debugging, verification.
Figure One-Wire Equivalent
APEX Device
Unused Internal Nodes Embedded Logic Analyzer JTAG Trigger
MasterBlaster communications cable connects host standard serial universal serial (USB) port, target system using 10-pin female connector. provides multi-voltage interface target system, supporting levels between future lower-voltage standards.
Integrated with Quartus Software
SignalTap logic analyzer integral part Quartus development software, providing single environment development, debugging, verification. Internal nodes selected using Quartus Node Finder then dropped onto logic analyzer window, automatically assigning them capture. Analyzer setup-including triggering, sample buffer configuration control-is provided single, intuitive user interface Quartus software. Once analyzer created configured, compiled with rest design downloaded target device. Triggering changes made on-the-fly without recompiling design. Data acquired logic analyzer presented Quartus software waveform analysis.
trigger output, when captured external logic analyzer oscilloscope, used determine specific information about trigger event, such Whether event occurred many times occurred duration internal event duration variation (jitter)
MasterBlaster Communications Cable
MasterBlastercommunications cable shown Figure used downloading designs device. also provides control, data transfer information from SignalTap logic analyzer.
Figure MasterBlaser Communications Cable
SignalTap Plus System Analyzer
During system integration, designers face challenges-interfacing with rest system. Understanding elements board interact from system level becomes critical task. SignalTap Plus system analyzer from Boulder Creek Corporation addresses this need. more information SignalTap Plus system analyzer, Boulder Creek Corporation site http://www.bcreek.com.
Conclusion
SignalTap logic analyzer provided with Quartus development software lets view signals within device. This technology allows spend less time debugging, resulting increased productivity.
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Questions
Answers Setup/Hold option MAX+PLUS® QuartusSimulator. This guideline does apply circuits with different clock domains that interact with each other.
should port pulled instead high?
When device with both pulled high powered IEEE Std. 1149.1 Joint Test Action Group (JTAG) controller should stay within base, TEST_LOGIC/RESET state. However, during some power-up processes, transition from unpowered level powered high level occurs slightly different moments time between TCK. Figure Application Note (Using Language Embedded Processor). rise high level same time, rises before TCK, should have problem. However, rises before TMS, JTAG controller recognizes rising edge state machine clock, with signal equal shifts device into RUN_TEST/IDLE state. device stays this state until receives further control signals from JTAG port. Therefore, should pulled through resistor, both blank programmed devices. Figure Application Note (In-System Programmability Devices).
does MAX+PLUS software issue error "Device `device name' does have JTAG attribute information" nonAltera device after have entered JTAG attribute information? receive this error entered JTAG attribute information non-Altera device included space character Device Name field JTAG Device Attributes dialog box. avoid this error, remove space character from name.
Memory Initialization File (.mif) initialize memory created using lpm_ram_dq function implemented with logic elements (LEs) macrocells? MIFs only used initialize memory FLEX® embedded array blocks (EABs) APEXembedded system blocks (ESBs) during device configuration. cannot MIFs initialize blocks that have been implemented EABs because registers macrocells initialize zero after power-up configuration. want initialized block, initialize block that implemented EABs APEX ESBs.
doesn't multi-clock design function properly board even though simulation shows proper results? When using multiple clocks, should follow good asynchronous design practices, such registers synchronize data when transferring from clock domain another. first-in first-out (FIFO) buffer transfer data from clock domain another.
improve timing requirements FLEX device bidirectional pins?
Without following these techniques, registers device have setup hold time violations when driven data synchronized with different clocks. view this type error your simulation turn
possible improve FLEX bidirectional breaking into input output using element (IOE) registers both pins. Using global clock drive registers both input output pins gives best possible times signal. continued page
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Questions Answers Questions Answers, continued from page program MAX® devices configure FLEX devices same JTAG chain using JamPlayer?
can't pick-and-place machine distinguish solder balls ball-grid array (BGA) package from underside device when trying mount device? underside some packages shiny pick-and-place machines distinguish solder balls from bottom device. Many pick-and-place machines expect underside dark, dull color which balls easily distinguishable from background. help distinguish balls from shiny underside, recalibrate pickand-place machine. Contact machine's vendor help with recalibration.
Yes, program devices configure FLEX devices same JTAG chain using Byte-Code File (.jbc) File (.jam). should pass both DO_PROGRAM=1 DO_CONFIGURE=1 initialization variables Player version perform both functions. can't generate File from MAX+PLUS software program 7000AE devices test platform?
receive warning: "Current device family <device family> does support dual-port synchronous implementing synchronous dffe array instead. (dcfifo, FLEX 10K)?" dcfifo function most efficiently implemented EABs embedded system blocks (ESBs) that support dual-port (e.g., FLEX 10KE APEX devices). using FLEX 10KE APEX device, dcfifo function will implemented array dffe functions achieve dual-clocked behavior that integral part dcfifo function. require dual-clock FIFO buffer, scfifo function, which only requires single-clocked EABs. This megafunction implemented using EABs FLEX device.
program 7000AE devices with File, must devices that support "fixed" constant programming algorithm. Altera released fixed programming algorithm 7000AE devices. When devices released, MAX+PLUS software will updated support File generation. more information about planned release dates other availability details, contact your local Altera representative Altera Customer Marketing.
configure subset FLEX devices Multi-Device FLEX Chain?
must configure devices FLEX chain. cannot selectively configure device, like JTAG chain. error "I/O error: cannot open device \ALTLPT1. Check port number device driver installation." when running Player Windows workstation? most likely cause this error that ByteBlasterdownload cable driver been installed your Search "ByteBlaster" Atlas Solutions database Altera site (http://www.altera.com) details install driver.
Does EPC2 device have fixed programming pulse width?
Yes, EPC2 devices have fixed programming pulse width, which allows them programmed in-circuit testers using Serial Vector Format Files (.svf). need order special fixed-algorithm EPC2 devices.
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Every
Issue
Service (KCE-BBS) Microsystems' BBS. Programming support configuration, MAX® 9000, 7000 devices shown Table information subject change.
Table Third-Party Programming Hardware Support Device Data Microsystems
Altera Publications
publications available from Altera Literature Services. Individual documents available Altera site http://www.altera.com. Document part numbers shown parentheses. MasterBlaster Serial/USB Communications Cable Data Sheet (A-DS-MASTERBL-01) 3000A Programmable Logic Device Family Data Sheet (A-DS-M3000A-01) Quartus Programmable Logic Development System Software Data Sheet (A-DS-QUARTUS-01) SignalTap Embedded Logic Analyzer Megafunction Datasheet (A-DS-SIGNALTAP-01) 109: Using 3070 Tester InSystem Programming (A-AN-109-01) 110: Gate Counting Methodology APEX Devices (A-AN-110-01) 111: Embedded Programming Using 8051 Byte-Code (A-AN-111-01) 112: Integrating Product-Term Logic APEX Devices (A-AN-112-01) 115: Using ClockLock ClockBoost Features APEX Devices (A-AN-115-01) 116: Configuring APEX 20K, FLEX FLEX 6000 Devices (A-AN-116-01) Component Selector Guide (M-SG-COMP-06) Development Tools Selector Guide (M-SG-TOOLS-14)
EPC1064 EPC1213 EPC1 EPC1441 EPM7032 EPM7032AE EPM7032S EPM7064 EPM7064AE EPM7064S EPM7096 EPM7128A EPM7128S EPM7128AE EPM7128E EPM7160E EPM7192S EPM7192E EPM7256A EPM7256AE EPM7256S EPM7256E EPM7512AE
EPM9320 EPM9320A EPM9400 EPM9480
Altera Programming Support
Altera® third-party programming support available your Altera devices.
EPM9560 EPM9560A
Third-Party Programming Support
Data Microsystems provide programming hardware support selected Altera devices. Algorithms supplied Data I/O's Keep Current Express-Bulletin Board
1999 News Views
Notes: These devices supported Data 3900 version UniSite programmers version 6.0. These devices supported Microsystems programmers version 3.40. Please contact Data Microsystems about programming support these devices.
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Every Issue
Programming Hardware Support
following table contains latest programming hardware information Altera devices. correct programming,
Table Altera Programming Adapters (Part Note Device
EPC1064 EPC1064V EPC1441 EPC1 EPC1213 EPC2 J-lead TQFP EPM9320 J-lead (84-pin) RQFP (208-pin) (280-pin) EPM9320A J-lead (84-pin) RQFP (208-pin) EPM9400 J-lead (84-pin) RQFP (208-pin) RQFP (240-pin) EPM9480 RQFP (208-pin) RQFP (240-pin) EPM9560 RQFP (208-pin) RQFP (240-pin) (280-pin) RQFP (304-pin) EPM9560A RQFP (208-pin) RQFP (240-pin)
EPM7032 J-lead (44-pin) PQFP (44-pin) TQFP (44-pin) EPM7032S EPM7032AE EPM7032V EPM7064 J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin) EPM7064AE EPM7064S FBGA (100-pin) J-lead (44-pin) J-lead (84-pin) TQFP (44-pin) TQFP (100-pin) EPM7064AE J-lead (44-pin) TQFP (44-pin) TQFP (100-pin) EPM7096 J-lead (68-pin) J-lead (84-pin) PQFP (100-pin) PLMJ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMF7000-100 PLMJ7000-44 PLMJ7000-84 PLMT7000-44 PLMT7000-100NC PLMJ7000-44 PLMT7000-44 PLMT7000-100NC PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 J-lead (44-pin) TQFP (44-pin)
software version shown "Current Software Version" page Table lists Altera programming adapters 9000, 7000, configuration devices.
Table Altera Programming Adapters (Part Note Device
EPM7128E
Package
DIP, J-lead TQFP
Adapter
PLMJ1213 PLMT1064
Package
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
Adapter
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMT7000-100NC PLMT7000-144NC PLMF7000-100 PLMF7000-256 PLMJ7000-84 PLMQ7000-100NC PLMT7000-100NC PLMQ7128/7160160NC
DIP, J-lead
PLMJ1213
EPM7128A EPM7128AE
J-lead (84-pin) TQFP (100-pin) TQFP (144-pin) FBGA (100-pin) FBGA (256-pin)
PLMJ1213 PLMT1064 PLMJ9320-84 PLMR9000-208 PLMG9000-280 PLMJ9320-84 PLMR9000-208NC PLMJ9400-84 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMG9000-280 PLMR9000-304 PLMR9000-208NC PLMR9000-240NC
PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44 EPM7256A EPM7256E
EPM7128S
J-lead (84-pin) PQFP (100-pin) TQFP (100-pin) PQFP (160-pin)
EPM7160E
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMQ7128/7160160NC
EPM7160S
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7192E
(160-pin) PQFP (160-pin)
PLMG7192-160 PLMQ7192/7256-160 PLMQ7192/7256160NC
EPM7192S
PQFP (160-pin)
PQFP (160-pin) (192-pin) PQFP (208-pin) RQFP (208-pin) TQFP (100-pin) TQFP (144-pin) PQFP (208-pin) FBGA (256-pin)
PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMR7256-208 PLMT7000-100NC PLMT7000-144NC PLMR7256-208NC PLMF7000-256 PLMR7256-208NC PLMT7256-208NC
PLMT7000-100NC PLMF7000-100 PLMT7000-144NC PLMF7000-256 PLMT7000-144NC PLMR7256-208NC PLMB7000-256 PLMF7000-256
EPM7256A EPM7256S
EPM7256AE
PQFP (208-pin) RQFP (208-pin)
TQFP (100-pin) FBGA (100-pin) TQFP (144-pin) FBGA (256-pin)
EPM7512AE
TQFP (144-pin) PQFP (208-pin) (256-pin) FBGA (256-pin)
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Notes Table Refer Altera Programming Hardware Data Sheet device adapter information 5000 Classicdevices. Altera offers adapter exchange program 0.8-µm EPM5032, EPM5064, EPM5130 programming adapters. FBGA: FineLine BGApackages. FLEX® 8000 configuration device. FLEX 10K, FLEX 8000, FLEX 6000 configuration device. APEX 20K, FLEX 10K, FLEX 6000 configuration device. These devices shipped carriers.
Table Download Cable Compatibility Device
APEX APEX 20KE FLEX FLEX 10KA FLEX 10KE FLEX 8000 FLEX 6000 9000 9000A 7000S 7000A
BitBlaster
ByteBlasterMV
MasterBlaster
Download Cables
Table provides programming configuration compatibility information MasterBlasterserial universal serial (USB) communications cable, BitBlasterserial ByteBlasterMVparallel port download cables. (The ByteBlasterdownload cable been replaced with ByteBlasterMV cable.)
Notes: ByteBlasterMV download cable must operate these devices. Therefore, VCCIO pins FLEX 6000 family, this download cable only compatible with EPF6016 devices.
Altera Device Selection Guide
Current information Altera® APEX20K, FLEX® 10K, FLEX 8000, FLEX 6000, MAX® 9000, 7000, 3000A, configuration devices listed here. Information other Altera products located Altera Component Selector Guide.
APEX Devices
DEVICE
EP20K100
most up-to-date information, Altera site http://www.altera.com. Some devices listed available yet. Contact Altera your local sales office latest device availability.
GATES
100,000
PIN/PACKAGE OPTIONS
144-Pin TQFP, 196-Pin FBGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin FBGA2, 356-Pin
SUPPLY VOLTAGE
LOGIC ELEMENTS
4,160
BITS
53,248
MACROCELLS
EP20K100E
100,000
144-Pin TQFP, 196-Pin FBGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin FBGA2, 356-Pin
4,160
53,248
EP20K160E EP20K200 EP20K200E
160,000 200,000 200,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 400-Pin FBGA2 208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin FBGA2
6,400 8,320 8,320
81,920 106,496 106,496
208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin FBGA2, 652-Pin BGA, 672-Pin FBGA2
EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E
300,000 400,000 400,000 600,000 1,000,000
208-Pin RQFP, 240-Pin RQFP, 652-Pin BGA, 672-Pin FBGA2 652-Pin BGA, 655-Pin PGA, 672-Pin FBGA2 208-Pin RQFP, 240-Pin RQFP, 652-Pin BGA, 672-Pin 652-Pin BGA, 672-Pin FBGA2, 784-Pin FBGA2 784-Pin FBGA2, 984-Pin FBGA2
11,520 16,640 16,640 24,320 42,240
147,456 212,992 212,992 311,296 540,672
1,152 1,664 1,664 2,432 4,224
Notes: This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD. This package space-saving FineLine BGApackage.
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FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E EPF10K50S
GATES
10,000 10,000 20,000 30,000 30,000 30,000 40,000 50,000 50,000 50,000 50,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin FBGA1 144-Pin TQFP, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin FBGA1, 356-Pin BGA, 484-Pin FBGA1 144-Pin TQFP, 208-Pin PQFP, 256-Pin FBGA1, 484-Pin FBGA1 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin PQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin FBGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin FBGA1, 356-Pin BGA, 484-Pin FBGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin FBGA1, 356-Pin BGA, 484-Pin FBGA1
PINS
102, 102, 134, 102, 147, 147, 189, 102, 147, 189, 191, 246, 102, 147, 176, 147, 189, 274, 189, 189, 274, 102, 147, 189, 191, 220, 102, 147, 189, 191, 220, 189, 189, 274, 369, 147, 189, 147, 189, 191, 274, 470, 186, 274, 369, 424, 470, 470, 182, 274, 369, 470, 470,
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728 1,728 2,304 2,880 2,880 2,880 2,880
BITS
6,144 6,144 12,288 12,288 12,288 24,576 16,384 20,480 20,480 40,960 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E
70,000 100,000 100,000 100,000 100,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin FBGA1, 600-Pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin FBGA1 208-Pin PQFP, 240-Pin PQFP, 256-Pin FBGA1, 356-Pin BGA, 484-Pin FBGA1
3,744 4,992 4,992 4,992 4,992
18,432 24,576 24,576 24,576 49,152
EPF10K130V EPF10K130E
130,000 130,000
599-Pin PGA, 600-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin FBGA1, 600-Pin 672-Pin FBGA1 599-Pin PGA, 600-Pin BGA, 672-Pin FBGA1 240-Pin RQFP, 356-Pin BGA, 484-Pin FBGA1, 600-Pin BGA, 672-Pin FBGA1
6,656 6,656
32,768 65,536
EPF10K200E EPF10K200S
200,000 200,000
9,984 9,984
98,304 98,304
EPF10K250A
250,000
599-Pin PGA, 600-Pin
12,160
40,960
Notes:
EThis8packageD eavspace-saving FineLine package. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
DEVICE
GATES
2,500 2,500 4,000 6,000 8,000
PIN/PACKAGE OPTIONS
PINS
118, 136, 112, 120, 152, 152, 148, 184, 181, 208,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
LOGIC ELEMENTS
EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A
84-Pin PLCC, 100-Pin TQFP 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin
EPF81188A EPF81500A
12,000 16,000
208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
1,188 1,500
1,008 1,296
FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A
GATES
10,000 16,000 16,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 100-Pin FBGA1, 256-Pin FBGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 100-Pin FBGA1, 144-Pin TQFP, 208-Pin PQFP, 256-Pin FBGA1
PINS
117, 812, 1392 117, 171, 199, 1172, 171, 2182 117, 171, 199, 218, 2182
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320
LOGIC ELEMENTS
1,320 1,320
EPF6024A
24,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin FBGA1
1,960
1,960
Notes tables: This package space-saving FineLine package. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
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Configuration Devices APEX FLEX Devices
DEVICE
EPC1064 EPC1064V EPC1213 EPC14411 EPC11 EPC21
PIN/PACKAGE OPTIONS
8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 20-Pin PLCC, 32-Pin TQFP
SUPPLY VOLTAGE
3.3/5.0 3.3/5.0 3.3/5.0
DESCRIPTION
64-Kbit serial configuration device designed configure FLEX 8000 devices 64-Kbit serial configuration device designed configure FLEX 8000 devices 213-Kbit serial configuration device designed configure FLEX 8000 devices 441-Kbit serial configuration device designed configure FLEX devices 1-Mbit serial configuration device designed configure APEX FLEX devices 2-Mbit serial configuration device designed configure APEX, FLEX 10K, FLEX 10KE, FLEX 6000 devices
Note: This device programmed user operate either
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-15, -15, -15, -15,
7000 Devices
DEVICE
EPM7032AE EPM7032S EPM7032 EPM7064AE EPM7064S EPM7064 EPM7096 EPM7128A EPM7128AE EPM7128S EPM7128E EPM7160S EPM7160E EPM7192S EPM7192E EPM7256A EPM7256AE
MACROCELLS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP
PIN/PACKAGE OPTIONS
PINS
SUPPLY VOLTAGE
SPEED GRADE
-10, -12, -10, -12, -10, -12, -10, -5,-7,-10 -10, -10, -12, -15, -10, -10, -12, -15, -10, -12, -15, -10,
44-Pin PLCC/TQFP/PQFP 44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin FBGA1 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin FBGA1, 144-Pin TQFP, 256-Pin FBGA1
100, 100, FBGA1 120, 164, 120, 164, 132, 164,
84-Pin PLCC, 100-Pin TQFP, 100-Pin FBGA1, 144-Pin TQFP, 256-Pin FBGA1 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP/PGA 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin
100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 100-Pin FBGA1, 256-Pin FBGA1
EPM7256S EPM7256E EPM7512AE
208-Pin RQFP/PQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 144-Pin TQFP, 208-Pin PQFP, 256-Pin FBGA1, 256-Pin
-10, -12, -15, -10,
120, 176, 212,
Note: This package space-saving FineLine package.
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3000A Devices
DEVICE
EPM3032A EPM3064A EPM3128A EPM3256A
MACROCELLS
PIN/PACKAGE OPTIONS
44-pin PLCC, 44-pin TQFP 44-pin PLCC, 44-pin TQFP, 100-pin PQFP 100-pin TQFP, 144-pin PQFP 144-pin TQFP, 208-pin PQFP
PINS
116,
SUPPLY VOLTAGE
SPEED GRADE
Contact Altera
Getting information services from Altera easier than ever. table below lists some ways reach Altera:
Information Type
Literature
Access
Altera Literature Services
U.S. Canada
(888) 3-ALTERA lit_req@altera.com
Other Locations
(408) 544-7144 lit_req@altera.com http://www.altera.com (408) 544-7000 (408) 544-6403 (408) 544-7000
World-Wide Non-Technical Customer Service Technical Support Telephone Hotline Telephone Hotline a.m. p.m. Pacific Time) Electronic Mail Site General Product Information Telephone World-Wide
http://www.altera.com (800) SOS-EPLD (408) 544-6403 (800) 800-EPLD (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
(408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Notes: MAX+PLUS Getting Started manual available from Altera site. obtain other MAX+PLUS software manuals, contact your local distributor. also contact your local Altera sales office sales representative. Altera site listing.
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Altera launching Tools Training Program Altera Technical Training classes offered North America. This program provides with free evaluation copy Altera development tools, including MAX+PLUS Quartus software when attend Altera training class.
-bit
Other Interface Megafunctions
interface solution includes functions such peripheral component interconnect (PCI), universal serial (USB), SDRAM controller functions. This solution enables designers focus differentiating design elements, typically local interface custom configurable logic. Altera® solution provides critical advantages system designer. Altera's high-density APEXand FLEX® devices enable designers create single-device solution that includes both interface application-specific logic custom solution. Altera megafunctions deliver compliance optimization, significantly reduce design efforts. Megafunctions ready-made, pre-tested blocks intellectual property (IP) that optimized make efficient target architecture. using megafunctions, designers focus more time energy improving differentiating their system-level product, rather than redesigning common functions. download Altera MegaCorefunctions from Altera site evaluate them free before licensing using OpenCorefeature found MAX+PLUS® software. also e-mail request OpenCore version almost every Altera Megafunction Partners Program (AMPPSM) megafunction Altera site. most up-to-date information about Altera megafunctions, Altera site. Contact Altera your local sales office questions related megafunctions.
Megafunctions
Megafunction 64-Bit Master/Target Function 64-Bit Master/Target (EC240) 64-Bit Master/Target Interface 64-Bit Target 64-Bit Target Interface Parameterized 32-Bit Master/Target 32-Bit Target Interface 32-Bit Master/Target with Burst 32-Bit Master/Target with Burst 32-Bit Master/Target with Controller 32-Bit Target with Burst 32-Bit Target with Burst Hostbridge Source Altera MegaCore Function Eureka Technology Applications Eureka Technology Applications Altera MegaCore Function Applications Eureka Technology Applications Altera MegaCore Function Altera MegaCore Function Eureka Technology Eureka Technology
MegaCore
Other Interface Megafunctions
Megafunction IEEE 1284 Parallel Slave Interface IEEE 1394-Compatible Link Layer Controller (LLC-1) IEEE 1394A Function Master Slave PowerPC Arbiter (EP300) PowerPC Master (EP200) PowerPC Slave (EP100) SDRAM Controller SDRAM Controller Si-Enable USP-86: Host Controller Si-Function: Function Controller Si-Function: Controller Si-Link: IEEE 1394 Link Layer Controller Function Controller Host Controller VUSB Embedded Host Controller Source Sican Microelectronics
ALTERA MEGAFUNCTION PARTNERS PROGRAM
Phoenix Technologies Sican Microelectronics Sican Microelectronics Eureka Technology Eureka Technology Eureka Technology Northwest Logic Design Stargate Solutions Simple Silicon Simple Silicon Simple Silicon Simple Silicon Sapien Design Sapien Design VAutomation
OpenCore
Discontinued Devices Update
Altera announcements regarding discontinued devices. Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera® sales representative. Selected ADVs, PDNs, complete listing discontinued devices also available Altera's site http://www.altera.com. Rochester Electronics, after-market supplier, offers many discontinued Altera products. Contact Rochester Electronics (978) 462-9332 their site http://www.rocelec.com.
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