Altera® FLEX® 10KE family meets 66-MHz/64-bit peripheral component int
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FLEX 10KE Devices Meet 66-MHz/64-Bit Compliance Challenge
Altera® FLEX® 10KE family meets 66-MHz/64-bit peripheral component interconnect (PCI) compliance challenge. Flexibility density make programmable logic devices (PLDs) ideal choice implementing designs. FLEX 10KE devices meet timing specification 3-ns setup time (tSU) 6-ns clock-to-output time (tCO), 66-MHz, 64-bit PCI-compliant. Innovative Programmable Delay Feature FLEX 10KE devices have innovative programmable delay feature that allows them meet most stringent timing specifications. Designers programmable multiplexer bypass delay buffer element (IOE), improving timing requirements. Figure FLEX 10KE devices will include programmable delay feature with delay buffer that used bypassed unnecessary. non-PCI designs, delay buffer implemented introduce required delay guarantee zero hold time pin. designs have sufficient amount combinatorial
Figure Programmable Delay Feature
Programmable Multiplexer
Interconnect
logic between register pin; therefore, extra delay needed register guarantee zero hold time. Bypassing delay buffer gives better setup times enabling signal reach input register faster, allowing FLEX 10KE devices meet setup times required 66-MHz, 64-bit compliance. existing EPF10K50E EPF10K200E devices, element introduces delay from input input register ensure zero hold time designs. These devices will enhanced include programmable delay feature. Although existing EPF10K50E devices already compliant without this feature, adding programmable delay increases flexibility designs. Support Programmable Delay with MAX+PLUS Version Support programmable delay available with version 9.11 higher MAX+PLUS® development software. MAX+PLUS version software supports 66-MHz/64-bit PCI-compliant timing Altera MegaCorefunctions Altera Megafunction Partners Program (AMPPSM) megafunctions. continued page
Delay Buffer
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A-NV-Q199-01
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Contents
Features FLEX 10KE Devices Meet 66-MHz/64-Bit Compliance Challenge Customer Application: FLEX Device Creating Fully Featured, Compact Motion Controller Altera News Coming Soon: Altera 1999 Data Book Revolutionary Quartus Software Enhances Design Process Altera Technical Seminars Provide System-on-aProgrammable-Chip Solution Newest AMPP Partner Offers SONET, Test Boards Altera Technical Training Program ASSET Provides First Tools Suite Supporting Both Programming Devices Tools APEX Family MegaLAB Structures APEX Devices APEX High-Performance Support ESBs Offer Memory Advantages SignalTap Logic Analysis Speeds Verification High-Density EPF10K200E Devices Available Available FLEX 10KE Devices Programmable Delay FLEX 10KE Devices More FLEX Devices Packages FLEX Product Transitions FLEX Device Availability FineLine Packages Coming Soon FLEX 6000 Devices Industrial-Temperature FLEX 6000 Devices Available EPC2 Reprogrammable Configuration Device Available 9000A Device Availability
7000A Availability 7000S Family 7000 9000 Device Transitions NativeLink Integration Offers Seamless Interface with Tools Discontinued Devices Update CoreSyn Synthesis Altera Subscription Program Available Place Subscription Renewal Orders with Altera Tools Services Adapters Programming 7000A 7000AE Devices Altera Ships MAX+PLUS Version 9.21 Software Obtain MAX+PLUS License Files MAX+PLUS BASELINE Software
Technical Articles Using Altera Devices Multiple Voltage Systems Hot-Socketing Embedded Programming Using 8051 Microprocessor Byte-Code Questions Answers APEX Devices Feature Product-Term Mode Every Issue Third-Party Programming Support Altera Publications Programming Hardware Support Altera Programming Adapters Altera Offers over Megafunctions Altera Device Selection Guide Current Software Version Contact Altera Response Form
information about this newsletter, submit questions, contact: Erica Heidinger, Publisher Greg Steinke, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 E-mail: n_v@altera.com
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Altera, APEX, APEX 20K, ASCEND, ACCESS, AMPP, BitBlaster, ByteBlaster, ByteBlasterMV, Classic, ClockBoost, ClockLock, CoreSyn, EPC2, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Jam, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 7000AE, 5000, MAX, MAX+PLUS, MAX+PLUS MegaCore, MegaLAB, MegaWizard, MultiCore, MultiVolt, NativeLink, nSTEP, OpenCore, Quartus, SignalTap, System-on-a-Programmable-Chip, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: ASSET registered trademark ASSET InterTech, Inc. HammerCores registered trademark HammerCores, Inc. Integrated Silicon Systems registered trademark Integrated Silicon Systems, Inc. KTech Telecommunications registered trademark KTech Telecommunications, Inc. Nova Engineering registered trademark Nova Engineering, Inc. Rochester Electronics registered trademark Rochester Electronics, Inc. Tech registered trademark Technology Inc. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. actual availability Altera's products features could differ from those projected this publication provided solely estimate reader. Copyright 1999 Altera Corporation. rights reserved.
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Features FLEX 10KE Devices Meet 66-MHz/64-Bit Compliance Challenge, continued from page MegaCore Functions AMPP Megafunctions Maximize Performance addition increased power flexibility solution with FLEX 10KE devices, Altera also introducing MegaCore function. This function will help maximize performance designs. Altera plans release pci_c MegaCore function March 1999. This highperformance master/target MegaCore function fully hardware-tested flexibly implemented 66-MHz/64-bit master/target interface. Through this megafunction, designers parameterize their function meet exact design requirements optimal PLD. Implemented FLEX 10KE devices, pci_c function 66-MHz PCI-compliant. Table lists Altera MegaCore functions.
Table MegaCore Megafunctions
Megafunction
pci_c pci_a pci_b pcit1
Table AMPP Megafunctions
AMPP Partner
Eureka Technology Eureka Technology Eureka Technology Applications Applications Applications Applications
Description
32-bit target with burst 64-bit target only 32-bit master/target with burst 32-bit target only 32-bit master/target 64-bit target only 64-bit master/target
Availability
Description
MHz, 64-bit; master/target MHz, 64-bit; master/target MHz, 32-bit; master/target MHz, 32-bit; master/target MHz, 32-bit; target only
Availability
March 1999
board. After implementing design downloading FLEX 10KE device universal board, designer exercise design verify functionality. board reduces time required implement test design. universal board supports Altera MegaCore functions scheduled ship second quarter 1999. Conclusion With introduction FLEX 10KE devices including innovative programmable delay feature, Altera offers solution challenge. 66-MHz, 64-bit master/target MegaCore function universal board maximize performance these devices. combination device, function, board simplifies implementation testing designs. Altera developed winning solution meet your design challenges.
AMPP program also offers number 64-bit, 33-MHz megafunctions that optimized Altera devices. Table lists AMPP megafunctions currently available. Universal Board Tests Functionality expedite process testing designs boost productivity, Altera offering universal
Coming Soon: Altera 1999 Data Book
Altera® 1999 Data Book will available March 1999 from Altera Literature Services. This book contains comprehensive literature Altera devices, including: Current information APEXarchitecture, including APEX Programmable Logic Device Family Data Sheet current Altera device family data sheets Application notes device timing Ordering information Altera devices software Altera will release data book device packaging second quarter 1999, another data book Altera tools second half 1999.
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Devices
APEX Family
&TOOLS
APEX Update
component interconnect- (PCI-) compliant pins. MultiVoltI/O interface, which ideal mixed-voltage systems, also standard feature. APEX 20KE devices extend highest integration density support advanced standards, including LVTTL, LVCMOS, Gunning transceiver logic (GTL+), stub-series terminated logic (SSTL-2 SSTL-3), low-voltage differential signaling (LVDS), advanced graphics port (AGP), center terminated (CTT), high speed transceiver logic (HSTL). These devices also offer further enhancements ClockLock ClockBoost features. APEX devices will offered variety packages, including space-saving FineLine BGApackages. Table shows device features APEX family.
APEX20K family, with system performance over MHz, will have densities ranging from 100,000 million gates. This family uses revolutionary MultiCorearchitecture, which combines look-up table (LUT) logic, product-term logic, embedded memory into single device, provide first APEX device, 2.5-V EP20K400, will available March 1999. 1.8-V APEX 20KE devices will available 1999 offer enhanced superset features. MegaLAB Structures APEX Devices APEX devices combine logic elements (LEs) memory into MegaLABstructures (see Figure MegaLAB structures contain logic array blocks (LABs) composed each, advanced embedded structure called embedded system block (ESB), local interconnect that connects LABs ESB. APEX High-Performance Support APEX devices offer enhanced ClockLockand ClockBoostfeatures support peripheral
Table APEX Devices
Feature
Maximum Gates Typical Gates Logic Elements Maximum Macrocells Maximum Bits
Figure APEX MegaLAB Structure
Logic Element (LE) 4-Input Flipflop Carry Cascade Chains
Embedded System Block (ESB)
MegaLAB Interconnect
LAB1 LAB2 LAB16
Logic Array Block (LAB) MegaLAB LABs
Local Interconnect
MegaLAB
EP20K100E EP20K100
263,000 53,000 106,000 4,160 53,248
EP20K160E
404,000 82,000 163,000 6,400 81,920
EP20K200E EP20K200
526,000 106,000 211,000 8,320 106,496
EP20K300E
728,000 147,000 293,000 11,520 1,152 147,456
EP20K400E EP20K400
1,052,000 213,000 423,000 16,640 1,664 212,992
EP20K600E
1,537,000 311,000 618,000 24,320 2,432 311,296
EP20K1000E
2,670,000 541,000 1,073,000 42,240 4,224 540,672
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Devices Tools ESBs Offer Memory Advantages APEX ESBs, which contain 2,048 programmable bits, configured product-term logic, LUT-based logic, three different types memory: dual-port RAM, ROM, content addressable memory (CAM). Configuring product-term logic enables APEX device achieve unmatched integration efficiencies. more information product-term mode functionality, "APEX Devices Feature Product-Term Mode" page also supports dual-port wide range widths depths required systemlevel design. APEX 20KE supports CAM, parallel processing memory that accelerates applications requiring fast searches. takes data input then supplies address that contains data input. APEX ESBs cascaded together implement larger functions. SignalTap Logic Analysis Speeds Verification APEX devices used with Quartusdevelopment software implement SignalTaplogic analysis, which allows users capture analyze internal APEX device signal. SignalTap logic analysis allows reduced verification times enabling engineers conduct at-speed, on-the-fly functional verification. Software support FLEX 10KE PLLs available MAX+PLUS® version 9.21 higher software. Programmable Delay FLEX 10KE Devices FLEX 10KE devices provide programmable delay feature that aids FLEX 10KE-1 device's compliance 66-MHz/64-bit peripheral component interconnect (PCI) specification; speed grade devices, programmable delay feature provides timing enhancements performance-critical designs. EPF10K100E device first with this feature; EPF10K130E EPF10K30E devices will next devices released with this feature. EPF10K50E EPF10K200E devices, which have already been released, will enhanced include programmable delay feature. performance characteristics, existing EPF10K50E-1 device already compliant 66-MHz/64-bit specifications. Software support programmable delay feature available MAX+PLUS version higher software. More FLEX Devices Packages Altera plans offer more FLEX 10KE devices 1.27-mm pitch packages. addition EPF10K100E device 356-pin packages EPF10K200E device 600-pin packages, Altera planning offer EPF10K50E, EPF10K130E, EPF10K200E devices 356-pin packages, EPF10K130E devices 600-pin packages. Table page device package availability. FLEX Product Transitions Altera migrating EPF10K100A, EPF10K30A, EPF10K10A devices from 0.35-µm process 0.30-µm process. Additionally, EPF10K50 devices migrating from 0.50-µm process 0.42-µm process. Table outlines process migration schedule lists reference documentation associated with this migration. download these documents from Customer Notification page Altera site http://www.altera.com.
Table FLEX Migration Schedule
Device
EPF10K100A EPF10K30A EPF10K10A EPF10K50
FLEX Update
High-Density EPF10K200E Devices Available high-density EPF10K200E devices-featuring dualport with independent read/write ports, 9,984 logic elements (LEs), 98,304 bits on-chip RAM-are available. EPF10K200E devices offer most on-chip device FLEX® family; they available today 600-pin ball-grid array (BGA), 672-pin FineLine BGA, 599-pin pingrid array (PGA) packages. Available FLEX 10KE Devices phase-locked loop (PLL) available EPF10K200E devices designated with "-X" suffix ordering code (i.e., EPF10K200EBC600-1X). feature will offered FLEX 10KE device densities both speed grades. PLLs provide ClockLock ClockBoost options, which reduce clock delay skew, perform internal clock multiplication simpler board designs.
Transition Date
February 1999 April 1999 July 1999 June 1999
Reference
9810 9810 9810 9901
Process (µm)
0.30 0.30 0.30 0.42
Devices Tools, continued page
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Devices Tools Devices Tools, continued from page FLEX Device Availability Table shows expected availability 2.5-V FLEX 10KE devices. only FLEX 10KA device released EPF10K50V 484-pin FineLine package (shown Table other 3.3-V FLEX 10KA devices available today. MAX+PLUS design support currently available most device package options.
Table FLEX 10KE Device Availability
Device
EPF10K30E
FineLine Packages Coming Soon FLEX 6000 Devices FLEX 6000 devices FineLine packages planned available second quarter 1999. These area-efficient packages require less than half board space traditional packages. Table shows expected availability FLEX 6000 devices.
Table FLEX 6000 Device Availability
Package Device EPF6010A EPF6016 EPF6016A EPF6024A
Package
144-pin TQFP 208-pin PQFP
Speed Grade
Availability
June 1999 June 1999 August 1999 August 1999 March 1999 July 1999 March 1999 March 1999 April 1999 April 1999 April 1999 April 1999 June 1999 1999 June 1999 1999 June 1999 June 1999 July 1999 March 1999
100-Pin TQFP 100-Pin FineLine 144-Pin TQFP 208-Pin PQFP 240-Pin PQFP 256-Pin 256-Pin FineLine
1999 1999
1999 1999 1999
256-pin FineLine 484-pin FineLine EPF10K50V EPF10K50E 484-pin FineLine 144-pin TQFP 208-pin PQFP 240-pin PQFP 356-pin EPF10K100B 208-pin PQFP 240-pin PQFP EPF10K100E 208-pin PQFP 240-pin PQFP 356-pin EPF10K130E 240-pin PQFP 356-pin 600-pin EPF10K200E 240-pin RQFP 356-pin 599-pin 600-pin
256-pin FineLine 484-pin FineLine
Industrial-Temperature FLEX 6000 Devices Available FLEX 6000 devices available industrialtemperature grades. There five devices currently shipping either 144-pin thin quad flat pack (TQFP) 208-pin plastic quad flat pack (PQFP) packages. sixth device 100-pin TQFP package planned release March 1999. Table lists availability industrial-temperature grade FLEX 6000 devices.
Table Industrial-Temperature FLEX 6000 Device Availability
Device
EPF6016TI144-3 EPF6016QI208-3 EPF6016ATI100-3 EPF6016ATI144-3 EPF6016AQI208-3 EPF6024AQI208-3
256-pin FineLine
256-pin FineLine 484-pin FineLine
Package
144-pin TQFP 208-pin PQFP 100-pin TQFP 144-pin TQFP 208-pin PQFP 208-pin PQFP
Availability
March 1999
484-pin FineLine 672-pin FineLine
484-pin FineLine
672-pin FineLine
Configuration Device Update
EPC2 Reprogrammable Configuration Device Available EPC2, Altera's first reprogrammable configuration device, available. This device offered 20-pin plastic J-lead chip carrier (PLCC) 32-pin TQFP packages compatible with existing
Note: RQFP: power quad flat pack.
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Devices Tools Altera configuration devices same packages. single EPC2, which configure FLEX device with 130,000 gates, programmed in-system using IEEE Std. 1149.1 Joint Test Action Group (JTAG) test ports. EPC2 supports Serial Vector Format (SVF) test programming language. EPC2 operates supported MAX+PLUS version software.
Table 7000A Device Availability
Device
EPM7032AE EPM7064AE
Package
44-pin PLCC 44-pin TQFP 44-pin PLCC 44-pin TQFP 100-pin TQFP
Speed Grade Availability
-10, -10, -10, -10, -10, -10,
-10, -10, -10,
100-pin FineLine
Update
9000A Device Availability With propagation delays fast MAX® 9000A devices offer significant performance enhancements cost reduction over existing 9000 devices. packages EPM9320A EPM9560A devices available production quantities. Table summarizes commercial- industrial-temperature 9000A device availability.
Table 9000A Device Availability
Device 84-Pin PLCC
EPM7128A
84-pin PLCC 100-pin TQFP 160-pin PQFP
100-pin FineLine -10, 256-pin FineLine -10, EPM7128AE 84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP EPM7256A 100-pin TQFP 144-pin TQFP 208-pin PQFP 1999
256-pin FineLine
Note
240-Pin RQFP
256-pin FineLine -10,
208-Pin RQFP
356-Pin
EPM7256AE
100-pin TQFP 144-pin TQFP 208-pin PQFP
1999
100-pin FineLine
EPM9320A EPM9560A
Note: designates commercial designates industrial temperature.
256-pin FineLine
EPM7512AE 144-pin TQFP 208-pin PQFP 256-pin
7000A Availability Altera improved performance 7000A devices, which include devices with 4.5-ns propagation delays. 7000A devices support in-system programmability (ISP) MultiVolt pins, provide compatibility with industry-standard 7000 devices. EPM7032AE, EPM7064AE, EPM7128A, EPM7256A, EPM7512AE devices shipping. Table shows 7000A device availability. 7000S Family 7000S devices available. These devices offer features such speed grades in-system programming, open-drain output, IEEE Std. 1149.1 (JTAG) boundary-scan testing (BST) circuitry devices with more macrocells. 7000S devices available industrial temperature grades. Table shows packages
256-pin FineLine -10,
Table 7000S Device Packages
Device
EPM7032S EPM7064S
Package
44-pin PLCC 44-pin TQFP 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10,
EPM7128S
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP
EPM7160S
84-pin PLCC 100-pin TQFP 160-pin PQFP
EPM7192S EPM7256S
160-pin PQFP 208-pin PQFP
continued page
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Devices Tools Devices Tools, continued from page speed grades available commercial temperature grade devices. 7000 9000 Device Transitions Altera completed migration 7000 9000 devices from 0.65-µm process 0.5-µm process. Table outlines devices that were migrated lists reference documentation associated with this migration. download these documents from Customer Notifications page Altera site http://www.altera.com.
Table 7000 9000 Process Migrations
Device
EPM7032 EPM7064 EPM7064S EPM7128E EPM7128S EPM7160E EPM7192E EPM7192S EPM7256S EPM7256E EPM9320 EPM9560
Tools Update
NativeLink Integration Offers Seamless Interface with Tools Designers developing 400,000-gate designs APEX devices likely follow flow involving third-party synthesis, simulation, verification tools together with Altera's Quartus software. problems with such flow pass design information between different tools. NativeLinkfeature found Altera's Quartus software provides unmatched level integration with third-party tools, allowing designs compiled much faster more efficiently. Third-party applications launched from within Quartus software background during compilation. Quartus NativeLink feature developed ensure seamless interface with Altera's partners. Altera provided third-party partners with application programming interface (API) specifications Quartus software allow feature database access third-party tools using C++, TCL, Visual Basic. Through this process integrated development, NativeLink feature allows Quartus easily interface with other tools. using NativeLink feature integrate thirdparty tools with Quartus software, design process simplified. Designers required learn software package; Quartus software will interface tool with which designer already familiar. This close integration allows error warning messages traced directly back source file. Through Quartus software with NativeLink feature, information passed more efficiently between tools, accelerating compilation providing better timing estimates optimal synthesis. This tightly integrated system will allow engineers achieve high quality results when implementing designs Altera APEX devices.
Note
Reference
9703 9803 9703 9708 9703 9708 9703 9803 9703 9708 9703 9708 9703 9803 9703 9803
Date
Complete Complete Complete Complete Complete Complete Complete Complete
Process (µm)
Notes: process transition will result changes data sheet parameters ordering codes. Altera provides advisories process change notices. Altera site these reference documents.
Discontinued Devices Update
Altera announcements regarding discontinued devices. Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera® sales representative. Selected ADVs, PDNs, complete listing discontinued devices also available Altera's site http://www.altera.com. Rochester Electronics, after-market supplier, offers many discontinued Altera products. Contact Rochester Electronics (978) 462-9332 their site http://www.rocelec.com.
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Devices Tools CoreSyn Synthesis Quartus nSTEPCompiler includes incremental compilation CoreSynsynthesis capability. CoreSyn synthesis feature invokes appropriate synthesis technology determine optimal mapping design Altera device's architecture. When design compiled, CoreSyn feature partitions functions into appropriate architectural element within APEX device. example, state machines implemented into product-termbased macrocell, first-in first-out (FIFO) functions placed ESBs, data-paths utilize LUT-based LEs. engineer also direct where particular portion design mapped within APEX device. Figure illustrates CoreSyn synthesis feature. CoreSyn feature, along with incremental compilation, allows designers nSTEP Compiler compile, change, recompile design fraction time once needed same process. Each piece design placed appropriate type APEX architecture, ensure optimal implementation. Altera Subscription Program Available Altera Subscription Program offers customers simple obtain Altera development software support. With subscription, customers receive updates Altera software (including both MAX+PLUS Quartus software) months. Customers have purchased subscription products will receive Quartus software when released. duration their 12-month subscription, they will continue receive full-featured versions MAX+PLUS Quartus development software. your current 12-month subscription, must purchase renewal subsequent releases. subscription program provides significant reduction cost, priced only $2,000 (fixednode product) months. Under Altera maintenance program, same support would cost over $6,000 ($4,995 PLS-MAGNUM, year software maintenance). Table provides description Altera Subscription Program options.
Table Altera Subscription Program Product Line
Product
FIXEDPC FLOATPC FLOATNET
Description Coverage
using software guards Networked environment consisting clients only Networked environment consisting UNIX, combination clients Renew existing subscription program additional month period Additional seats FLOATPC product Additional seats FLOATNET product
List Price
$2,000 $2,200 $2,400
RENEWAL
$2,000
ADD-FLOATPC ADD-FLOATNET
$2,200 $2,400
continued page
Figure Quartus CoreSyn Feature
Write Memory Control Read Memory Control CoreSyn Algorithm Memory Controller FIFO
Product Term
Memory
FIFO Usage Parameter Control State Machine
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Devices Tools Devices Tools, continued from page more information Altera Subscription Program, contact your local Altera sales office. Place Subscription Renewal Orders with Altera Tools Services Altera Tools Services dedicated supporting subscription renewals, offers following services customers North America: Provides subscription renewal quotes Accepts subscription renewal orders Answers your questions subscription coverage renewal Altera Tools Services simplifies subscription renewal process lets purchase subscription renewal agreements with single phone call. North American customers purchase their subscription renewal contacting Altera Tools Services Altera Tools Services Innovation Drive 4207 Jose, 95134 Tel: (888) 800-0631 Fax: (408) 544-7606 International customers should contact their local Altera sales representative their subscription renewal. Adapters Programming 7000A 7000AE Devices MAX+PLUS version software offers support 7000A 7000AE devices FineLine packages. While most designers will program these devices in-system, three programming adapters speed grades available program these devices using Master Programming Unit (MPU). Table lists adapters. "Altera Programming Adapters" page list programming adapters 9000, 7000, configuration devices.
PLMF7000-256
Table 7000 Adapters
Altera Part Number
PLMF7000-100
Device Package
Devices Supported
EPM7128AFC100 EPM7128AEFC100 EPM7256AEFC100
100-pin FineLine EPM7064AEFC100
256-pin FineLine EPM7128AFC256 EPM7128AEFC256 EPM7256AFC256 EPM7256AEFC256 EPM7512AEFC256
PLMB7000-256
256-pin
EPM7512AEBC256
Altera Ships MAX+PLUS Version 9.21 Software MAX+PLUS version 9.21 software shipping customers have active subscription software maintenance agreement. MAX+PLUS version 9.21 software will provide support FLEX 10KE devices with ClockLock ClockBoost features. support highspeed designs, FLEX 10KE devices offer ClockLock ClockBoost circuitry containing phase-locked loop (PLL). MAX+PLUS version 9.21 software update provides support these features EPF10K200EB600 EPF10K200EF672 devices. This latest version MAX+PLUS software adds many useful features full line Altera devices, including support various FLEX 10KE 7000AE device package combinations. Table lists device package combinations supported software.
Table Devices Supported MAX+PLUS Software Version 9.21
Device Family
7000
Device
EPM7032AE EPM7064AE EPM7128A EPM7512AE
Package
44-pin PDIP, 44-pin TQFP 100-pin FineLine 256-pin FineLine 144-pin TQFP, 208-pin PQFP, 256-pin BGA, 256-pin FineLine 256-pin FineLine 256-pin FineLine 256-pin FineLine BGA, 484-pin FineLine
FLEX
EPF10K10 EPF10K30A EPF10K50E
EPF10K200E 599-pin PGA, 600-pin
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Devices Tools MAX+PLUS version 9.21 software also allows designers features available EPC2 configuration device. This version supports programmable pull-up resistors programmable JTAG USERCODE instruction EPC2 device. With version 9.21, users also issue JTAG command software that causes EPC2 device initiate configuration FLEX device board. Obtain MAX+PLUS License Files Altera site obtain your license file latest version MAX+PLUS software. need license file using MAX+PLUS software first time have recently renewed your subscription with Altera. Every time your subscription renewed (typically once year), must obtain license file. request your license file, need your software guard number (which 10-digit number beginning with host network interface card (NIC) number your Altera Your Altera printed mailing label communication receive from Altera, including quarterly News Views. web-based license generator also generates licenses MAX+PLUS BASELINE software. MAX+PLUS BASELINE Software MAX+PLUS BASELINE software free, entrylevel version MAX+PLUS software that replaces PLS-WEB software Site License software. MAX+PLUS BASELINE software version includes timing functional simulator. extensive device support capability makes MAX+PLUS BASELINE software most fullfeatured programming logic development software available free download from web. Designers license MAX+PLUS BASELINE software months requesting license file from Altera site http://www.altera.com. Table outlines features MAX+PLUS BASELINE software version 9.2. MAX+PLUS BASELINE software available download from Altera site; also available Altera Digital Library CD-ROM.
Table MAX+PLUS BASELINE Software Version Features
Feature Property
Device Support EPF10K10, EPF10K10A, EPF8452A, EPF8282A, EPF6010A, EPF6016, EPF6016A, EPM9320, EPM9320A devices; well 7000 (including 7000E, 7000S, 7000A, 7000AE), 5000, Classic device families Design Entry Schematic design entry Text-based design entry using Altera Hardware Description Language (AHDL) Interfaces popular tools Floorplan editing Hierarchical design management Library parameterized modules (LPM) Design Compilation Logic synthesis automatic fitting Automatic error location OpenCoreevaluation Altera MegaCorefunctions megafunctions from Altera Megafunction Partner Program (AMPPSM) partners Design Verification Functional timing simulation Timing analysis Creates output files with third-party simulators Programming Device programming Other Features On-line help
Note: Altera Stand-Alone Programmer (ASAP2) software, which stand-alone version MAX+PLUS Programmer application, program, verify, examine, test Altera devices without having full version MAX+PLUS software. ASAP2 software downloaded from Altera site ftp.altera.com.
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Technical
ARTICLES
Using Altera Devices Multiple Voltage Systems
Although 5.0-V interface been standard decades, move towards advanced process technology requires shift lower voltage levels. today's market, printed circuit boards (PCBs) assembled with mixture 5.0-V, 3.3-V, 2.5-V devices. accommodate this mixture, essential that these devices interface with systems differing supply voltages. Altera's MultiVoltI/O interface meets increasing demand compatibility with devices different voltages. MultiVolt interface separates power supply voltage from output voltage, enabling Altera devices powered specific core voltage level interface with devices other voltage levels. MultiVolt Interface 3.3-V power supply required 0.35-µm process technologies, 0.25-µm process technologies require 2.5-V power supply. Therefore, many today's devices require 5.0-V, 3.3-V, 2.5-V interface.
Table Altera MultiVolt Support
Device VCCINT
future, even lower voltage levels will required smaller geometry processes. accommodate future trends, Altera developed broadest range devices that support MultiVolt interface mixed-voltage system integration (see Table MultiVolt interface enables devices different voltages communicate mixed-voltage design environment. VCCINT pins power device core, VCCIO pins power buffers. Therefore, device core pins powered with separate supply voltages. However, VCCIO pins device with MultiVolt capability should supplied from same voltage level (e.g.,
2.5-V, 3.3-V 5.0-V Device Compatibility
2.5-V FLEX® 10KE devices, VCCINT pins must always connected 2.5-V power supply. With 2.5-V VCCINT level, input voltages compatible with 2.5-V, 3.3-V, 5.0-V inputs. VCCIO pins
Note
VCCIO Input Signal
Output Signal
FLEX 10K, FLEX 8000 FLEX 6000 (5.0 9000, 7000S EPF10K130V, EPF10K50V FLEX 10KA, FLEX 6000 (3.3 7000A, 7000AE FLEX 10KE APEX APEX 20KE
Notes: FLEX devices support 3.3-V pins with 5.0-V core, except 84-pin plastic J-lead chip carrier (PLCC) 240-pin quad flat pack (QFP) packages. 7000 family, EPM7032S EPM7064S devices 44-pin PLCC thin quad flat pack (TQFP) packages support 3.3-V pins with 5.0-V core. These devices have separate VCCINT VCCIO pins. pins EPF8282V device 5.0-V tolerant. Altera does recommend driving 5.0-V signals these 3.3-V devices.
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Technical Articles connected either 2.5-V 3.3-V power supply, depending output requirements. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. When using Altera's newer 3.3-V devices-including 3.3-V FLEX 6000 devices, well FLEX 10KA MAX® 7000AE devices-the VCCINT pins must connected 3.3-V power supply. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. EPF10K50V EPF10K130V devices must have their VCCIO pins connected Inputs driven 2.5-V, 3.3-V, 5.0-V systems with exception EPF10K50V EPF10K130V devices, which only driven 3.3-V 5.0-V systems. Altera's 5.0-V 7000, 7000S, 9000, FLEX 8000, FLEX 6000, FLEX devices support interfaces 3.3-V 5.0-V devices. When VCCIO pins connected 5.0-V power supply, output levels compatible with 5.0-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. transistor will continue conduct, preventing external pull-up resistor from pulling signal pull output 3.3-V device level 5.0-V CMOS device, open-drain driving trace that pulled through external pull-up resistor. open-drain never drives high, only tristate. When open-drain active, drives low. When open-drain inactive, tristated, trace pulls-up V-within device's operating conditions-by external resistor. Conclusion Altera MultiVolt interface allows designers seamlessly incorporate newer generation devices with devices varying voltage levels. PCBs often 2.5-V, 3.3-V, 5.0-V devices. MultiVolt interface enables device core specific voltage (2.5 while keeping pins compatible with 5.0-V, 3.3-V, 2.5-V logic levels. combination MultiVolt hot-socketing (see "Hot-Socketing" this page) allow Altera devices fulfill design requirement.
Hot-Socketing
Hot-socketing plug-in refers practice inserting removing board device from system board while system power When board plugged removed, cannot disturb system operation. Altera designed devices support hot-socketing. following features have been implemented Altera devices ease hot-socketing process: Devices driven before power-up without damaging device. Devices drive before during power Signal pins cannot drive VCCIO VCCINT power supply. Most 3.3-V 2.5-V Altera devices designed support hot-socketing without special design requirements. These devices include FLEX 10KA, FLEX 10KE, FLEX 6000 (3.3-V), 7000AE devices. continued page
5.0-V Compatibility
Altera devices 5.0-V compatible. Therefore, 3.3-V device drive 5.0-V device and, turn, driven 5.0-V devices. Also, when VCCIO Altera devices connected pins still driven 5.0-V signals because buffers still 5.0-V tolerant. only exception EPF8282V device, whose pins 5.0-V tolerant (see Table Note
5.0-V CMOS Compatibility
Altera 5.0-V devices with NMOS-only output buffers will meet 5.0-V levels. When voltage output exceeds approximately NMOS pull-up transistor cut-off mode. Therefore, output reach full 5.0-V level with external pullup resistor. make output signals from Altera 3.3-V devices compatible with 5.0-V CMOS, configure output pins open-drain pins. 3.3-V devices have CMOS driver; VOUT VCCIO, PMOS pull-up
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Technical Articles
Embedded Programming Using 8051 Microprocessor Byte-Code
In-system programming in-circuit reconfiguration embedded processor enables easy design prototyping, streamlines production, allows quick efficient in-field upgrades. Devices that support insystem programmability (ISP) in-circuit reconfigurablity (ICR) upgraded field downloading design information using ROM, FLASH cards, modems, other data links. This article outlines Altera® support embedded programming configuration using 8051 family microprocessors JamByte-Code File (.jbc). MAX+PLUS® software generates Files, which contain specific design information given IEEE Std. 1149.1 Joint Test Action Group (JTAG) chain topology. Application Note (Embedded Programming Using 8051 Processor Byte-Code) Application Note (Using Language Embedded Processor) more information 8051 processor support Byte-Code. 8051 Architecture devices. 8051 access Kbytes Kbytes RAM, extended paging additional memory. However, paging memory requires additional discrete logic between 8051 micro-processor associated memory, which slows access programming times. Many variants basic 8051 architecture exist, including different clock speeds MHz), 16-bit functions, Kbytes on-chip ROM. When programming devices that contain more than macrocells, Altera recommends using fastest 8051 microprocessor best programming times. Byte-Code Software Byte-Code Player, which coded programming language, File needed program configure Altera devices using 8051 processor. default configuration source code compatible with particular processor, code customized specific 8051 microprocessor. However, supporting compiler must able compile code. Byte-Code Player source code obtained contacting Altera Applications (800) 800-EPLD,
8051 family microprocessors inexpensive, easy use, proven platform managing simple processing tasks. 8051 architecture consists separate addressing. Figure illustrates 8051 architecture Figure 8051 Architecture applies memory. 8051 microprocessor retrieves executes instructions from "program memory". Part instruction execution involves controlling pins that provide access ROM, RAM, ports, addresses. example, when 8051 microprocessor receives instruction access external data, RAM, processor automatically toggles such that information retrieved stored appropriate internal registers. These actions performed automatically processor. 8051 processor retrieve programming configuration information from EPROM FLASH
Kbytes FFFFh
Program Memory
!PSEN
0000h
8051 Kbytes Port Data Memory FFFFh
JTAG Chain
0000h
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Technical Articles sending e-mail sos@altera.com. more information customize source code, Application Note (Embedded Programming Using 8051 Processor Byte-Code). ICR, also supported 8051 microprocessor, work together speed design process. simplify things further, source code provided make porting easier support ability upgrade variety device densities. This source code specific 8051 family microprocessors configuration altered 8051 microprocessor variant. Additionally, programming file generation offered MAX+PLUS software.
File generated using MAX+PLUS software, compiling existing ASCII-based File (.jam) into Byte-Code equivalent using stand-alone Byte-Code Compiler. compiler available from site http://www.jamisp.com. Figure shows store Figure 8051 Software Storage software 8051 embedded system. Although Figure shows File stored ROM, file could also stored executed RAM. either case, Byte-Code Player must 8051 processor, must have access File. Conclusion 8051 Byte-Code Player supports ISP, giving designer option performing in-field upgrades.
JTAG Chain !PSEN
Kbytes FFFFh Byte-Code File (.jbc)
Size 8051
Byte-Code Player Binary
0000h Kbytes
FFFFh
Size
Scratch Area 0000h
Hot-Socketing, continued from page These user pins dedicated input dedicated clock pins these devices driven before during power without device damage. Their pins drive before during power configuration. Additionally, there leakage current from I/O, dedicated input, dedicated clock pins VCCIO VCCINT pins before VCCIO VCCINT powered Therefore, these devices inserted into removed from) powered-up system board without damage without interfering with operation system board. During normal operation, these devices have input leakage current specified under operating conditions each device data sheet. This leakage current devices that support hotsocketing. Table shows leakage current that occur during hot-socketing.
better system flexibility, Altera designed these devices support hot-socketing operation.
Table Hot-Socket Leakage Current Altera Devices
Device
FLEX 10KA FLEX 10KE FLEX 6000 (3.3 7000AE 5.75
Condition
5.75
Maximum
Notes: These devices 5.0-V tolerant. Includes current from weak pull-up resistors cell. GCLRn pins 7000AE devices driven during hot-socketing. other pins driven 5.75 during hot-socketing. After hotsocketing, pins 5.0-V tolerant.
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Customer
architecture capacity FLEX device enabled Tech engineers include digital functionality 5950B single FLEX device.
Application
FLEX Device Creating Fully Featured, Compact Motion Controller
Recently, engineers Technology Inc. (Tech 80), manufacturer motion control products, goal: design new, fully featured four-axis servo motion controller that would compliant with PC/104 specification version 2.3. challenge functionality this complex controller onto board measuring just 3.55 3.78 inches. product would industry's first fully featured fouraxis motion controller PC/104 industry-required form factor. solution they chose simple: they took existing design that required larger board several devices ported single Altera® FLEX® device. resulting product 5950B fouraxis PC/104 servo motion controller (see Figure Because small size, controller useful packaging machinery, robotics, medical instrumentation. 5950B chipset consists 1401A digital signal processing (DSP) device Altera EPF10K30 device. FLEX Device Allows Enhancements architecture capacity FLEX device enabled Tech engineers include digital functionality 5950B single FLEX device, just PC/104 interface, shown Figure They were also able number enhancements design make controller more precise easier use. Tech engineers, precision control priority designing 5950B. FLEX device made possible design board's analog output section using true instrumentation-quality 16-bit digital-toanalog converter (DAC). 5950B, monotonic, adjusting compensate low-level deviations analog output circuitry ensuring servo loop stability. simplify set-up 5950B, Tech engineers eliminated jumpers potentiometers. default configuration board programmed into FLEX device factory; users easily reconfigure 5950B using setup software. embedded array block (EAB) architecture FLEX device, with capability implement on-chip memory, allowed Tech engineers configure internal register overlay powerful register addressing capabilities. addition, board space saved using FLEX device gave Tech designers opportunity other
Figure Technology Inc. 5950B Four-Axis PC/104 Servo Motion Controller
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Customer Application enhancements product, such greater protection, enhanced interface specifications, fuller axis signals. MAX+PLUS Software Speeds Development powerful simulation timing analysis features MAX+PLUS software shortened development time 5950B design project. MAX+PLUS Simulator allowed engineers verify project before committed hardware, shortening time needed transform their original design FLEX device. With Timing Analyzer, they could analyze project performance, tracing signal paths project determine critical speed paths. "The power ease MAX+PLUS development software helped minimize amount bench time needed bring product from design release," said Sandell, senior engineer Tech Four Products, During development process, engineers decided move analog circuitry onto plug-in daughter board. 5950B could then sold without analog circuitry offer cost savings
Figure 5950B Design Architecture
Clock Data Address Control Analog Motor Commands Motor Enable Outputs, Auxilary Outputs Drive Fault, Auxilary Outputs Programmable Debounce Digital Filtering, Decoding, Error Detection Software Setup Drivers Receivers Receivers Protection Home Limit Inputs Encoder Inputs Drivers Protection Digital Motor Outputs
customers only digital motor interface. That way, company could same design three other products addition 5950B. "This decision will allow maximize volume minimize cost PCB," said Burkett, Tech COO. basic Altera design worked well that Tech plans port other platforms where they already have designs. Designing exchanging interface will simple task that will minimize nonrecoverable engineering (NRE) costs development time. Converting core Altera design support circuitry will help company maximize product family coherence minimize costs. Conclusion Moving digital functionality 5950B into single EPF10K30 device saved Tech board space, design time, implementation costs. same time, design increased ease use, precision, flexibility 5950B motion controller. With Altera devices software, current future Tech motion control designs will benefit from easy integration system into single device.
"The power ease MAX+PLUS development software helped minimize amount bench time needed bring product from design release." -Jim Sandell, Senior Engineer, Tech
Contact Information: Technology Inc. Mendelssohn Ave. Minneapolis, 55427 (612) 542-9545 http://www.tech80.com
Data
Multiport Buffer Control Read/Write Control
Command Adjustment Auxiliary Capture Registers
Data Serializer
Analog Daughter Board Connector
Address Control Status
Drivers Protection
IRQs
Interrupt Control
Counters
Board Configuration
Software Jumper Control
Altera EPF10K30 Device
Current Limiting Filtering Altera Configurator Base Address Switch Serial EEROM
Encoder Power
Host
Technology 5950B Board
Axis Interface
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Questions
&ANSWERS
Programmable Logic Family Data Sheet "Using Altera Devices Multiple Voltage Systems" page
Does Programmer Object File (.pof) change between versions MAX+PLUS® software?
recompile design created older software version newer software version, identical, example, because different logic synthesis improved routing algorithms. Back-annotating your design locks down location logic, routing. Therefore, even change design assignments, routing still differ, resulting different programming file. latest version MAX+PLUS Programmer always read POFs created previous versions MAX+PLUS software.
MAX® 7000A, 7000AE, 7000S, 9000 device programming times vary depending whether Master Programming Unit (MPU), third-party programmer? Programming times 7000A, 7000AE, 7000S, 9000 devices using different programming hardware vary. Additionally, notice slower programming times when using slower programming hardware. particularly sensitive variations programming times, Altera recommends using incircuit testers fixed-algorithm devices (these devices have suffix ordering code). When using devices with in-circuit testers, programming times same each device. cannot in-circuit testers devices, faster reduce overall programming time. faster will eliminate differences programming times, does reduce overall programming time.
receive error: "Can't program configure device `EPFxxxx' multi-device JTAG chain-delete programming file from device information?" will receive this error create Serial Vector Format File (.svf) device chain that contains FLEX® device; FLEX devices support Files. Because file size configuration time, Files cannot used configure FLEX devices. Files used primarily in-circuit testers. Configuring FLEX devices with in-circuit testers recommended because when board with FLEX device removed from tester, configuration information lost. configure FLEX devices IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface using incircuit testers embedded processors, Jamor Byte-Code language. language interpreted language that optimized configuring devices JTAG interface. more information language, refer site http://www.jamisp.com.
doesn't PLS-WEB license work with MAX+PLUS BASELINE software?
PLS-WEB version 9.01 BASELINE version software both licensed using license.dat file have same feature set. However, because products different versions, licensing scheme contents FEATURE line license.dat file different. must appropriate FEATURE line software work properly. sample license file PLS-WEB version 9.01 shown below: FEATURE max2.es alterad 0000.00 15-jun 1999 uncounted D64F2D5DAE78 HOSTID=DISK_SERIAL_NUM=d8452f2f sample license file BASELINE version shown below (the text differs from PLS-WEB license): FEATURE maxplus2web alterad 1999.06 15-jun-1999 uncounted 626CE8C32D52 HOSTID=DISK_SERIAL_NUM=d8452f2f
What FLEX 10KE voltage supply levels VCCIO VCCINT?
FLEX 10KE devices, VCCINT must VCCIO either more information MultiVoltcapabilities FLEX 10KE devices, FLEX 10KE Embedded
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Questions Answers want license both versions software with same license file, combine FEATURE lines license.dat file. Then, point this file both PLS-WEB BASELINE software. down depending your design requirements) externally through pull-up down) resistor. Other FLEX 10KE devices have weak pull-up resistors that activated before during configuration. FLEX 10KE Embedded Programmable Logic Family Data Sheet more information.
Files (.jam) Byte-Code Files (.jbc) ASCII binary file types, respectively. Although information contained each file unique, files have consistent format. Therefore, your EPROM FLASH memory programmer convert these files format programmer use. example, device programmer read ASCII files program EPROM FLASH device automatically. FLASH devices that programmed system, contact FLASH vendor information about format data that sent FLASH device during programming. Additionally, wide variety conversion utilities available that convert ASCII binary files number required output formats programming various memory technologies.
convert Files (.jam) Byte-Code Files (.jbc) storage embedded memory?
perform JTAG testing JTAG chain containing EPM7032S and/or EPM7064S devices, which have boundary-scan test circuitry? EPM7032S EPM7064S devices contain JTAG boundary-scan test circuitry; however, they contain JTAG test access port (TAP) controller. Additionally, these devices contain circuitry necessary ensure that they interfere with JTAG test operation. Therefore, systems that support in-system programmability (ISP) have these devices JTAG chain. devices allow following JTAG instructions: Instructions-The devices' JTAG controller allows JTAG-compliant instructions, which used send instructions data device in-system programming. BYPASS-When either device included JTAG chain, device must bypassed. support this function, these devices contain JTAG BYPASS instruction. EXTEST SAMPLE/PRELOAD-These devices support EXTEST SAMPLE/PRELOAD instructions even though they cannot tested because test tools often send EXTEST SAMPLE/PRELOAD instructions devices chain. Although EPM7032S EPM7064S devices cannot tested when these instructions loaded, boundary-scan register length selected. JTAG specification allows EXTEST SAMPLE/PRELOAD instructions have pattern. EPM7032S EPM7064S devices have different patterns than other members family that have full JTAG boundary-scan test circuitry. boundary-scan description language (BSDL) file these devices represents patterns select these instructions. JTAG information these devices contained their respective BSDL files, which available Altera site.
JTAG Chain Files (.jcf) contain name location Programmer Object File(s) (.pof) needed program device. does contain actual POFs. receive this error message load into MAX+PLUS software using Multi-Device JTAG Chain dialog (JTAG menu) location POFs referenced file changed. avoid this error, make sure location POFs does change, example saving POFs same directory.
error: "Can't open file <filename>.pof" (JTAG Chain File)?
EPF10K100B devices have weak pull-up resistors. During configuration, pins tri-stated voltage these pins undefined. these pins connected input pins that must known voltage level, these pins should pulled-up
EPF10K100B devices have weak pull-up resistors during configuration?
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Technical Articles
APEX Devices Feature Product-Term Mode
Altera® APEX20K devices feature revolutionary MultiCorearchitecture, which combines strengths look-up table (LUT) product-term logic. integration these architectures makes APEX devices well suited APEX Architecture basic building block APEX family MegaLABstructure, which contains logic array blocks (LABs), each comprised logic elements (LEs). APEX MegaLAB structure also embedded system block (ESB) that configurable 2,048-bit RAM, ROM, content addressable memory (CAM), product-term macrocells. Each macrocell contains product terms that combined through gate gate, programmable inverter wide-input functions. output each macrocell registered, with each register containing clock enable asynchronous clear. Additionally, macrocell includes parallel expanders that feed adjacent macrocell. Parallel expanders improve system performance routability, making product-term architecture ideal applications that require wide multiplexing high fan-in. Improved Performance MultiCore architecture improves system performance because product-term architecture provides higher performance combinatorial
Table APEX Performance Common Applications
Function Product Terms Performance (MHz)
32-bit gate with registered inputs outputs 8-state, 6-input/11-output, 148-transition state machine 16-to-1 registered multiplexer registered multiplier
functions such address decoding state machines, while architecture contributes superior performance registered data path functions. Off-chip delays that would occur design used separate product-term devices eliminated. Figure shows system performance using separate product-term devices, including typical off-chip delay. Figure shows system performance with integrated productterm architectures.
Figure System Performance Using Separate Devices
EPF10K100E-1
Register Product Term
EPM7064AE-4
Register
Delay
Figure System Performance APEX 20K-1 Devices
APEX 20K-1
Register Product Term Register
tLAD
Delay
Performance Comparison LUTs Performance (MHz)
Ideal Solution Product Term
Utilization
product term (die size equivalent logic elements) product terms (die size equivalent logic elements) product terms (die size equivalent logic elements) product terms (die size equivalent 1,097 logic elements)
Utilization
logic elements logic elements logic elements logic elements
Note: Count does include input registers.
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Technical Articles Design functionality such wide-input functions state machines implemented more efficiently because architectures device results better performance device utilization. Table shows performance common functions implemented product terms LUTs, gives corresponding device utilization each implementation. product terms require same area LEs. wide-input gate state machine faster implemented more efficiently product-term architecture, while multiplier multiplexer better implemented LUT. Quartus Software Support Quartussoftware configure block macrocells ESB-by-ESB basis, allowing maximum flexibility. following modes available: product-term, RAM, ROM, CAM, LUT. more information APEX devices Quartus software, contact Altera Applications (800) 800-EPLD visit Altera site http://www.altera.com.
Altera
Revolutionary Quartus Software Enhances Design Process
Programmers design compile much more efficiently with Altera's Quartusdevelopment system. This revolutionary software, combined with Altera® APEXarchitecture, allows designers exceed one-million-gate mark. size complexity APEX devices create additional challenges when implementing design. Quartus software simplifies entire design process, allowing programmers work more efficiently shorten their time-to-market. There many features found Quartus development system enhance design productivity: Workgroup computing-Multiple designers work single project with global file management design revision control. Integrated logic analysis functionality-The SignalTaplogic analyzer within software offers system-level verification devices running speed, which significantly reduces verification times. tool integration-The NativeLinkinterface connects Quartus software seamlessly from other synthesis design verification tools, also reducing verification times. more information NativeLink feature, "NativeLink Integration Offers Seamless Interface with Tools" page Multi-processor support-Computer-intensive functions distributed multiple processors locally, across networks, across operating systems, reducing compilation times. Incremental compilation-The nSTEPCompiler permits fast, multiple iterations small portions design, offering huge savings compilation time. Intellectual property (IP) integration-A block-based design orientation allows easy integration megafunctions with OpenCoreevaluation MegaWizardPlug-In parameterization; blocks placed optimize timing. Improved quality results-The CoreSynsynthesis capability used invoke appropriate synthesis technology determine optimal mapping design device architecture. Compiler analyzes design then partitions functions into appropriate type memory within APEX architecture. more information CoreSyn feature, "CoreSyn Synthesis" page Internet connectivity-The Quartus software "web-aware," with latest Internet browser technology built customers have purchased Altera subscription product will receive Quartus software when released. purchase Altera subscription product, contact your local Altera sales office.
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Altera Technical Seminars Provide System-on-a-Programmable-Chip Solution
Altera invites attend free technical seminar, providing with information need stay ahead your competition. You'll learn details Altera® APEXarchitecture, demonstrations revolutionary Quartusdevelopment system, learn devices software support These revolutionary products offer design flexibility, performance, density need your products market faster, more North America
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easily, lower cost than ever imagined possible. North American customers reserve their space nearest free Altera technical seminar either registering Altera site http://www.altera.com/seminar calling (800) 9-ALTERA. International customers should register Altera site call their local Altera representative register European Asian seminars.
North Carolina Raleigh, Research Triangle Park Ohio Fairborn Oregon Beaverton Texas Austin Richardson Utah Salt Lake City Washington Bellevue
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Altera News
Newest AMPP Partner Offers SONET, Test Boards
Altera's latest Altera Megafunction Partner Program (AMPPSM) partner, Innocor, licenser original equipment manufacturer (OEM) data communication products based Ontario, Canada. company provides customers with design services that target Altera® devices. Founder Randy Gill first designed with Altera devices tools while working Nortel. 1995, used knowledge data communication designs build 11-person engineering team: Innocor.
ALTERA MEGAFUNCTION PARTNERS PROGRAM
ATM, intellectual property demonstration development platform. Innocor offers megafunctions that designed, optimized, marketed exclusively Altera's programmable logic devices (PLDs). Their list Altera-specific products includes:
Innocor developed OC-1/OC-3 tester product from their data communication megafunctions. Innocor TestPoint OC-1/OC-3 tester, shown Figure includes customizable embedded server showcases Innocor's Synchronous Optical Network (SONET), asynchronous transfer mode (ATM), Packet Over SONET (POS) functions optimized Altera devices. using retargetable architecture featuring Altera EPF10K100A device, Innocor able provide cost-effective feature migration path. With SONET, ATM, test capabilities, this premier product supports extensive feature set. Additionally, when TestPoint OC-1/OC-3 tester configured with modified software image, used versatile SONET,
8030 serial commmunications controller Monosync/bisync controller SDLC/HDLC controller Data encoder/decoder Cyclic redundancy code (CRC) generator/detector Digital phase-locked loop (PLL) 8036 8259 programmable interrupt controller (PIC) SONET byte telecommunication interface SONET VT1.5 mapper SONET VT1.5 extractor over SONET controller
Innocor extensive experience producing high quality designs real-world data communication applications using Altera devices. Partnering with Altera Innocor greatly reduce your design costs time-to-market. Innocor solution extends well beyond megafunctions include extensive customer support, design consultation, commitment product evolution. Figure Altera EPF10K100A Device Featured Innocor's TestPoint
OC-1/OC-3 Tester
additional information, including pricing, contact Innocor Ltd. Innocor Ltd. Attn: Randy Gill Mill Street, Suite Almonte, Canada Tel: (613) 256-5339 Fax: (613) 256-5161 info@innocor.com http://www.innocor.com
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Altera Technical Training Program
Altera Technical Training Program offers customers wealth information Altera devices efficiently. These classes explain designs implemented achieve optimal performance. Courses that focus almost Altera's devices available, software courses highlight MAX+PLUS® software, VHDL, Verilog HDL. These classes teach increase productivity, accelerate product development, resources effectively from these classes. following courses currently offered Altera Technical Training Program: Introduction Altera Achieving High Performance Optimal Utilization FLEX® Devices Achieving High Performance Optimal Utilization FLEX 6000 FLEX 8000 Devices Optimizing Designs MAX® 9000 Devices Optimizing Designs 7000 Devices Designing with MAX+PLUS Software Designing with MAX+PLUS Software Using AHDL Introduction VHDL Designing with MAX+PLUS Software Using VHDL Introduction Verilog Optimizing Verilog Code Altera Devices Tools Optimizing FLEX Designs with Synopsys MAX+PLUS Training classes offered throughout North America during entire year. enroll classes North America Altera site http://www.altera.com. Classes also offered internationally Asia, Europe, Middle South America. information international class availability enrollment, Altera site.
ASSET Provides First Tools Suite Supporting Both Programming
ASSET InterTech, market leader boundary-scan testing insystem programmability (ISP) longtime leader standardization process, released version ASSET suite tools. addition providing several boundary scan test features, this release makes ASSET first boundary-scan system that supports both Jamprogramming test language Serial Vector Format (SVF) test programming language. With release ASSET, files from programmable logic device (PLD) vendor used perform in-system programming either standalone programming station integrated part manufacturing test flow. ASSET supports version submitted JEDEC September 1997 standardization. Both Altera ASSET look forward approval JEDEC standard because standard language eases development tool support boundary-scan testing. open specification that used perform develop boundary-scan tests. specific product information details ASSET version 2.3, visit ASSET site contact company directly. ASSET InterTech, Inc. 2201 Central Expressway, Suite Richardson, 75080 Tel: (972) 437-2800 Toll-free: (888) 694-6250 http://www.asset-intertech.com
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Every
Altera Publications
publications available from Altera Literature Services. Individual documents available Altera site http://www.altera.com. Document part numbers shown parentheses.
Third-Party Programming Support
Data Microsystems provide programming hardware support selected Altera devices. Algorithms supplied Data I/O's Keep Current Express-Bulletin Board Service (KCE-BBS) Microsystems' BBS. Programming support configuration, MAX® 9000, 7000 devices shown Table information subject change.
Table Third-Party Programming Hardware Support
Device
EPC1064 EPC1213 EPC1 EPC1441 EPM7032 EPM7032S EPM7032AE EPM7064 EPM7064S EPM7064AE EPM7096 EPM7128E EPM7128S EPM7128A EPM7160E EPM7192E EPM7192S EPM7256E EPM7256A EPM7256S EPM7512AE EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
Data
Microsystems
Altera Digital Library CD-ROM, version (P-CD-ADL-05) APEX Programmable Logic Device Family Data Sheet (A-DS-APEX20K-01) Guidelines Handling J-Lead, Devices (A-AN-071-04) Selecting Sockets Altera Devices (A-AN-080-03) Reflow Soldering Guidelines Surface-Mount Devices (A-AN-081-03) SameFrame Pin-Out Design FineLine Packages (A-AN-090-01) 102: Improving Performance FLEX Devices with Leonardo Spectrum Software (A-AN-102-01) 106: Designing with 2.5-V Devices (A-AN-106-01) SDRAM Controller Megafunction (A-SB-038-01)
Programming Hardware Support
Table provides programming configuration compatibility information BitBlasterserial port ByteBlaster MVparallel port download cables. (The ByteBlasterdownload cable been replaced with ByteBlaster cable.)
Table Download Cable Compatibility
Device
FLEX FLEX 10KA FLEX 10KE FLEX 8000 FLEX 6000 9000 9000A 7000S 7000A
BitBlaster
ByteBlasterMV
Notes: These devices supported Data 3900 version UniSite version programmers. These devices supported Microsystems programmers version 3.38. Please contact Data Microsystems programming support these devices.
Note: FLEX® 6000 family, this download cable only compatible with EPF6016 devices.
continued page
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February 1999
Every Issue Programming Hardware Support, continued from page Altera Programming Adapters following table contains latest programming hardware information Altera® devices. correct programming, software version shown "Current Software Version" page Table lists Altera programming adapters MAX® 9000, 7000, configuration devices.
Table Altera Programming Adapters (Part
Device
EPC1064 EPC1064V (2), EPC1441 EPC1 EPC1213 EPC2 EPM9320 J-lead TQFP J-lead (84-pin) RQFP (208-pin) (280-pin) EPM9320A J-lead (84-pin) RQFP (208-pin) EPM9400 J-lead (84-pin) RQFP (208-pin) RQFP (240-pin) EPM9480 RQFP (208-pin) RQFP (240-pin) EPM9560 RQFP (208-pin) RQFP (240-pin) (280-pin) RQFP (304-pin) EPM9560A RQFP (208-pin) RQFP (240-pin) EPM7032, EPM7032V J-lead (44-pin) PQFP (44-pin) TQFP (44-pin) EPM7032S, EPM7032AE EPM7064 J-lead (44-pin) TQFP (44-pin) J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin) PLMJ1213 PLMT1064 PLMJ9320-84 PLMR9000-208 PLMG9000-280 PLMJ9320-84 PLMR9000-208NC PLMJ9400-84 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMG9000-280 PLMR9000-304 PLMR9000-208NC PLMR9000-240NC PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100
EPM7512AE EPM7384AE TQFP (144-pin) PQFP (208-pin) TQFP (144-pin) PQFP (208-pin) (256-pin)
Table Altera Programming Adapters (Part
Device
EPM7128, EPM7128E
Note
Package
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
Adapter
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMT7000-100NC PLMT7000-144NC
EPM7128A
J-lead (84-pin) TQFP (100-pin) TQFP (144-pin)
Note
FineLine (100-pin) PLMF7000-100 FineLine (256-pin) PLMF7000-256 EPM7128AE FineLine (100-pin) PLMF7000-100 FineLine (256-pin) PLMF7000-256
Package
DIP, J-lead TQFP
Adapter
PLMJ1213 PLMT1064
DIP, J-lead
PLMJ1213
EPM7128S
J-lead (84-pin) PQFP (100-pin) TQFP (100-pin) PQFP (160-pin)
PLMJ7000-84 PLMQ7000-100NC PLMT7000-100NC PLMQ7128/7160-160NC PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMQ7128/7160-160NC PLMG7192-160 PLMQ7192/7256-160 PLMQ7192/7256-160NC PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMR7256-208
EPM7160E
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7160S
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7192E
(160-pin) PQFP (160-pin)
EPM7192S EPM7256E
PQFP (160-pin) PQFP (160-pin) (192-pin) PQFP (208-pin) RQFP (208-pin)
EPM7256A EPM7256A EPM7256S
EPM7256AE
FineLine (256-pin) PLMF7000-256 PQFP (208-pin) RQFP (208-pin)
FineLine (256-pin) PLMF7000-256 PLMT7000-144NC PLMR7256-208NC PLMT7000-144NC PLMR7256-208NC PLMB7000-256
PLMR7256-208NC PLMT7000-208NC
FineLine (100-pin) PLMF7000-100
FineLine (256-pin) PLMF7000-256
EPM7064AE EPM7064S, EPM7064AE
FineLine (100-pin) PLMF7000-100 J-lead (44-pin) J-lead (84-pin) TQFP (44-pin) TQFP (100-pin) PLMJ7000-44 PLMJ7000-84 PLMT7000-44 PLMT7000-100NC PLMJ7000-68 PLMJ7000-84 PLMQ7000-100
EPM7096
J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
Notes: Refer Altera Programming Hardware Data Sheet device adapter information 5000 Classicdevices. Altera offers adapter exchange program EPM5032, EPM5064, EPM5130 programming adapters. FLEX® 8000 configuration device. FLEX 10K, FLEX 8000, FLEX 6000 configuration device. These devices shipped carriers.
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Altera Offers Over Megafunctions
Altera® digital signal processing (DSP) solutions provide optimized performance that ideal real-time, high-performance OpenCore applications such satellite communications, digital image processing, spread-spectrum systems. Altera offers variety products from basic building block megafunctions, such filters high-speed multipliers, more complex megafunctions such Reed-Solomon Viterbi Decoders.
Megafunctions ready-made, pre-tested blocks intellectual property (IP) that optimized make
target architecture efficiently. using megafunctions, designers focus more time energy improving differentiating their system-level product, rather than redesigning common functions. download Altera MegaCore function from Altera site evaluate free before purchase using OpenCorefeature found MAX+PLUS® software. also email request OpenCore version almost every Altera Megafunction Partner Program (AMPPSM) megafunction Altera website. most upto-date information about Altera megafunctions, Altera site. Contact Altera your local sales office more information.
Building Block Megafunctions
Function
Filter Compiler Convolutional Interleaver/Deinterleaver Fast Fourier Transform Fast Fourier Transform (FFT/IFFT) Filter Library Floating-Point Adder Floating-Point Divider Floating-Point Multiplier Filter Library Median Filter Library Multi-Standard ADPCM Rank Order Filter Library Parameterized Floating-Point Adder/Subtractor Parameterized Integer Divider Parameterized Floating-Point Multiplier Data Word Rounder Data Word Saturator
Wireless Broadband Communication Megafunctions
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Function
Adaptive Equalizer Adaptive Equalizer Adaptive Filter Binary Pattern Correlator Convolutional Encoder Block Convolutional Interleavers/Deinterleavers Complex Mixer/Multiplier Convolutional Interleaver (Cable Modem PCS) Cordpol Function DES-Core DES-Core Canada Only) DES-Core Digital Modulator Early/Late Gate Symbol Synchronizer FFT/IFFT Linear Feedback Shift Register Zero-Forcing Equalizers Numerically Controlled Oscillator QPSK Equalizer
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Error Control Coding Megafunctions
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Checker/Generator Convolutional Encoder Convolutional Interleaver Reed-Solomon Encoder Intermediate Data Rate (IDR) Framer/Deframer Reed-Solomon Decoder Reed-Solomon Decoder Reed-Solomon Encoder Viterbi Decoder Viterbi Decoder
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Altera Device Selection Guide
Current information Altera APEX20K, FLEX® 10K, FLEX 8000, FLEX 6000, MAX® 9000, 7000 devices listed here. Information other Altera products located Altera Component Selector Guide. most up-to-date information, Altera site http://www.altera.com. Some products listed available yet. Contact Altera your local sales office current product availability.
APEX Devices
DEVICE
EP20K100
GATES
100,000
PIN/PACKAGE OPTIONS
144-Pin TQFP, 196-Pin BGA1, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA1, 356-Pin
SUPPLY VOLTAGE
LOGIC ELEMENTS
4,160
BITS
53,248
MACROCELLS
EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E
100,000 160,000 200,000 200,000 300,000 400,000 400,000 600,000 1,000,000
144-Pin TQFP, 196-Pin BGA1, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 400-Pin BGA1
4,160 6,400 8,320 8,320 11,520 16,640 16,640 24,320 42,240
53,248 81,920 106,496 106,496 147,456 212,992 212,992 311,296 540,672
1,152 1,664 1,664 2,432 4,224
208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1, 672-Pin BGA1 208-Pin PQFP, 240-Pin PQFP, 484-Pin BGA1 208-Pin RQFP, 240-Pin RQFP, 672-Pin BGA1
652-Pin BGA, 655-Pin PGA, 672-Pin BGA1 208-Pin RQFP, 240-Pin RQFP, 672-Pin BGA1 672-Pin BGA1, 900-Pin BGA1
900-Pin BGA1, 984-Pin
Notes: This package space-saving FineLine BGApackage. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
vices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E
GATES
10,000 10,000 20,000 30,000 30,000 30,000 40,000 50,000 50,000 50,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1, 356-Pin BGA, 484-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1, 484-Pin BGA1 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1, 356-Pin BGA, 484-Pin BGA1
PINS
102, 102, 134, 102, 147, 147, 189, 102, 147, 189, 191, 246, 102, 147, 176, 147, 189, 274, 189, 274, 102, 147, 189, 191, 2562, 189, 189, 274, 369, 147, 189, 147, 189, 191, 2742, 470, 186, 2742, 369, 4262, 1822, 2742, 3802, 470, 470,
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728 1,728 2,304 2,880 2,880 2,880
BITS
6,144 6,144 12,288 12,288 12,288 24,576 16,384 20,480 20,480 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E
70,000 100,000 100,000 100,000 100,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1, 600-Pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1, 356-Pin BGA, 484-Pin BGA1
3,744 4,992 4,992 4,992 4,992
18,432 24,576 24,576 24,576 49,152
EPF10K130V EPF10K130E
130,000 130,000
599-Pin PGA, 600-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA1, 600-Pin 672-Pin BGA1
6,656 6,656
32,768 65,536
EPF10K200E
200,000
240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1, 599-Pin PGA, 600-Pin BGA, 672-Pin
9,984
98,304
EPF10K250A
250,000
599-Pin PGA, 600-Pin
12,160
40,960
Notes: This package space-saving FineLine package. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
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FLEX 8000 Devices
DEVICE
EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A
GATES
2,500 2,500 4,000 6,000 8,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 100-Pin TQFP 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin
PINS
118, 136, 112, 120, 152, 152, 148, 184, 181, 208,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
LOGIC ELEMENTS
EPF81188A EPF81500A
12,000 16,000
208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
1,188 1,500
1,008 1,296
FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A
GATES
10,000 16,000 16,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 100-Pin BGA1, 256-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1
PINS
117, 812, 1392 117, 171, 199, 1172, 171, 2182 117, 171, 199, 218, 2182
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320
LOGIC ELEMENTS
1,320 1,320
EPF6024A
24,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin BGA1
1,960
1,960
Notes: This package space-saving FineLine package. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
Configuration Devices APEX FLEX Devices
DEVICE
EPC1064 EPC1064V EPC1213 EPC14411 EPC11 EPC21
PIN/PACKAGE OPTIONS
8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 20-Pin PLCC, 32-Pin TQFP
SUPPLY VOLTAGE
3.3/5.0 3.3/5.0 3.3/5.0
DESCRIPTION
64-Kbit serial configuration device designed configure FLEX 8000 devices 64-Kbit serial configuration device designed configure FLEX 8000 devices 213-Kbit serial configuration device designed configure FLEX 8000 devices 441-Kbit serial configuration device designed configure FLEX devices 1-Mbit serial configuration device designed configure APEX FLEX devices 2-Mbit serial configuration device designed configure APEX FLEX devices
Note: This device programmed user operate either
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-15, -15, -15, -15,
continued page
Current Software Version
latest version Altera software product MAX+PLUS® version 9.21. MAX+PLUS development system available Windows-based SPARCstation, 9000 Series 700/800, RISC System/6000 platforms.
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7000 Devices
DEVICE
EPM7032AE EPM7032S EPM7032 EPM7064AE EPM7064S EPM7064 EPM7096 EPM7128A EPM7128AE EPM7128S EPM7128E EPM7160S EPM7160E EPM7192S EPM7192E EPM7256A EPM7256AE
MACROCELLS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP
PIN/PACKAGE OPTIONS
PINS
SUPPLY VOLTAGE
SPEED GRADE
-10, -12, -10, -12, -10, -12, -10, -5,-7,-10 -10, -10, -12, -15, -10, -10, -12, -15, -10, -12, -15, -10,
44-Pin PLCC/TQFP/PQFP 44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin BGA1 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1
100, 100, 120, 164, 120, 164,
84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP/PGA 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 100-Pin BGA1, 256-Pin BGA1 256-Pin
EPM7256S EPM7256E EPM7512AE
208-Pin RQFP/PQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1, 256-Pin
132, 120, 176, 212,
-10, -12, -15, -10,
Note: This package space-saving FineLine package.
Contact Altera
Getting information services from Altera easier than ever. table below lists some ways reach Altera:
Information Type
Literature
Access
Altera Literature Services World-Wide
U.S. Canada
(888) 3-ALTERA lit_req@altera.com http://www.altera.com (800) SOS-EPLD (408) 544-6403 (800) 800-EPLD (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Other Locations
(408) 544-7144 lit_req@altera.com http://www.altera.com (408) 544-7000 (408) 544-6403 (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Non-Technical Customer Service Telephone Hotline Technical Support Telephone Hotline a.m. p.m. Pacific Time) Electronic Mail Site General Product Information Telephone World-Wide
Notes: MAX+PLUS Getting Started manual available from Altera site. obtain other MAX+PLUS software manuals, contact your local distributor. also contact your local Altera sales office sales representative. Altera site listing.
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