Raphaelprogrammable logic device (PLD) family, based revolutionary Mul

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Raphael: Embedded Family System-Level Integration
Raphaelprogrammable logic device (PLD) family, based revolutionary MultiCorearchitecture, meets system-level design challenges offering complete system integration single device. Ranging from 100,000 over million gates manufactured using 6-layer-metal process, 0.25-µm, 2.5-V Raphael devices will extend Altera's leadership embedded architectures levels efficiency performance. Raphael devices give designers ultimate design flexibility they efficiently address much larger designs broader range applications. System-Level Features Raphael devices contain powerful system-level features that offer design flexibility high-performance system-on-a-chip functionality, including:
Enhanced phase-locked loop (PLL) supporting clock multiplication System performance over MHz, well 64-bit, 66-MHz peripheral component interconnect (PCI) compliance 1.0-mm FineLine BGApackaging that uses only half board area traditional ball-grid array (BGA) packages
Embedded Architecture Breakthrough Raphael devices provide single-chip solution complex system design, saving board space simplifying system design implementation. Raphael MultiCore architecture combines enhances strengths FLEX® 6000, 7000, FLEX architectures, shown Figure permits designers integrate entire system into single device.
MultiCore embedded architecture with embedded product terms, highspeed dual-port RAM, contentaddressable memory (CAM) Enhanced 4-level FastTrack Interconnectrouting structure, which features MegaLABinterconnect Support existing emerging standards including low-voltage transistor-to-transistor logic (LVTTL), low-voltage complementary metal-oxide semiconductor (LVCMOS), stub-series terminated logic (SSTL-3), Gunning transceiver logic (GTL/GTL+), low-voltage differential signaling (LVDS)
Figure Raphael Incorporates LUTs, Product Terms, Embedded Memory
FLEX 6000 Interleaved LABs Structure Structure 7000 Product Terms Wide Fan-In Fast State Machines
Raphael
FLEX Interconnect Structure Embedded Memory Phase-Locked Loop High Density
continued page
Altera Corporation
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Contents
Features Raphael: Embedded Family System-Level Integration Contributed Article: ASSET InterTech Provides Low-Cost Test Support Altera Viewpoint: Next-Generation Tool Requirements Altera News Customer Training Brings Speed SameFrame Pin-outs FineLine Packaging ACAP: Outsourcing Design Development Achieving Cost Efficiency Altera 1998 1998 ICSPAT/DSP World Coming Soon: Altera Digital Library Devices Tools Design FLEX 10KE Today 250,000-Gate EPF10K250A Devices Shipping 2.5-V EPF10K100B Device Available Entire 3.3-V FLEX 10KA Family Available EPF6010A EPF6016A Devices Available FLEX 6000 Devices Coming Soon EPC2 Device Available October 9000A Device Availability 7000 9000 Product Transitions
Altera In-Circuit Tester Support 7000AE Devices 7000A Availability 7000S Devices Discontinued Devices Update Features Available MAX+PLUS Version 9.01 Network Licensing MAX+PLUS Version 9.01 Version-Controlled Licensing MAX+PLUS Version
Technical Articles FLEX 10KE Provides Advanced Features Guidelines Using Implementing FIFO Solutions Altera Devices with FIFO MegaWizard Plug-In Questions Answers Introducing Byte Code Every Issue Altera Publications Third-Party Programming Support Current Software Version Programming Hardware Support Altera Device Selection Guide Contact Altera Response Form
information about this newsletter, submit questions, contact: Erica Heidinger, Publisher Greg Steinke, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 E-mail: n_v@altera.com
Printed recycled paper.
Altera, ASCEND, AMPP, BitBlaster, ByteBlaster, ByteBlasterMV, Classic, FastTrack Interconnect, FineLine BGA, FLEX, FLEX 10K, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Jam, µPitch, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 7000AE, 5000, MAX, MAX+PLUS, MAX+PLUS MegaCore, MegaLAB, MegaWizard, MultiCore, MultiVolt, OpenCore, Raphael, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Advin Systems registered trademark Advin Systems, Inc. Verilog Cadence registered trademarks Cadence Design Systems. Exemplar Logic registered trademark Exemplar Logic, Inc. Integrated Silicon Systems registered trademark Integrated Silicon Systems, Inc. Mentor Graphics registered trademark Mentor Graphics, Inc. Data registered trademark Data Corporation. registered trademark Microelectronics, Inc. Synopsys registered trademark Synopsys, Inc. Synplicity registered trademark Synplicity, Inc. Viewlogic registered trademark Viewlogic Systems. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1998 Altera Corporation. rights reserved.
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Features Raphael: Embedded Family System-Level Integration, continued from page Altera pioneered embedded architecture 1995 with introduction FLEX family. Raphael device's revolutionary MultiCore embedded architecture takes embedded concept level with innovative combination three different types structures: look-up tables (LUTs), like those found FLEX devices; product-term arrays, like those found devices; enhanced embedded memory blocks, like those found FLEX 10KE devices. Together, these structures make integration complex functions such megafunctions easy efficient process. Raphael architecture embedded system block (ESB). offers embedded productterm capability with fast 3.9-ns performance. Many system designs today implemented with multiple FLEX devices. However, where designs with multiple devices suffer from on-device/off-device delays that decrease system performance, Raphael devices integrate product-term capability offer vastly improved system speeds. Figure shows example system speed improvements that achieved with Raphael devices. Raphael configured product-term logic, dual-port RAM, read-only memory (ROM), CAM. This system-level memory integration efficiently supports various memory requirements system-level design, such cache RAM, dual-port first-in first-out (FIFO) buffers, ROM. accelerates search applications such databases, lists, patterns, high-speed communication applications. Unlike RAM, which looks data specific address, looks data memory outputs address. With speeds over MHz, Raphael faster than traditional CAM. Raphael ESBs located MegaLAB structure, shown Figure page Each MegaLAB consists logic array blocks (LABs) composed logic elements (LEs). MegaLABs connected internally MegaLAB interconnect, which adds fourth hierarchical level continuous metal FastTrack Interconnect routing structure, increasing both performance efficiency. Low-Voltage Support trend toward system integration, higher performance requirements, lower supply voltages makes imperative devices support multiple low-voltage standards. Raphael devices offer continued page
Figure Integrated Product-Term Performance Capability Improves System Speeds
Raphael
EPF10K100E-1
Register
EPM7064S-5
Product Terms Register
Speed Grade Raphael Device
Register Product Terms Register
tLAD
Delay
Delay
Altera Corporation
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August 1998
Features Raphael: Embedded Family System-Level Integration, continued from page selectable support LVTTL, LVCMOS, SSTL-3, GTL/GTL+, LVDS standards, allowing high-speed interfacing between SDRAMs, processors, system backplanes. Raphael devices also support Altera MultiVoltI/O interface 3.3-V, 2.5-V, 1.8-V mixed voltage systems. Raphael Family Members system-level features take PLDs into next generation flexible, system-on-a-chip design. These complex devices require advanced software tool-Altera developing software meet this challenge. Using revolutionary Raphael architecture Altera's next-generation software, designers find ideal programmable logic solution system-on-a-chip applications. further details, visit Altera world-wide site http://www.altera.com contact your local representative.
Raphael device family ranges from 100,000 over million usable gates logic will introduced 0.25-µm, six-layer-metal SRAM process, with plans migrate 0.18-micron, six-layer-metal process then 0.15-micron, seven-layer-metal process. Table Figure Raphael MegaLAB outlines Raphael family. Availability Packaging first Raphael family member, 400,000-gate R400, planned ship 1999. expected available 208-pin quad flat pack (QFP), 240-pin packaging, 599-pin pin-grid array (PGA), well 1.0-mm pitch FineLine BGApackaging. Conclusion Altera's Raphael device family density, performance,
Table Raphael Family Features
Feature
Maximum gates Typical gates Maximum macrocells Maximum pins Packages, Note FineLine 144-pin TQFP 208-pin 240-pin FineLine 144-pin TQFP 208-pin 240-pin FineLine 208-pin 240-pin FineLine 208-pin 240-pin FineLine 208-pin 240-pin 599-pin FineLine FineLine MegaLAB Interconnect
LAB0 LAB1 LAB15
Logic Element (LE) 4-Input Flipflop Carry Cascade Chains
Embedded System Block (ESB)
Logic Array Block (LAB) MegaLAB LABs
MegaLAB
R100
263,000 53,000 106,000 4,160
R160
404,000 82,000 163,000 6,400 81,920
R200
526,000 106,000 211,000 8,320 106,496
R300
728,000 147,000 293,000 11,520 147,456 1,152
R400
1,052,000 213,000 423,000 16,640 212,992 1,664
R500
1,294,000 262,000 520,000 20,480 262,144 2,048
R1000
2,670,000 541,000 1,073,000 42,240 540,672 4,224
Maximum bits 53,248
Note: TQFP: thin quad flat pack, QFP: quad flat pack, BGA: ball-grid array, PGA: pin-grid array.
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Devices
Design FLEX 10KE Today
&TOOLS
FLEX Update
Table shows FLEX 10KE device availability.
Table FLEX 10KE Availability
Device
EPF10K30E EPF10K50E EPF10K100E EPF10K100B EPF10K130E EPF10K200E EPF10K250E
Availability
1999 October 1998 1999 1999 1998 Second Half 1999
Altera® MAX+PLUS® version 9.01 software delivers advanced support FLEX® 10KE devices, complete with full pin-out information. Designers design, simulate, their boards today take advantage high-performance, low-power, dual-port capability FLEX 10KE devices. Table lists FLEX 10KE devices supported MAX+PLUS version 9.01 software.
Table FLEX 10KE Devices Supported MAX+PLUS Version 9.01 Software
Device
EPF10K30E
250,000-Gate EPF10K250A Devices Shipping Altera currently shipping industry's highest density device, 250,000-gate EPF10K250A. This device offered 599-pin pin-grid array (PGA) 600-pin ball-grid array (BGA) packages. With 12,160 logic elements (LEs) 40,960 memory bits, this device ideal application-specific integrated circuit (ASIC) prototyping allows system integration single chip. 2.5-V EPF10K100B Device Available EPF10K100B device built 0.25-µm, 5-layermetal process, offering high performance power consumption. EPF10K100B device's 0.25-µm process provides nearly performance advantage power savings over competing 0.35-µm, 3.3-V devices. MultiVoltfeature enables these devices interface with 2.5-V, 3.3-V, 5.0-V devices. EPF10K100B devices 240-pin plastic quad flat pack (PQFP) available today. 256-pin FineLine BGApackage with 17mm2 footprint will available September 1998. Entire 3.3-V FLEX 10KA Family Available With high-performance, low-cost, embedded memory, space-saving package offerings, EPF10K10A device cost-effective solution today's highvolume programmable logic device (PLD) designs. smallest FLEX 10KA device, feature-rich EPF10K10A ideal solution your production design needs. With availability EPF10K250A EPF10K10A devices, 3.3-V FLEX 10KA devices have been introduced.
Package
144-Pin TQFP 208-Pin PQFP 256-Pin FineLine 484-Pin FineLine
EPF10K50E
144-Pin TQFP 208-Pin PQFP 240-Pin PQFP 256-Pin FineLine 484-Pin FineLine
EPF10K100B EPF10K100E
208-Pin PQFP 240-Pin PQFP 208-Pin PQFP 240-Pin PQFP 356-Pin 484-Pin FineLine
EPF10K130E
240-Pin PQFP 484-Pin FineLine 672-Pin FineLine
EPF10K200E
599-Pin 600-Pin 672-Pin FineLine
continued page
Altera Corporation News Views August 1998
Devices Tools Devices Tools, continued from page EPF6010A EPF6016A Devices Available EPC2 Device Available October Altera shipping 3.3-V EPF6010A EPF6016A devices, which deliver high performance prices that competitive with gate arrays. These devices, along with EPF6024A device (already shipping), offered speed grades, including highperformance speed grade. Support these speed grades available MAX+PLUS version 9.01 software. Table shows features offered FLEX 6000 devices.
Table FLEX 6000 Device Features
Feature
Process Supply Voltage Logic Elements Usable Gates User Pins (Maximum)
Configuration EPROM Update
EPF6010A
0.35 5,000 10,000
EPF6016
1,320 8,000 16,000
EPF6016A
0.35 1,320 8,000 16,000
EPF6024A
0.35 1,960
EPC2 device, first reprogrammable Configuration EPROM from Altera, scheduled introduction October 1998. This device, which will offered 20-pin plastic J-lead chip carrier (PLCC) 32-pin thin quad flat pack (TQFP) packages, will pin-compatible with existing Altera Configuration EPROMs same packages. single EPC2 device, which configure FLEX device 130,000 gates, programmed in-system using industry-standard IEEE Std. 1149.1 Joint Test Action Group (JTAG) test ports. EPC2 will operate
Update
9000A Device Availability
12,000 24,000
FLEX 6000 Devices Coming Soon FLEX 6000 devices 100-pin 256-pin FineLine packages planned fourth quarter 1998. These area-efficient packages require less than half board size traditional ball-grid array (BGA) packages. Software support planned MAX+PLUS version software, scheduled release 1998. Table shows FLEX 6000 package availability.
With propagation delays 9000A devices offer customers significant performance enhancements well cost reductions over 9000 devices. Packages EPM9320A EPM9560A devices currently available production quantities. Table summarizes both commercial- industrialtemperature grade 9000A device availability.
Table 9000A Device Availability
Device
EPM9320A EPM9560A
Note
84-Pin PLCC
208-Pin 240-Pin 356-Pin PLCC RQFP
Note: designates commercial designates industrial temperature grade availability.
Table FLEX 6000 Package Availability
Device
EPF6010A EPF6016 EPF6016A EPF6024A
Availability
100-Pin TQFP
100-Pin
144-Pin TQFP
208-Pin PQFP
240-Pin PQFP
256-Pin
256-Pin
Note: FineLine packages will available 1998.
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Devices Tools 7000 9000 Product Transitions Altera moving 7000 9000 devices from 0.65-µm process 0.5-µm process. Table outlines process migration schedule lists reference documentation associated with this migration. download these documents from Customer Notification page Altera site http://www.altera.com.
Table 7000 9000 Migration Schedule Note
Device
EPM7032 EPM7064 EPM7064S EPM7128E EPM7128S EPM7160E EPM7192E EPM7192S EPM7256S EPM7256E EPM9320 EPM9560
Altera In-Circuit Tester Support 7000S family offers complete in-circuit tester support. most efficient customers in-circuit testers in-system programming order fixed programming algorithm devices. These devices denoted with ordering code. example, EPM7128STC100-10 device with in-circuit testers ordering code EPM7128STC100-10F. order devices, contact your local Altera sales representative. 7000AE Devices 7000AE devices will provide speed functionality 7000A devices, plus enhanced in-system programmability (ISP) features. 7000AE devices will offered densities ranging from macrocells with propagation delays fast continuing 7000 family's industry leadership density performance. 7000AE enhanced features summarized Table
Table 7000AE Enhanced Features
Feature
programming algorithm ISP_Done Pull-up resistor pins
Reference
PCN9703 ADV9803 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9803 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9803 PCN9703 ADV9803
Availability
August 1998 October 1998 September 1998 September 1998
Process
0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron
Enhancement
Improves programming factor times. Ensures complete programming. pins pull high while programming in-system.
Notes: transition process will result changes data sheet parameters ordering codes. Advisories process change notices available from Altera's site.
first 7000AE device, EPM7064AE, will available September 1998. Table shows Altera's 7000A devices. EPM7128A EPM7256A, without enhanced feature set, currently available. continued page
Table 7000A Devices
Feature
Macrocells Maximum User Pins Minimum (ns) Packages
EPM7032AE
44-pin PLCC 44-pin TQFP
EPM7064AE
44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP 256-pin September 1998
EPM7128A
84-pin PLCC 100-pin TQFP 100-pin 144-pin TQFP
EPM7256A
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin
EPM7384AE
144-pin TQFP 208-pin PQFP 256-pin
EPM7512AE
144-pin TQFP 208-pin PQFP 256-pin
Projected Availability
1999
1999
November 1998
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Devices Tools Devices Tools, continued from page 7000A Availability 3.3-V 7000A devices, EPM7128A EPM7256A, currently shipping. Each 7000A device supports ISP, MultiVolt pins, propagation delays fast 7000A devices also provide pin-compatibility with industry-standard 7000 devices. Table shows 7000A device availability.
Table 7000A Device Availability
Device
EPM7032AE EPM7064AE
7000S Devices 7000S devices available. These devices offer features such speed grades ISP, IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry devices with more macrocells, open-drain output option. Table shows available packages speed grades.
Table 7000S Device Features
Device
EPM7032S
Package
44-pin PLCC 44-pin TQFP 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10,
Package
44-pin PLCC 44-pin TQFP 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10,
Availability
1999 September 1998 EPM7128S EPM7160S EPM7064S
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP 84-pin PLCC 100-pin TQFP 160-pin PQFP
EPM7128A
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP 256-pin
EPM7256A
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin
EPM7192S EPM7256S
160-pin PQFP 208-pin PQFP
EPM7384AE
144-pin TQFP 208-pin PQFP 256-pin
1999
EPM7512AE
144-pin TQFP 208-pin PQFP 256-pin
November 1998
Discontinued Devices Update
Altera announcements regarding discontinued devices. Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera sales representative. Selected ADVs, PDNs, complete listing discontinued devices also available Altera's site http://www.altera.com. Rochester Electronics, after-market supplier, offers many discontinued Altera products. Contact Rochester Electronics (978) 462-9332 their site http://www.rocelec.com.
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Devices Tools
Tools Update
Features Available MAX+PLUS Version 9.01 Altera shipping MAX+PLUS version 9.01 software. This version provides compilation simulation support Altera FLEX 10KE devices, well enhancements that significantly increase your design productivity, including: Improved place-and-route algorithms that increase average registered design performance Improved quality results Altera VHDL Verilog synthesis that comparable quality results Altera Hardware Description Language (AHDL) synthesis. JamByte Code, compiled representation File (.jbc), which available MAX+PLUS version 9.01, speeds in-system programming times 25%. more information Byte Code, "Introducing Byte Code" page Support FineLine packages. discount. Contact your local Altera sales representative about PLS-PROMO discount. This offer valid through 1998. Version-Controlled Licensing MAX+PLUS Version MAX+PLUS version software (scheduled release October 1998) will feature GLOBEtrotter's FLEXlm, leading license management program. FLEXlm integration allows easy flexible network licensing ensures full Year 2000 compliance MAX+PLUS software. This license management program also changes software licensing structure number ways: Licensing fixed-node, PC-based systems still requires software guards, license file used instead authorization code. When upgrade MAX+PLUS version 9.1, must obtain license file software. minimize inconvenience, Altera will ensure that license sent customers have valid software maintenance agreement before release MAX+PLUS version software. Additionally, after October 1998, MAX+PLUS version users will able generate license file Altera site http://www.altera.com. Starting with MAX+PLUS version software, only customers with valid maintenance agreement will able features each release. Customers without maintenance agreement continue their existing version MAX+PLUS software. license file must generated each time maintenance contract renewed (generally once year).
Network Licensing MAX+PLUS Version 9.01 MAX+PLUS version 9.01 software provides floating-node licenses networks. Customers order this product using PLS-NET/PC ordering code. This product full-featured supports Altera device families. Floating-node licenses platforms implemented UNIX- (Solaris 2.5+, HP-UX 10.20+, 4.1+) Windows NT-based license servers. license will based either UNIX server HOST Network Interface Card (NIC) Windows servers. limited time, customers with fixed-node versions MAX+PLUS active maintenance purchase floating-node design sites significant
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Technical
ARTICLES
FLEX 10KE Provides Advanced Features
Dual-Port Mode FLEX 10KE enhanced adds dual-port capability existing structure. dual-port structure ideal first-in first-out (FIFO) buffers with clocks. FLEX 10KE dual-port single-port mode. When dual-port mode, separate clocks used read write sections, which allows written read different rates. also separate synchronous clock enable signals read write sections, which allows independent control these sections. Figure page Single-Port Mode FLEX 10KE also used single-port mode. This mode also used backward compatibility with FLEX designs. example FLEX 10KE device single-port mode, Figure page Synchronous EABs used implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable (WE) signal, while ensuring that data address signals meet setup hold time specifications relative signal. contrast, EAB's synchronous generates signal self-timed with respect input write clock. circuit using EAB's self-timed must only meet setup hold time specifications global clock. When used RAM, each configured following sizes: 1,024 2,048 Larger blocks created combining multiple EABs. example, blocks combined form block; blocks combined form block. Figure page
Altera® FLEX® 10KE devices contain advanced systemlevel features, including enhanced embedded array blocks (EABs), that increase performance resource utilization. FLEX 10KE flexible block with registers input output ports. also suitable functions such multipliers, vector scalars, error correction circuits when programmed with read-only pattern. These functions combined applications such digital filters microcontrollers. Logic functions implemented programming with read-only pattern during configuration, thereby creating large look-up table (LUT). With LUTs, combinatorial functions implemented looking results, rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times EABs. large capacity EABs enables designers implement complex functions logic level without routing delays associated with linked logic elements (LEs) field-programmable gate array (FPGA) blocks. example, single implement multiplier with nine inputs nine outputs. Parameterized functions such library parameterized module (LPM) functions take advantage automatically. FLEX 10KE provides advantages over FPGAs, which implement on-board arrays small, distributed blocks. These small FPGA blocks must connected together make usablesized blocks. blocks connected together using multiplexers implemented with more logic blocks. These extra multiplexers cause extra delays, which slow down block. FPGA blocks also prone routing problems because small blocks must connected together make larger blocks. contrast, EABs used implement large, dedicated blocks that eliminate these timing routing concerns.
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Technical Articles
Figure FLEX 10KE Device Dual-Port Mode
Dedicated Inputs Global Signals Dedicated Clocks
Notes (1),
Interconnect
data
RAM/ROM Data 1,024 2,048
Data
rdaddress
Read Address
Local Interconnect, Note wraddress
Write Address
rden
Read Enable
wren outclocken
Write Enable
inclocken
inclock outclock
Write Pulse Generator
Multiplexers allow read address read enable registers clocked inclock outclock signals.
Column Interconnect
Notes: registers asynchronously cleared local interconnect signals, global signals, chip-wide reset. EPF10K30E EPF10K50E devices have local interconnect channels. EPF10K100E, EPF10K130E, EPF10K200E, EPF10K250E devices have local interconnect channels. EPF10K100B device does offer dual-port mode.
necessary, EABs device cascaded form single block. EABs cascaded form blocks 2,048 words without impacting timing. Altera's MAX+PLUS® software automatically combines EABs meet designer's specifications. EABs provide flexible options driving controlling clock signals. Different clocks clock enables used reading writing EAB. Registers independently inserted data input, output, write address, signals, read address, read enable (RE) signals. global signals local interconnect drive clock enable signals. global signals,
dedicated clock pins, local interconnect drive clock signals. Because drive local interconnect, control clear, clock, clock enable signals. interconnect drive column interconnects. Each output drive channels column channels; unused channel driven other LEs. This feature increases routing resources available outputs. column interconnect, which adjacent EAB, twice many channels other columns device. Figures page continued page
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Technical Articles FLEX 10KE Provides Advanced Features, continued from page
Figure FLEX 10KE Device Single-Port Mode
Dedicated Inputs Global Signals Chip-Wide Reset
Interconnect
RAM/ROM Data 1,024 2,048
Data
Local Interconnect, Note
Address
Write Enable
Column Interconnect
Notes: EPF10K30E EPF10K50E devices have local interconnect channels. EPF10K100E, EPF10K100B, EPF10K130E, EPF10K200E, EPF10K250E devices have local interconnect channels.
more information FLEX 10KE devices, refer FLEX 10KE Embedded Programmable Logic Family Data Sheet, contact Altera Applications.
Figure Examples Combining EABs
Design Tips from Altera Applications series will resume next quarter.
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Technical Articles
Guidelines Using
time-to-market pressures increase, design engineers devices JTAG chain must same state. require advanced system-level products ensure Therefore, systems with multiple power supply problem-free development manufacturing. voltages, JTAG circuitry must held testProgrammable logic devices (PLDs) with in-system logic-reset state until devices chain programmability (ISP) help accelerate completely powered This procedure particularly development time, simplify manufacturing flow, important because systems with multiple power supreduce inventory costs, improve printed circuit plies cannot power voltage levels simultaneously. board (PCB) testing capabilities. Altera® MAX® 9000 (including 9000A), 7000S, 7000A Altera devices with MultiVoltfeature devices programmed reprogrammed using power supply voltages (VCCINT VCCIO). VCCINT IEEE Std. 1149.1 Joint Test Action Group provides power JTAG circuitry; VCCIO provides (JTAG) interface. This interface allows devices power output drivers pins, including TDO. programmed functionally tested Therefore, when these devices power supply single manufacturing step, saving testing time voltages, JTAG circuitry must held testassembly costs. This article describes some logic-reset state until both power supplies turned guidelines should follow when using ISP. easiest ensure this pull high. Device Operating Conditions Using Non-"F" Devices Each Altera device several parametric ratings, operating conditions, that required proper devices either fixed-algorithm ("F"), operation. Even these conditions violated user require branching algorithms (non-"F"). Most in-circuit mode, device usually operates correctly. However, tester file formats (e.g., Serial Vector Format Files (.svf), these conditions should exceeded during Hewlett-Packard Pattern Capture Format Files (.pcf), in-system programming. Violating operating DTS, ASC) "fixed" deterministic, which conditions during in-system programming result means they only support fixed algorithm programming failures incorrectly programmed without branching. MAX+PLUS software devices. appropriate family data sheet version higher generates files 1998 Data Book specifications. devices. Because algorithms files constant, always these files program future devices. Signal Most in-system programming failures caused noisy signal. Noisy transitions rising falling edges cause incorrect clocking IEEE Std. 1149.1 Test Access Port (TAP) controller. Incorrect clocking cause state machine transition unknown state, leading in-system programming failures. Further, because signal must drive IEEE Std. 1149.1 devices chain parallel, signal will have high fan-out. Like other highfan-out user-mode clock, must manage clock tree maintain signal integrity. Typical errors that result from clock integrity problems invalid messages, blank-check errors, verification errors. MultiVolt Devices JTAG circuitry operate correctly during insystem programming boundary-scan testing, Altera does recommend programming non-"F" devices most in-circuit testers. Some testers support JamProgramming Test Language program non-"F" devices. Non-"F" devices require branching based three variables read from device: programming pulse time, erase pulse time, manufacturer silicon These three variables programmed into Altera non-"F" devices. Using only devices eliminates potential problems these variables change. Conclusion information provided this article based development experiences customer issues resolved Altera. Refer Application Note (In-System Programmability Guidelines) complete details. more information resolving in-system programming problems, contact Support Program ISPembed@altera.com ISPATE@altera.com.
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Technical Articles
Implementing FIFO Solutions Altera Devices with FIFO MegaWizard Plug-In
Altera offers first-in first-out (FIFO) buffer solutions with MegaWizardPlug-In FIFO buffers. This feature provides fast, flexible, easy-toimplement FIFO solutions automatically selecting appropriate megafunction based upon FIFO design requirements. This feature available beginning with MAX+PLUS® version 9.01 software. FIFO MegaWizard solution implements megafunctions, single-clock FIFO (scfifo) double-clock FIFO (dcfifo). SCFIFO used synchronous FIFO designs implemented FLEX device family embedded array blocks (EABs), including FLEX 10KE dual-port RAM. dcfifo implemented asynchronous FIFO designs (designs requiring separate read write clocks) FLEX 10KE dual-port EAB. Both FIFOs implemented logic element- (LE) based FIFOs FLEX devices. With FIFO MegaWizard plug-in, FIFO width depth dimensions, output control signals, read access easily chosen modified wide range FIFO solutions. Synchronous FIFO Designs Using FIFO MegaWizard plug-in, synchronous FIFO designs implemented selecting option assign common clock both reading writing FIFO function. Simultaneous reads writes possible with synchronous FIFO function. Figure shows MegaWizard Plug-In Manager with option synchronous FIFO design selected. with synchronous FIFO function, asynchronous FIFO function takes full advantage FLEX 10KE device's dual-port architecture. more information MegaWizard Plug-In Manager, FLEX 10KE dual-port EAB, scfifo dcfifo functions, contact Altera Applications (800) 800-EPLD consult MAX+PLUS Help (version 9.01 higher). more information about FIFO solutions FLEX devices, refer Altera's 1998 News Views Altera site, contact Altera Applications. synchronous FIFO function ideal implementation FLEX 10KE devices, taking full advantage EABs' dual-port architecture, 16-bit width, 4,096-bit memory EAB. With FLEX 10K, FLEX 10KA, EPF10K100B devices, MegaWizard plug-in-generated megafunction efficiently implemented EABs interleaved FIFO function, allowing simultaneous reads writes performed. Asynchronous FIFO Designs With MegaWizard feature, asynchronous FIFO designs implemented selecting option assign separate clocks reading writing FIFO function. Figure shows MegaWizard PlugIn Manager with option asynchronous FIFO design selected.
Figure Selecting Asynchronous FIFO
Figure Selecting Synchronous FIFO
Altera Corporation
News Views
August 1998
Contributed
Dave Bonnett Product Marketing Manager ASSET InterTech, Inc.
several years, equipment manufacturers have heard about in-system programmability (ISP) exciting effective help meet increasingly difficult cost time-to-market requirements their industries. emergence programming methodology choice programmable logic devices (PLDs) been accidental. industry expended significant effort provide both devices tools support ISP. Now, facto adoption boundary-scan (IEEE Std. 1149.1) Test Access Port (TAP) serial interface combines companies that experts devices capable with companies that experts boundary-scan tests (BSTs). With ASSET suite tools, promises realized today. ASSET's Leadership ASSET long been active leader standardization process ISP. addition helping Altera with efforts standardize JamProgramming Test Language through JEDEC, ASSET been responsible maintaining serial vector format (SVF) specification. Many staff ASSET worked development standard format that would allow vectors transferred among different systems. ASSET enhanced adding instructions capabilities that allow used effectively process. Valuable ASSET ASSET® product family, which runs platforms, allows users quickly easily test perform in-system programming during phase product's life, including design, manufacturing, infield maintenance. ASSET's capabilities available different products. ScanProgrammer
ASSET InterTech Provides Low-Cost Test Support
interactive programming product that used during design verification. ISPExtender brings full power ASSET's existing manufacturing test solutions. While ASSET system been used some time perform with files, ScanProgrammer automates simplifies process. ScanProgrammer adds ability language ASSET's existing support using SVF. ScanProgrammer used program devices during manufacturing/assembly test process. ScanProgrammer also load programmable devices during burn-in testing. addition, used later system's life cycle load updated software into PLDs after system been shipped installed field. ISPExtender adds support language ASSET's ScanDriverTM, allowing files used either stand-alone programming station that integrated into manufacturing flow. ScanDriver/ISPExtender controlled from manufacturing test user interface that will seamlessly into manufacturing process. Future Although need gained significant momentum recent years, increased new, more delicate finer-pitch packages like ball-grid array packages, chip scale packages, others will certainly accelerate years ahead. tools-like ASSET-used reduce programming costs system's time-to-market, available today designers seeking competitive advantage.
Contact Information: ASSET InterTech, Inc. 2201 Central Expressway Suite Richardson, 75080 http://www.asset-intertech.com
Altera Corporation
News Views
August 1998
Questions
&ANSWERS
configure EPF6016A device with EPF6016 configuration file?
What extra balls that part ball grid some ball-grid array (BGA) packages, will they affect reflow process? extra solder balls provide ground plane that connected package. extra balls called high-temperature balls because they have different tin/lead (Sn/Pb) composition than regular solder balls melt higher temperature. These high-temperature balls have 90/10 ratio Sn/Pb melt 240° 245° Device leads have 63/37 ratio Sn/Pb. maximum temperature package reach before damages solder device 220° Therefore, high-temperature balls will disturb reflow process because they melt temperature well above maximum package temperature. hightemperature balls melt, indication that reflow temperature high.
EPF6016A EPF6016 devices configuration file-compatible; cannot configure EPF6016A device with EPF6016 configuration file, vice versa. migrate EPF6016 design EPF6016A device, change device assignment EPF6016A device recompile Using Smart Recompile command (Processing menu) will allow MAX+PLUS Compiler skip over Logic Synthesizer Fitter, speeding recompilation. After recompilation, Altera recommends re-running timing analysis simulation verify correct design operation with faster EPF6016A device.
does FLEX® 8000 device fail during incircuit reconfiguration (ICR) when using Active Serial (AS) configuration mode? require stabilization DCLK. Prior start configuration, FLEX 8000 devices mode tri-state DCLK, which becomes active after nSTATUS released FLEX 8000 device pulled high VCC. DCLK tri-stated floating period time between nSTATUS being released DCLK starting toggle. nSTATUS connected count enable serial Configuration EPROM device, EPROM counter enabled pulling nSTATUS high Then, configuration EPROM ready send data rising edges DCLK input seen. floating DCLK potentially send erroneous rising edges configuration EPROM, thereby clocking EPROM counter before FLEX 8000 device ready accept data correctly. This situation cause configuration fail. solution 2.2-K pull-down resistor DCLK. While DCLK tri-stated start ICR, pull-down resistor prevents EPROM device from recognizing spurious rising edges clock input until FLEX 8000 device actively toggles DCLK. more details FLEX 8000 device configuration, refer following documents: Application Note (Configuring FLEX 8000 Devices) Application Note (Configuring Multiple FLEX 8000 Devices)
combine multiple Timing Analyzer outputs into file when running MAX+PLUS® software from command line? either type command (from command prompt) command (from UNIX prompt) combine multiple Timing Analyzer Output Files (.tao) into single file. example: DOS: type <filename>.tao <result name>.txt UNIX: <filename>.tao <result name>.txt also these commands batch script file. sample batch file shown below: maxplus2 chiptrip -ta_reg chiptrip type chiptrip.tao results.txt example above compiles project chiptrip creates chiptrip.tao file registered performance. batch file then adds file information file named results.txt. This process repeated different compilations timing analyses save file information same results.txt file.
Altera Corporation
News Views
August 1998
Questions Answers
What minimum time that clear signal must held active FLEX device make sure that reset actually performed? ensure that reset performed, must hold clear signal active length time that least long delay from input clear port flipflop. find delay using Timing Analyzer (Delay Matrix) MAX+PLUS software. Select input which clear signal assigned timing analysis source clear port flipflop timing analysis destination.
MAX® 7000, 7000E, 7000S, 7000A device Programmer Object Files (.pof) compatible? Typically, program newer device type with older programming file, vice versa. following programming files compatible: program 7000E device with 7000 POF. program 7000S device with 7000E 7000 POF. 7000S device features superset 7000E device features. Therefore, program 7000S device with 7000E POF, MAX+PLUS software will automatically disable superset features 7000S device. This programming (often called crossprogramming) supported MAX+PLUS software, well third-party programmers such programmers from Data (http://www.data-io.com) Microsystems (http://www.bpmicro.com). program 7000A device with 7000, 7000E, 7000S POF.
Does MAX+PLUS software show effect using 3.3-V VCCIO with FLEX 10KE device (including EPF10K100B)? MAX+PLUS software shows effect using MultiVoltI/O devices that support this feature. 5.0-V 3.3-V devices, using MultiVolt will slow output performance slightly, because VCCIO level lowered. However, 2.5-V FLEX 10KE devices, VCCIO driven When driving CCIO output performance faster than when VCCIO model effect MultiVolt device that supports this feature, turn MultiVolt option Global Project Device Options dialog (Assign menu).
toggle while configuring more FLEX devices Passive Parallel Asynchronous (PPA) Passive Serial Asynchronous (PSA) modes? toggle during configuration your design meets specifications listed table below.
Table FLEX Device Family
Parameter
tCSSU
Where find information MAX+PLUS software with third-party
tools? information using MAX+PLUS software with other tools, MAX+PLUS ACCESSSM Guidelines Altera's site MAX+PLUS Software CD-ROM version higher. However, should always refer most up-to-date information. These guidelines replace software interface guides that were available MAX+PLUS version earlier. version 9.01, these guidelines should automatically installed together with MAX+PLUS software.
Definition
Chip select setup time before rising edge (minimum) pulse width (minimum) Chip select hold time after rising edge (minimum)
FLEX 6000 FLEX 8000
FLEX
tWSP
tCSH
Notes: This specification applies EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50, FLEX 10KA FLEX 10KE devices. This specification applies EPF10K70 EPF10K100 devices only.
Altera Corporation
News Views
August 1998
Altera
VIEWPOINT
Next-Generation Tool Requirements
multi-million-gate function availability will part programmable logic design fast multi-million-gate design methodology. approaching. ready? Altera already stage designing Design Collaboration Raphaeldevices, latest Altera® programmable logic device (PLD) family With today's rapid development cycles, that will offer single-chip densities unlikely that single individual will measured millions gates. undertake designs this size. Multiramifications devices this size person design teams must assigned substantial: designers must modify their single PLD, much like applicationRobert Beachler methodology create designs specific integrated circuits (ASICs) Director, Development designed today. successfully. Tools Marketing Additionally, support large programmable design teams, logic designers will need next-generation tools will techniques meet demand require workgroup-computing shrinking development capability, complete with cycles. This article describes heterogeneous network some ways design support design process must change modification tracking. accommodate multi-milliongate devices. Advanced Software Megafunctions: Pre-Tested Functional Blocks multi-million-gate design, megafunctions will increase dramatically. other single factor improve designer productivity much using megafunctions. Altera pioneered megafunctions programmable logic, developed technology innovations that will accelerate multi-million-gate design. Altera only company offer OpenCorecapability, allowing engineers "test drive" encrypted functions from Altera Altera Megafunction Partners Program (AMPPSM) partnership. MegaWizardPlug-Ins provide powerful parameterization capability ease integration megafunctions into diverse design requirements. Improvement these capabilities increasing support multi-million-gate designs, industrialstrength databases will required support Mbytes data needed represent design. design size grows, design iteration time must kept minimum. Exciting technologies will allow engineers make small design changes results minutes. Without such advanced software, design compiled from scratch would take hours. Today, engineer order receive dualprocessor Pentium II-based less than days, very software applications written take advantage this tremendous computing power. Next-generation software will maximize potential two- fourprocessor machines. Loadsharing facilities will take advantage under-used CPUs across network, helping keep compilation times low.
Altera Corporation
News Views
August 1998
Altera Viewpoint Tool Integration There thriving business third-party development tools programmable logic. next-generation development tools, integration with these thirdparty tools will grow even closer. Users will hardpressed tell where tool ends, next begins. Internet Support When MAX+PLUS® software designed early 1990s, Internet widespread popular today. Looking forward, clear that Internet will become critical component support infrastructure system designers. Using Internet full advantage will allow engineers stay abreast latest software releases, device information, solutions toughest design problems. Right Around Corner multi-million-gate design almost upon tools, embracing latest advances computing hardware software technology, will necessary realize full potential latest silicon. prepared exciting chapter programmable logic design.
Customer Training Brings Speed
Altera's Customer Training Department revised expanded course offerings. Classes created specifically meet different experience levels, provide realistic design examples labs, offer sound advice hardware design techniques software settings. These one-day sessions give knowledge that might otherwise require months trial error work. Introductory courses ideal designers beginning Altera devices. These courses introduce architecture features Altera device families, well access these features analyze design results with MAX+PLUS® software. Discussions include basic recommendations design layout software settings. experienced Altera users interested gaining higher speed utilization, advanced courses focus fitting performance specific architectures. These classes contain more labs than introductory courses. advanced courses faster paced, more challenging, require knowledge MAX+PLUS software well basic understanding Altera device family architectures. Altera also offers VHDL AHDL courses designers experience level. These classes cover basic syntax design structure, inferring instantiating elements, creating overall design with languages. Instructors emphasize common problems coding, particularly VHDL course. list available courses shown below. also find more detailed information registration form Altera world-wide site http://www.altera.com. Introduction Altera's Device Families Introduction Altera's FLEX Device Families Advanced Design Techniques Altera's Device Families Advanced Design Techniques Altera's FLEX Device Families Designing with MAX+PLUS Designing with MAX+PLUS Using AHDL Designing with MAX+PLUS Using VHDL
Altera Corporation
News Views
August 1998
Technical Articles
Introducing Byte Code
Jamprogramming test language, softwarelevel standard in-system programmability (ISP), provides solution problems that have plagued insystem programming, such ease use, fast programming times, small file sizes. address issues that have arisen since first implementation-file sizes large DOS-based programming embedded processors with little cache-Altera developed Byte Code. Byte Code binary-based programming file format that produces smaller file sizes faster programming times than original ASCII-based File. Byte Code accomplishes these improvements through reduced overhead parsing added compression algorithms available MAX+PLUS version 9.01 (complete online documentation will available version 9.1). Byte Code Files Byte Code binary file format analogous existing ASCII format. Like ASCII files, Byte Code files comply with Programming Test Language Specification defined variables. Byte Code also vendor- platformindependent, programs devices IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. Byte Code files consist software components: Byte Code Compiler Byte Code Interpreter. Byte Code Compiler writes Byte Code File (.jbc) required program design into specified device. Byte Code Interpreter interprets File programs target device. Together, these elements create universal language tool that addresses programmable logic devices (PLDs) programming methodologies. Byte Code Compiler Byte Code Compiler version uses literal compressed data. Literal JBCs produce faster programming times slightly larger than original ASCII File (.jam). Table Compressed Files smaller than original Files. Version compiler will allow designers choose between data compression small file sizes literal data programming speed. Starting with version 9.01, MAX+PLUS® software will generate Files directly. Designers will simply specify File using Generate File command (File menu) MAX+PLUS Program20
Table Programming Times
Device File Format, Note ASCII (Seconds)
EPM7064S EPM7128S EPM7256S EPM9320 EPM9560
Improvement
Byte Code (Seconds)
Note: Programming times were gathered using Pentium processor with download cable 32-bit Byte Code Interpreter.
Compiler. version 9.01, designers will also Byte Code Compiler convert existing ASCII Files into File format. Further, because Byte Code Compiler fully architectureindependent, convert vendor's File into format. Byte Code Interpreter JBCs applied ISP-capable devices through Byte Code Interpreter (JBI). similar ASCII Interpreter, using identical interface routines porting steps. only difference that roughly smaller than ASCII interpreter. source code available site http://www.jamisp.com. Figure page shows block diagram Files applied ISP-capable devices. existing projects, designers must apply ASCII files ISP-capable devices through ASCII Interpreter. Table describes which Interpreter with each file format. Compatibility Altera recommends using Byte Code projects because generates smaller file sizes
Table Player Support
File Format
ASCII Player version
Byte Code Player version
continued page
Altera Corporation News Views August 1998
Altera
SameFrame Pin-outs FineLine Packaging
SameFramepin-outs refer unique arrangement solder balls 1.0-mm pitch FineLine BGApackaging recently introduced Altera. With SameFrame pin-outs, balls arranged that FineLine packages with lower ball counts form subset packages with higher ball counts. SameFrame pin-out feature offers unique level flexibility, allowing designers same printed circuit board (PCB) layout packages with varying counts devices with different densities. With SameFrame pin-outs, Altera enhanced concept device migration, taking from vertical diagonal migration. Vertical migration enables designers same layout with devices different densities within common package. SameFrame pin-out diagonal migration capability means that same board layout accommodate changes both device density package size, bringing designers flexibility, cost savings, faster time-to-market. Matching Pin-outs Figure shows example SameFrame pin-out 100-pin 256-pin FineLine packages. this simplified example, common power ground pins located center packaging that they compatible both smaller 100-pin package larger 256-pin package. ring common configuration pins surrounds common power ground pins, making these pins compatible both packages. additional power ground pins larger 256-pin package located four corners package, additional configuration pins located four outer edges. this way, designers place 100-pin package precisely same location larger 256-pin package, sure that pin-outs match. SameFrame Pin-out Device Support SameFrame pin-out feature supported FLEX® 10KA, FLEX 10KE, FLEX 6000A, MAX® 7000A devices, shown Table
Table SameFrame Pin-Out Device Support Note
Device 100-Pin FineLine 256-Pin FineLine
484-Pin FineLine
672-Pin FineLine
EPF10K10A EPF10K30A EPF10K50V EPF10K30E EPF10K50E EPF10K100A EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K250E EPF6010A EPF6016A EPF6024A EPM7064A EPM7128A EPM7256A EPM7384A EPM7512A
Figure 100-Pin 256-Pin Pin-Out Example
Power Ground Pins (256-Pin Package) Configuration Pins (256-Pin Packages) Common Configuration Pins (100-Pin 256-Pin Packages) Common Power Ground Pins (All FineLine Packages)
Note: Devices shown same color support SameFrame pinout migration capability.
continued page
Altera Corporation News Views August 1998
Altera News Designing SameFrame Pin-outs take advantage SameFrame pin-outs capability Altera devices, designers should follow basic steps: When creating your design, estimate maximum count that needed your current design future design revisions. package that fits this maximum count first, that packages with smaller ball count become potential drop-in replacements. MAX+PLUS® version software simplifies task using only available pins. Designers select which devices they future migration MAX+PLUS software compiles design using only pins that common different packages. Thus, following simple steps, SameFrame pin-outs assure easy migration between devices. Altera Pin-out Advantage SameFrame pin-outs, combined with FineLine packaging, dimension flexibility Altera's cutting-edge devices. SameFrame pin-out feature offers unprecedented design migration across densities counts. Previously, vertical migration enabled designers change density device they wished still keep same printed circuit board, only they maintained same package pin-out. Now, with diagonal migration capability SameFrame pin-outs, device density package size change without creating need board layout. Because layout completed before final selection device, product brought market shorter time. Costs moving from higher lower density device from higher lower pin-count package. Altera's SameFrame pin-outs offer flexibility, fast time-to-market, cost savings. more information SameFrame pin-outs, contact Altera Applications (800) 800-EPLD your local sales representative. details FineLine packaging, "Next-Generation Packaging" 1998 issue News Views Altera's site.
Figure illustrates board design 256-pin FineLine package that accommodate either 100-pin 256-pin package.
Figure SameFrame Pin-out Flexibility
Printed circuit board (Designed 256-Pin package)
100-Pin FineLine
256-Pin FineLine
100-Pin package (Reduced count logic requirements)
256-Pin package (Increased count logic requirements)
When designing SameFrame pin-outs, should also consider variance count between your current target design. Your board design should avoid using pins that will available device package that might used future. Introducing Byte Code Jam, continued from page faster programming times. However, Altera will continue support ASCII that designers program existing projects into ISP-capable devices. more information Byte Code programming test language, refer Application Note (Using Language Embedded
Processor) Programming Test Language Specification.
Figure File Path
MAX+PLUS .jbc Byte Code Interpreter JTAG Chain
Altera Corporation
News Views
August 1998
Altera News
ACAP: Outsourcing Design Development
When Splash Technology, Inc. Torrance, wanted increase their development capacity supplement their peripheral component interconnect (PCI) business, they decided look outside company help. design, involving Altera® EPF10K30 programmable logic devices (PLDs), already been completed. However, scheduling constraints, internal Splash resources were available work simulation portion. After viewing Altera Consultants Alliance Program (ACAPSM) listing Altera's site, Splash Technology found expertise they needed System Design Group (SDG) Diego, several ACAP consultants have been successful leveraging their expertise meet design requirements Altera customers. short life span nine months, ACAP program been able provide customers with resource accelerate their design cycle times increase time-tomarket productivity. Motorola, Hughes Network Systems, Ericsson, Hewlett Packard among Altera customers that have used expertise design engineering services ACAP consultants. Today's increasing densities encourage more complex designs, complex designs usually require more expertise design time. device densities system speeds increase, designs become more complex. same time, competitive time-to-market pressures require faster design cycles. ACAP provides viable solution customers outsource their designs offer alternative product development path. Before Altera certifies recommends ACAP consultants, they receive advanced training Altera device architec-tures software, equipped with state-of-the-art design tools. Certified ACAP consultants currently working North America, Europe, Asia. qualifications ACAP consultants their areas expertise available Altera world-wide site http://www.altera.com. Below list current ACAP consultants: Western U.S. Advanced Logical Design, Inc., Saratoga, Bright Design Services, Seattle, Great River Technology, Inc., Albuquerque, Engineering, Inc., Santa Clara,
News Views August 1998
Innovative Configuration, Inc., Aptos, Northwest Logic Design, Beaverton, Norton Engineering Consultants, Oakland, Systems, Jose, Seitz Associates, Inc., Beaverton, Software Systems Engineering, Inc., Tucson, System Design Group, Diego, Wipro Limited, Santa Clara,
Central U.S. ASIC Designs, Inc., Naperville, Design Analysis Associates, Inc., Logan, Enterprises, Inc., Richardson, Eberwein Associates, Inc., Houston,
Eastern U.S. Canada Applied Microelectronics, Inc., Halifax, Nova Scotia, Canada Bolton Engineering, Inc., Melrose, Courtenay Johnson, Ontario, Canada Manufacturing, Inc., Pennsauken, Mettrix Technology Corporation, Hopewell Junction, Moore Labs, Hudson, Nova Electronic Design Analysis, Corp., Ashburn, Plandscapes, Inc., Stow, Princeton Technology Group, East Windsor, Lowenstein Associates, Vienna, Szabo Electronic Systems, Watertown,
Europe Asia Gid'el Ltd., Israel Wipro Limited, India BARCO SILEX, Louvain-la-Neuve, Belgium Frontec ASIC Design Center, Solna, Sweden IC-Technologie, Wertheim, Germany Locke's Digital Developments Ltd., Dorsett, England ProDrive B.V., Eindhoven, Netherlands
inquire comment about ACAP program, please send email acap-info@altera.com. find more about becoming ACAP member, please send email acap@altera.com.
Altera Corporation
Altera News
Achieving Cost Efficiency
Altera's provide customers with programmable logic devices (PLDs) that offer best performance, highest density, lowest price. satisfy today's design requirements, devices must offer advanced feature set, backed efficient design tools, widely available intellectual property, reliable customer support service. Nonetheless, component price remains factor device selection. FLEX Architecture Maximizes Performance Minimizes Costs offer lowest prices, Altera strives reduce manufacturing costs. size yield factors that directly affect these costs. Because wafer prices fixed, increasing number dice wafer lowers cost die. Reducing size, however, enough. increase number dice wafer only cost-effective these dice usable. small size must combined with high yield maximum cost reduction. With innovative FLEX architecture, Altera able increase density improve performance while minimizing size maximizing yield.
Figure FLEX Redundancy Allows Impurities Bypassed
Element (IOE)
Reducing Size features FLEX architecture crucial reducing size increasing yield. continuous hierarchical routing structure. This structure, which consists device-wide metal lines, offers fast, predictable performance fast compilation times. also "metal friendly" structure that stacked take advantage extra metal process layers. When 0.5-mm, 3-layer-metal process FLEX devices were migrated FLEX 10KA devices manufactured 0.35-mm, 4-layer-metal process, size reduced significantly, merely because horizontal "shrink", also because added layer metal. Increasing Yield feature FLEX device architecture that dramatically increases yield redundancy. Redundant circuits, commonly employed memory devices, provided FLEX devices that, when impurity found die, defective area bypassed redundant circuit used place. Figure shows affected transformed into
Element (IOE)
Interconnect
Column Interconnect
Interconnect
Column Interconnect
Column with Impurities
Isolated Area
Redundant Capacity
Connected Capacity
Altera Corporation
News Views
August 1998
Altera News good die. redundant circuitry only brought into use, however, because continuous interconnect structure FLEX architecture. Together, these features maximize yield. Conclusion cost semiconductor dependent number dice wafer yield. combining continuous interconnect structure with Altera continues push down prices programmable logic devices allow customers programmable logic production. redundancy decrease size increase yield, Altera been able reduce device costs dramatically. These other engineering innovations ensure that Altera's customers enjoy optimal performance lowest prices.
Altera 1998
crowds around Altera® booth recent Design Automation Conference (DAC) Francisco showed growing popularity Altera's solution programmable logic designs. Altera solution focuses improving productivity reducing product development cycles. Over 1,200 engineers managers viewed Altera's presentation participated software hardware demonstrations. soccer balls used promotional giveaways proved quite popular throughout conference. Altera booth offered numerous demonstrations using Altera devices tools from Altera's electronic design automation (EDA) partners. Design engineers operated MegaWizardPlug-Ins that provide user customization megafunctions. Also featured first public demonstration Jamlanguage programming devices from Altera, Cypress, Lattice, Vantis, Xilinx single board. Altera also distributed latest AMPP Catalog, which summarizes current Altera Megafunction Partners Program (AMPPSM) functions provides corporate profile each AMPP partner. copy AMPP Catalog, contact Altera Literature Services; up-to-date AMPP information also available Altera world-wide site http://www.altera.com.
1998 ICSPAT/DSP World
International Conference Signal Processing Applications Technology will held September 1998, Toronto Convention Center, Toronto, Canada. sure stop visit Altera booth #807 details latest digital signal processing (DSP) developments Altera. Altera® representatives will distributing papers will provide three-hour product demonstration September 13th, highlighting Reed-Solomon, Viterbi decoder, filter solutions.
Altera Corporation
News Views
August 1998
Every
Third-Party Programming Support
Data Microsystems provide programming hardware support Altera devices. Algorithms available from either Data I/O's Keep Current ExpressBulletin Board Service (KCE-BBS) Microsystems' with MAX+PLUS® software releases. Programming support Configuration EPROM, MAX® 9000, 7000 devices shown table below. information subject change.
Third-Party Programming Hardware Support
Device
EPC1064 EPC1213 EPC1 EPC1441 EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7128A EPM7160E EPM7192E EPM7192S EPM7256E EPM7256S EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
Altera Publications
publications available from Altera Literature Services. Individual documents available Altera world-wide site http://www.altera.com. Document part numbers shown parentheses. Altera Digital Library CD-ROM, version (P-CD-ADL-04) Master/Target MegaCore Function with Data Sheet (A-DS-PCI1-02) pci_b Master/Target MegaCore Function Data Sheet (A-DS-PCIB-01) pcit1 Target MegaCore Function Data Sheet (A-DS-PCIT1-01.01) FLEX 10KE Embedded Programmable Logic Family Data Sheet (A-DS-F10KE-01) Performance Measurements Typical Applications (A-AN-096-01) Comparing Performance High-Density PLDs (A-AN-097-01) Comparing Performance Common Megafunctions (A-AN-098-01) Comparing Performance Dual-Port Memory Functions (A-AN-099-01) 100: In-System Programmability Guidelines (A-AN-100-01) 64-Bit Target Megafunction (A-SB-037-01) Passing Hierarchical Timing Constraints from Synopsys Tools MAX+PLUS Version (M-TB-048-01)
Data
Microsystems
Notes: These devices supported Data 3900 version UniSite version programmers. These devices supported Microsystems programmers version 3.34.
Current Software Version
latest version Altera® software shown below: MAX+PLUS version 9.01 (PC, SPARCstation, 9000 Series 700/800, RISC System/6000 platforms)
Altera Corporation
News Views
August 1998
Every Issue
Programming Hardware Support
following tables contain latest programming hardware information Altera devices. correct programming, software version shown "Current Software Version" previous page. Table
Table Altera Programming Adapters (Part
Device
EPC1441 EPC1 (3), EPC1213, EPM9320
Table Altera Programming Adapters(Part
Device
EPM7128S
Note
Package
J-lead (84-pin) PQFP (100-pin)
Adapter
PLMJ7000-84 PLMQ7000-100NC
TQFP (100-pin) PLMT7000-100NC PQFP (160-pin) PLMQ7128/160-160NC EPM7160E J-lead (84-pin) PQFP (100-pin) PQFP (160-pin) PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMQ7128/7160-160NC
Note
EPM7160S
Package
TQFP J-lead J-lead (84-pin) (280-pin)
Adapter
PLMJ1213 PLMT1064 PLMJ1213 PLMJ1213 PLMJ9320-84
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPC1064 (2), EPC1064V DIP, J-lead
EPM7192E (160-pin) PQFP (160-pin) PLMG7192-160 PLMQ7192/7256-160
RQFP (208-pin) PLMR9000-208 PLMG9000-280 PLMJ9320-84
EPM7192S EPM7256E
PQFP (160-pin) PLMQ7192/256-160NC PQFP (160-pin) PLMQ7192/7256-160 (192-pin) PLMG7256-192 PQFP (208-pin) PLMR7256-208 RQFP (208-pin) PLMR7256-208 PLMR7256-208NC
EPM9320A
J-lead (84-pin)
RQFP (208-pin) PLMR9000-208NC EPM9400 J-lead (84-pin) PLMJ9400-84 EPM7256A EPM7256S EPM7384AE RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240 EPM9480 RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240 EPM9560 RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240 (280-pin) PLMG9000-280 RQFP (304-pin) PLMR9000-304 EPM9560A RQFP (208-pin) PLMR9000-208NC RQFP (240-pin) PLMR9000-240NC EPM7032, EPM7032V J-lead (44-pin) PQFP (44-pin) TQFP (44-pin) EPM7032S, EPM7032AE J-lead (44-pin) TQFP (44-pin) EPM7064 J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin) EPM7064S, EPM7064AE J-lead (44-pin) J-lead (84-pin) TQFP (44-pin) PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-44 PLMJ7000-84 PLMT7000-44 FLEX FLEX 10KA FLEX 10KE FLEX 8000 FLEX 6000 9000 9000A 7000S 7000A EPM7512AE
PQFP (208-pin)
RQFP (208-pin) PLMT7000-208NC TQFP (144-pin) PLMT7000-144NC PQFP (208-pin) PLMR7256-208NC TQFP (144-pin) PLMT7000-144NC PQFP (208-pin) PLMR7256-208NC
Notes: Refer Altera 1998 Data Book device adapter information 5000 Classic devices. Altera offers adapter exchange program 0.8-micron EPM5032, EPM5064, EPM5130 programming adapters. FLEX 8000 Configuration EPROM. FLEX 10K, FLEX 8000, FLEX 6000 Configuration EPROM. These devices shipped carriers.
Table provides programming configuration compatibility information BitBlasterserial port, ByteBlasterparallel port, ByteBlasterMVparallel port download cables.
Table BitBlaster ByteBlaster Cable Compatibility
Device BitBlaster ByteBlaster ByteBlasterMV
TQFP (100-pin) PLMT7000-100NC EPM7096 J-lead (68-pin) J-lead (84-pin) PLMJ7000-68 PLMJ7000-84
PQFP (100-pin) PLMQ7000-100 EPM7128, EPM7128E J-lead (84-pin) PLMJ7000-84
PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 EPM7128A J-lead (84-pin) PLMJ7000-84 TQFP (100-pin) PLMT7000-100NC TQFP (144-pin) PLMT 7000-144NC
Note: This download cable available EPF6016 devices only.
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Altera Device Selection Guide
current information Altera FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices listed here. Information other Altera products located Altera 1998 Data Book. most up-to-date information about Altera products, Altera world-wide site http://www.altera.com. Contact Altera your local sales office current product availability.
FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A
GATES
10,000 10,000 20,000 30,000 30,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin RQFP, 240-Pin PQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-pin BGA1, 356-Pin BGA, 484-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 256-pin BGA1, 484-pin BGA1 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1, 484-Pin BGA1
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728
BITS
6,144 6,144 12,288 12,288 12,288
EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E
30,000 40,000 50,000 50,000 50,000
1,728 2,304 2,880 2,880 2,880
24,576 16,384 20,480 20,480 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E
70,000 100,000 100,000 100,000 100,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1, 600-pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1 208-Pin PQFP, 240-Pin PQFP, 256-pin BGA1, 356-pin BGA, 484-pin BGA1
3,744 4,992 4,992 4,992 4,992
18,432 24,576 24,576 24,576 49,152
EPF10K130V EPF10K130E EPF10K200E EPF10K250A EPF10K250E
130,000 130,000 200,000 250,000 250,000
599-Pin PGA, 600-Pin 240-Pin PQFP, 484-Pin BGA1, 672-Pin BGA1 599-Pin PGA, 600-Pin BGA, 672-pin BGA1 599-Pin PGA, 600-Pin 599-Pin PGA, 600-Pin BGA, 672-Pin BGA1
6,656 6,656 9,984 12,160 12,160
32,768 65,536 98,304 40,960 81,920
FLEX 8000 Devices
DEVICE
EPF8282A EPF8282AV EPF8452A EPF8452A EPF8636A EPF8636A EPF8820A EPF8820A EPF81188A EPF81500A
GATES
2,500 2,500 4,000 4,000 6,000 6,000 8,000 8,000 12,000 16,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 100-Pin TQFP 100-Pin TQFP 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
PINS
118, 112, 120, 112, 120, 148, 181,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,188 1,500
LOGIC ELEMENTS
1,008 1,296
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FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A
GATES
10,000 16,000 16,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1
PINS
812, 102, 117, 171, 199, 812, 117, 171, 1712 117, 171, 199, 218,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320
LOGIC ELEMENTS
1,320 1,320
EPF6024A
24,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin BGA1
1,960
1,960
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-15, -15, -15, -15,
7000 Devices
DEVICE MACROCELLS PIN/PACKAGE OPTIONS PINS SUPPLY VOLTAGE
SPEED GRADE
EPM7032AE EPM7032S EPM7032 EPM7032V EPM7064AE EPM7064S EPM7064 EPM7096 EPM7128A EPM7128S EPM7128E EPM7160S EPM7160E EPM7192S EPM7192E EPM7256A EPM7256S EPM7256E EPM7384AE EPM7512AE
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP/PQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin BGA1 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin PQFP/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP/PGA 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 208-Pin RQFP/PQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1
100, 120, 164, 132, 120, 176, 120, 176,
-10, -12, -12, -15, -10, -12, -10, -12, -10, -10, -10, -12, -15, -10, -12, -15, -10, -12, -15, -10, -10, -12, -15, -10, -10,
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Altera Digital Library CD-ROM version will available September 1998 from Altera Literature Services. This CD-ROM will contain current technical literature, including: Information Altera® device families, including FLEX® 10KE devices Information Altera's industry-leading MAX+PLUS development system current data sheets application notes current megafunction information, including AMPP Catalog, solution briefs, detailed technical information Altera MegaCorefunctions literature Altera in-system programmability (ISP) support Information target applications including digital signal processing (DSP), interface, networking applications
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