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Altera Unveils FLEX 10KE Devices
Altera recently unveiled enhanced versions FLEX® embedded programmable logic devices- FLEX 10KE devices. Fabricated 0.25-µm, five-layer-metal process with 2.5-V core, FLEX 10KE devices meet demands system designers increased functionality faster performance cost. FLEX 10KE devices, which include EPF10K100B devices, added enhancements that extend Altera's leadership embedded architectures levels performance silicon efficiency. Combined with inherent time-to-market benefits programmable logic, enhanced FLEX 10KE devices will accelerate movement high-speed designs from masked gate arrays programmable logic. Enhanced Features FLEX 10KE devices stands "enhanced" features. FLEX 10KE devices contain many powerful system-level features that boost design performance device utilization, including:
Figure summarizes enhanced FLEX 10KE features. Innovative Embedded Architecture Altera pioneered embedded programmable logic architecture 1995 combining EABs with logic array blocks (LABs). This architecture provided dramatic increase performance density industry's first embedded PLDs-FLEX devices. FLEX 10KE devices maintain this unique embedded architecture, while adding significant enhancements original family. FLEX 10KE devices pin- function-compatible with existing FLEX FLEX 10KA devices.
Figure Enhanced FLEX 10KE Features
Breakthrough Performance
Embedded array blocks (EABs) with double amount Kbits) Dual-port capability with first-on first-out (FIFO) performance Pin-selectable clamping diodes, which provide 3.3-V compliance 5.0-V tolerance same device 1.0-mm FineLine BGApackaging option, utilizing almost half board area traditional ball-grid array (BGA) packages power consumption MultiVoltI/O operation, supporting 2.5-V, 3.3-V, 5.0-V mixed-voltage systems
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Designed 100-MHz System Speed 150-MHz FIFO Buffers
Next-Generation Packaging
1.0-mm FineLine Packages Requires Half Board Area Standard Packages Minimizes Cost
Embedded Architecture Evolution
Dual-Port 4-Kbit with Width PCI-Compliant pins
Advanced Process Technology
0.25-µm CMOS SRAM Five-Layer-Metal Process 2.5-V Core with MutiVolt Interface Capability 5.0-V Tolerant Inputs
continued page
A-NV-Q298-01
Altera Corporation
Break Pack
HIGH PERFORMANCE High-Speed Programmable Logic Devices with System Performance DENSITY Programmable Logic Devices 250,000 Gates CUTTING-EDGE SOFTWARE MAX+PLUS II-the Industry's Best Development Tool POWERFUL MEGAFUNCTIONS Powerful Megafunctions from Altera's MegaCore Function Library AMPP Partners TEAMWORK ACCESS Partners Seamless Tool Integration
Altera Solution Booth #118 qualify free soccer ball.
Booth #118
35th Design Automation Conference Northern California Moscone Center Francisco, June 15-17, 1998
Altera Corporation News Views 1998
Contents
Features Altera Unveils FLEX 10KE Devices Customer Application: Creates Simple Node Using Altera Devices Altera News Coming Soon: AMPP Catalog, Version Benchmarks Measuring Design Performance FLEX 6000 Devices Compete Successfully with ASICs Language Hardware Support Tools Supported through ACCESS Program Altera European Technical Center AMPP Megafunctions Toll-Free Number Renewing Software Maintenance Devices Tools FLEX Devices Available 600-pin Packages EPF10K30A Devices Available 0.25-µm EPF10K100B Device Available June 1998 More FLEX 6000 Devices Coming Soon FLEX 6000 Family Offers 3.3-V 5.0-V Devices FLEX 6000 Device Availability Announcing EPC2 Device 9000A Device Availability Industrial-Temperature 9000A Device Available EPM7128A Devices Available 7000S Device Availability
7000 Product Transitions Network Licensing Available July 1998 Version-Controlled Licensing MAX+PLUS Version Discontinued Support SunOS Operating System Obtain MegaCore Functions Authorization Codes Microperipheral MegaCore Library Altera Introduces ByteBlasterMV Download Cable Target MegaCore Function Discontinued Devices Update
Technical Articles Selecting Right UART Megafunction Next-Generation Packaging FIFO Solutions FLEX Devices Design Tips from Altera Applications: Creating Efficient State Machine Questions Answers Every Issue Altera Publications Third-Party Programming Support Current Software Version Programming Hardware Support Altera Device Selection Guide Access Altera Response Form
information about this newsletter, submit questions, contact: Erica Heidinger, Publisher Craig Lytle, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 E-mail: n_v@altera.com
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Altera, ASCEND, ACCESS, AMPP, BitBlaster, ByteBlaster, ByteBlasterMV, FineLine BGA, EPC2, FLEX, FLEX 10K, FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Jam, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 5000, MAX, MAX+PLUS, MAX+PLUS MegaCore, MegaWizard, MultiCore, MultiVolt, OpenCore, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Advin Systems registered trademark Advin Systems, Inc. Alcatel registered trademark Alcatel Telecom GMBH. Verilog Cadence registered trademarks Cadence Design Systems. Exemplar Logic registered trademark Exemplar Logic, Inc. Integrated Silicon Systems registered trademark Integrated Silicon Systems, Inc. Mentor Graphics registered trademark Mentor Graphics, Inc. Data registered trademark Data Corporation. registered trademark Microelectronics, Inc. Synopsys registered trademark Synopsys, Inc. Synplicity registered trademark Synplicity, Inc. Viewlogic registered trademark Viewlogic Systems. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1998 Altera Corporation. rights reserved.
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1998
Features Altera Unveils FLEX 10KE Devices, continued from page Dual-Port
FLEX 10KE
Figure FLEX 10KE Dual-Port Block
Each FLEX 10KE dual-port capability, Kbits memory, bits width. These enhancements provide level performance efficiency implementing megafunctions such high-speed memories, first-in first-out (FIFO) buffers, specialized logic functions. EABs also support dual-port applications other large memory block requirements. Figure shows FLEX 10KE dual-port block. Advanced Process Technology FLEX 10KE devices based advanced 0.25-µm, five-layer-metal process consisting continuous transistor-free metal interconnect that optimizes multiple process metal layers. This architecture allows "stacking" metal layers. This "metal-friendly" architecture also supports sizes that half size comparable field programmable gate arrays (FPGAs). FPGAs transistor-heavy interconnects, which cannot "stacked" cannot optimize multiple process metal layers. Therefore, FPGAs have significant size increases, they sacrifice both cost-effectiveness performance. Figure shows smaller process geometry metal efficiency FLEX 10KE devices results size that smaller than comparable FLEX 10KA device less than half size comparable FPGA.
WR_ADD WR_DATA WR_CLK
RD_ADD RD_DATA RD_CLK
Breakthrough Performance FLEX 10KE devices provide significant performance improvements. With 0.25-µm, five-layer-metal process enhanced structure, these devices provide higher level system bandwidth today's demanding performance requirements. example, FLEX 10KE devices support 150-MHz FIFO buffer performance, with 6.5-ns access time memory block. Table shows FLEX 10KE-1 FIFO performance.
Table FLEX 10KE FIFO Speed
FIFO Size
FLEX 10KE-1 (MHz)
FLEX 10KA-1 (MHz)
Figure FLEX 10KE Comparison
Altera EPF10K100E Relative Size 0.25 4,992 Logic Cells EABs
Altera EPF10K100A Relative Size 0.35 4,992 Logic Cells EABs
Comparable FPGA Relative Size 1.91 0.35 4,608 Logic Cells EABs
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1998
Features
3.3-V Compliance
FLEX 10KE devices support Special Interest Group (PCI-SIG) Local Specification, Revision 2.1. devices will offer 100-MHz system speed support 66-MHz performance advanced communication applications, such 100-Mbit 1-Gbit Ethernet connections. addition, FLEX 10KE devices have pull-up clamping diodes every I/O, dedicated input, dedicated clock allow simultaneous compliance 5.0-V tolerance same device. These diodes clamp signal VCCIO value required 3.3-V compliance. They controlled pin-by-pin basis user-selectable option Altera® MAX+PLUS® software, which will allow device bridge between 3.3-V 5.0-V local-side device.
Innovative FineLine Packaging FLEX 10KE devices will available FineLine packages, which 1.0-mm packages that offer higher lead counts smaller package sizes. innovative FineLine packages have counts ranging from pins require less than half board area standard 1.27-mm packages. more details FineLine packages, "Next-Generation Packaging" page FLEX 10KE devices will also offered thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP) packages. Table Device Availability first FLEX 10KE device, 100,000-gate EPF10K100B device, scheduled released June 1998. This device process migration existing EPF10K100A device architecture will provide higher performance lower cost. more information availability EPF10K100B devices, contact Altera Applications (800) 800-EPLD your local sales representative. 50,000-gate EPF10K50E device will introduced fourth quarter 1998. Other FLEX 10KE devices scheduled released early 1999. Table page shows FLEX 10KE device availability.
Lower Power Consumption MultiVolt Interface
FLEX 10KE devices have core supply voltage which reduces power consumption significantly. FLEX 10KE devices also offer MultiVolt interface, which enables core operation allows pins compatible with 2.5-V, 3.3-V, 5.0-V devices.
Table FLEX 10KE Device Features
Features
Gates (logic RAM) Usable gates Logic elements EABs Total bits Package Options
EPF10K30E
30,000 22,000 119,000 1,728 24,576 144-pin TQFP 256-pin 484-pin
EPF10K50E
50,000 36,000 199,000 2,880 40,960 144-pin TQFP
EPF10K100E
100,000 62,000 257,000 4,992 49,152 208-pin PQFP
EPF10K100B
100,000 62,000 158,000 4,992 24,576 208-pin PQFP 240-pin PQFP 256-pin
EPF10K130E
130,000 82,000 342,000 6,656 65,536 240-pin PQFP 484-pin 672-pin
EPF10K200E
200,000 123,000 513,000 9,984 98,304 240-pin RQFP 599-pin 600-pin 672-pin
EPF10K250E
250,000 149,000 474,000 12,160 81,920 240-pin RQFP 599-pin 672-pin
208-pin PQFP 208-pin PQFP 240-pin PQFP 240-pin PQFP 256-pin 356-pin 256-pin 484-pin 484-pin
continued page
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1998
Devices
&TOOLS
FLEX Update
FLEX 6000 Family Offers 3.3-V 5.0-V Devices Altera shipping 3.3-V EPF6024A 5.0-V EPF6016 devices, which deliver higher performance prices directly competitive with gate arrays. These FLEX 6000 devices combine fast time-to-market flexibility with exceptionally cost high-volume applications. Table
Table EPF6016 EPF6024A Device Features
Feature
Process geometry Supply voltage migration Gate count Logic elements
FLEX Devices Available 600-Pin Packages Altera shipping EPF10K100A EPF10K130V devices 600-pin ball-grid array (BGA) packages. This package supports more pins, which allows take advantage FLEX® performance density applications that require high number pins. Contact your local Altera® sales representative Altera Applications (800) 800-EPLD more information about these package offerings. EPF10K30A Devices Available EPF10K30A devices provide ultra-high system performance (e.g., 8-bit, 16-tap filter) that addresses design engineers' performance needs. EPF10K30A devices available 144-pin thin quad flat pack (TQFP), 208-pin plastic quad flat pack (PQFP), 240-pin PQFP packages. Devices 356-pin packages scheduled release July 1998. 0.25-µm EPF10K100B Device Available June 1998 Initial shipments EPF10K100B devices will available June 1998. Built 0.25-µm, 5-layer-metal process, EPF10K100B devices offer high performance cost. With 2.5-V core, EPF10K100B devices less power than comparable 3.3-V field-programmable gate arrays (FPGAs). Additionally, MultiVoltfeature enables EPF10K100B devices interface with 2.5-V, 3.3-V, 5.0-V devices. EPF10K100B devices will available 240-pin PQFP, 208-pin PQFP, 256-pin packages. More FLEX 6000 Devices Coming Soon Altera plans ship EPF6016A devices June 1998 EPF6010A devices July 1998. Both devices manufactured 0.35-µm, triple-layer-metal process offer 3.3-V supply voltage. EPF6016A device offers 16,000 usable gates, EPF6010A device will offer 10,000 usable gates. more details, contact your local sales representative Altera Applications (800) 800-EPLD.
EPF6016
8,000 16,000 1,320 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin
EPF6024A
0.35 12,000 24,000 1,960 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin
User (maximum) Package options
FLEX 6000 Device Availability Table shows FLEX 6000 device availability.
Table FLEX 6000 Device Availability
Device Availability 100-Pin 144-Pin 208-Pin 240-Pin 256-Pin TQFP TQFP PQFP PQFP
EPF6010A July 1998 EPF6016 EPF6016A June 1998 EPF6024A
Configuration EPROM Update
Announcing EPC2 Device Altera plans introduce EPC2 device-Altera's first reprogrammable Configuration EPROM-in October 1998. single EPC2 device will able configure FLEX device 130,000 gates will programmable in-system using IEEE Std. 1149.1 Joint Action Test Group (JTAG) boundary-scan test (BST) ports. Altera plans offer EPC2 device 20-pin PLCC 32-pin TQFP packages. EPC2 device will pin-compatible with existing Altera Configuration EPROMs same package. EPC2 will operate
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1998
Devices Tools
Update
9000A Device Availability With propagation delays fast 9000A devices offer significant performance enhancement cost reduction over existing 9000 devices. Production quantities high-performance EPM9320A EPM9560A devices available today. Table summarizes 9000A device availability.
Table 9000A Device Availability
Device
EPM9320A EPM9560A
Table 7000S Device Availability
Device
EPM7032S EPM7064S
Package
44-pin PLCC 44-pin TQFP 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10,
Availability
EPM7128S
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP
(ns)
Availability 84-Pin 208-Pin 240-Pin 356-Pin PLCC RQFP RQFP
EPM7160S
84-pin PLCC 100-pin TQFP 160-pin PQFP
EPM7192S EPM7256S
160-pin PQFP 208-pin RQFP
Industrial-Temperature 9000A Devices Available 7000 Product Transitions Altera offers industrial-temperature speed grade EPM9560 devices 240-pin power quad flat pack (RQFP) packages. addition, speed grade EPM9560A devices 208-pin RQFP packages, EPM9320A devices 84-pin PLCC 208-pin PLCC packages, will available 1998. EPM7128A Devices Available Based Altera's industry-leading architecture, EPM7128A devices support MultiVolt pins, pin-compatibility with 5.0-V 7000S devices, propagation delays fast Altera currently offers speed grade EPM7128A devices 84-pin PLCC, 100-pin TQFP, 144-pin TQFP packages. addition, Altera plans ship EPM7256A devices June 1998. EPM7064A device will begin shipping third quarter 1998. three devices will supported MAX+PLUS version 9.0. 7000S Device Availability 7000S devices fastest product-term-based PLDs, with speed grades fast These devices offer features such ISP, IEEE Std. 1149.1 JTAG circuitry devices with more macrocells, open-drain output option. Table describes 7000S package options, speed grades, availability. Altera migrating 7000 devices from 0.65-µm process 0.5-µm process. Table outlines process migration schedule lists reference documentation associated with this migration. download these documents from Customer Notification page Altera site http://www.altera.com.
Table 7000 Process Migration Schedule
Device
EPM7032 EPM7064 EPM7064S EPM7128E EPM7128S EPM7160E EPM7192E EPM7192S EPM7256S EPM7256E
Note
Process
0.5-µm 0.5-µm 0.5-µm 0.5-µm 0.5-µm 0.5-µm
Reference
Date
August 1998 Complete Complete October 1998 Complete Complete
Note
PCN9703 ADV9803 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9803 ADV9708 ADV9708 PCN9703 ADV9708
Notes: This process transition will result changes data sheet parameters ordering codes. Altera site http://www.altera.com advisories process change notices.
continued page
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Devices Tools Devices Tools, continued from page supported MAX+PLUS version higher Solaris 2.5+, HP-UX 10.20+, 4.1+. Obtain MegaCore Functions provide with most up-to-date functions, download Altera MegaCorefunctions Altera site http://www.altera.com/html/ products/megacore.html. Altera site most up-to-date function files, allows begin designing with Altera MegaCore functions immediately. Because MegaCore functions downloaded from web, Altera will stop distributing functions MAX+PLUS CD-ROM, starting with MAX+PLUS version 8.3. Authorization Codes Microperipheral MegaCore Library Altera provides individual authorization codes each seven MegaCore functions entire Microperipheral MegaCore Library (ordering code: PLSM-MICROLIB). functions are:
Tools Update
Network Licensing Available July 1998 With release MAX+PLUS® version July 1998, floating-node licenses will available both (ordering code: PLS-NET/PC) UNIX platforms (ordering code: PLS-WS/xx). floating-node license platforms served from UNIX Windows NT-based license server. license file utilizes either UNIX server host network interface card (NIC) Windows servers. floating-node design sites will have list price $6,995 node. Additionally, software maintenance both UNIX floating-node licenses will covered maintenance product (ordering code: PLAESW-FLOAT, list price: $1,695 node). Altera will also continue sell fixed-node design sites that based MAX+PLUS software guards (i.e., PLS-MAGNUM PLS-BASE). Altera will offer floating-node license special promotional price customers with valid maintenance agreements existing fixed-node design sites. This special promotional price $1,495 node will available from July 1998 September 1998. more information this promotion, your local Altera sales representative about PLS-PROMO design site. Version-Controlled Licensing MAX+PLUS Version Starting with MAX+PLUS version 9.1, Altera will introduce version-controlled licensing, which will require have valid maintenance agreement utilize features each release. Altera will send license file maintained customers before MAX+PLUS version released. will also able generate license file Altera® site http://www.altera.com. Discontinued Support SunOS Operating System Beginning with MAX+PLUS version 9.1, scheduled release October 1998, Altera will longer provide MAX+PLUS support SunOS operating system. SunOS system been updated several years, does UltraSPARC machine, cannot support MAX+PLUS integrated features such Verilog synthesis MegaWizardPlug-Ins. UNIX operating systems that will
a8237 Programmable Controller a8251 Programmable Communications Interface a8255 Programmable Peripheral Interface Adapter a8259 Programmable Interrupt Controller a6402 Universal Asynchronous Receiver/ Transmitter a16450 Universal Asynchronous Receiver/ Transmitter a6850 Asynchronous Communications Interface Adapter
Previously, Altera provided single authorization code entire library. have license these functions individually (list price: $1,995 each) license entire Micropheripheral MegaCore Library (list price: $7,995). purchased Microperipheral MegaCore Library have seven individual authorization codes, please contact Altera Customer Service (800) SOS-EPLD. This library functions available Altera site megacore.html. should always site most current Microperipheral MegaCore library. MegaCore files from MAX+PLUS Software CD-ROMs. Altera Introduces ByteBlasterMV Download Cable Altera introduces ByteBlasterMVparallel port download cable (ordering code: PL-BYTEBLASTERMV),
Altera Corporation News Views 1998
Devices Tools which supports both 3.3-V 5.0-V in-system programmability (ISP)-capable devices. ByteBlasterMV download cable interface with standard 25-pin parallel port, uses same 10-pin circuit board connector ByteBlasterand BitBlasterdownload cables. download cable fully compatible with existing circuit boards. ByteBlasterMV download cable allows users program MAX® 9000, 7000S, 7000A devices in-system, configure FLEX® 10K, FLEX 8000, FLEX 6000 devices in-circuit standard parallel port. more information, refer ByteBlasterMV Parallel Port Download Cable Data Sheet Altera site http://www.altera.com, contact your local Altera sales representative. Target MegaCore Function Altera introduces target interface MegaCore function (ordering code: PLSM-PCIT1, list price: $4,995), which targets FLEX FLEX 6000 devices. more information about this MegaCore function, contact your local sales representative.
Discontinued Devices Update
Altera announced that various products will discontinued (see table below). Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera sales representative. Selected ADVs, PDNs, complete listing discontinued devices also available Altera's world-wide site http://www.altera.com. Rochester Electronics, after-market supplier, offers many discontinued Altera products. Contact Rochester Electronics (508) 462-9332 their site http://www.rocelec.com.
Discontinued Device Ordering Codes
Device Family
FLASHlogic
Device
EPX880 EPX8160 (all packages, temperature grades, speed grades) EPFX740 (all packages, temperature grades, speed grades)
Last Order Last Shipment Reference Date Date
6/30/97 3/31/97 6/30/98 9/30/97 PDN9625 PDN9516
Altera Unveils FLEX 10KE Devices, continued from page MAX+PLUS Software Support
Table FLEX 10KE Availability
Software support FLEX 10KE devices will included MAX+PLUS software, version July 1998. more details, contact Altera Applications (800) 800-EPLD. Conclusion With enhanced features such dual-port RAM, FineLine packaging, 2.5-V core with MultiVolt capability, FLEX 10KE devices provide increased performance efficiency cost. more information about FLEX 10KE devices, contact Altera Applications (800) 800-EPLD your local sales representative.
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Device
EPF10K30E EPF10K50E EPF10K100E EPF10K100B EPF10K130E EPF10K200E EPF10K250E
Availability
First Half 1999 1998 First Half 1999 June 1998 First Half 1999 First Half 1999 First Half 1999
Technical
ARTICLES
Selecting Right UART Megafunction
universal asynchronous receiver/transmitter (UART) module low-cost serial communication between central processing units microprocessor microcontroller. UART protocols implemented programmable logic devices (PLDs) available Altera® Microperipheral MegaCoreFunction library from Altera Megafunction Partners Program (AMPPSM) partners. About UARTs basic UART protocol consists transmitting receiving serial information through data line status line both directions. Each data packet contains various numbers information bits, stop bits, parity bits. UARTs generally used with RS-232 hardware, which converts -12-V signals +12-V signals, vice versa. Many UARTs have processor interface which instructs UART filling registers with commands settings. UARTs also have various buffer sizes received data. When character received UART, transferred buffer interrupt sent central processing unit (CPU), which reads stored data makes space next packet. UART megafunctions usually listed under different acronyms chipset microcontrollers address different combination requirements. Some these acronyms are:
Benefits UARTs Programmable Logic Implementing UART megafunctions PLDs offers several benefits compared application-specific standard product (ASSP):
Higher data rates Lower system cost Faster time-to-market
Higher Data Rates
From performance standpoint, programmable logic offers highest data rates. example, CAST Inc., AMPP partner, c16550 megafunction that allows easily achieve transmission rates Mbps. system level, UART megafunction implemented reduce number instruction cycles system CPU, therefore increases overall performance.
Lower System Cost
microcontroller typically different types peripheral UARTs with parameters. designs whole capability these UARTs; however, many designs require specific features that included with standard product. example, your design require c16550 UART megafunction with deep first-in first-out (FIFO) buffer, baud-rate generation. designing with chipset solution, must under-utilized baud rate feature memory FIFO buffer your board, increasing your overall system cost. These additional production costs eliminated when implement user-parameterizable UART megafunction PLD. using reprogrammable UART megafunctions, easily make changes your prototype design after implementation.
ACIA (Asynchronous Communications Interface Adapter) (Dual Asynchronous Receiver Transmitter) DUART (Dual Universal Asynchronous Receiver Transmitter) MUART (Multifunction Universal Asynchronous Receiver Transmitter), (Serial Input Output) USART (Universal Synchronous/Asynchronous Receiver/Transmitter)
Faster Time-to-Market
Programmable logic most flexible solution when implementing UART megafunctions greatly contributes decreasing time-to-market. example,
Musical Instrument Digital Interface (MIDI) Infrared Data Association (IrDa) communications interfaces also incorporate UART functionality.
Altera Corporation
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1998
Technical Articles CAST Inc. offers large number UART megafunctions with standard protocols such C16450, C16550, C6850, C8251 megafunctions, well user-customized C_UART megafunction. addition, CAST also provides VHDL simulation test-bench with each UART megafunction guarantee protocol's functionality. UART Megafunction Parameters When starting digital design that requires UART megafunction, must decide:
Protocol: Fixed Programmable Number Bits: Other (specify): Number STOP Bits: Other (specify): Parity: Even parity FIFO Depth: Reception depth Transmission depth
Other Solutions UART megafunctions available from Altera Microperipheral MegaCore library from AMPP partners such CAST, Inc. Fastman, Inc. preview megafunctions before licensing OpenCorefeature available with MAX+PLUS software. This pre-purchase evaluation system allows instantiate simulate UART megafunctions generate programming files. Conclusion more information about UART megafunctions offered through these Altera programs, contact Altera Applications (800) 800-EPLD your local sales representative Altera site http://www.altera.com.
many UARTs does system require? What type back (Intel, Motorola, other specific bus)? What baud rate generator requirements? Which frequency? What number information bits character? What number stop bits? Which type parity checking should used? What direction UART function (transmitter, receiver, both)? Does UART require fixed programmable protocol? What FIFO buffer depth?
Checklist Selecting Right UART Megafunction following checklist will help select right UART megafunction your design needs. Complete information this checklist then contact Altera Applications (800) 800-EPLD further assistance.
Functionality Needed (check that apply): 16450 function 16550 function 6402 function 6850 function 8251 function C_UART function MIDI function Other (specify): Custom Core (check that apply): Asynchronous Synchronous HDLC
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1998
Technical Articles
Next-Generation Packaging
1.0-mm pitch plastic ball-grid array (BGA) package, called FineLine BGApackage, Altera's latest innovative space-saving package. This package minimizes printed circuit board (PCB) size meets challenges high-density programmable logic devices (PLDs). Currently, 1.0-mm FineLine package provides most board space efficiency other package, requiring less than half board space conventional 1.27-mm packages even less board space when compared conventional quad flat pack (QFP) packages. Features FineLine packages have following features:
Conclusion With 1.0-mm FineLine package, Altera continues cutting-edge leadership providing more advanced flexible packages. FLEX® 10KE, FLEX 10KA, FLEX 6000, MAX® 7000A devices will available 1.0-mm FineLine packages. These FineLine packages also meet specifications industry-standard JEDEC Publication detailed information FineLine package, contact Altera Applications (800) 800-EPLD your local sales representative.
Table FineLine Package Types
Lead Count
count ranging from leads Easy prototyping Compatible with solder reflow processes
Package Size (mm)
Table shows planned FineLine packages. Packaging Efficiency FineLine packages offer more board space savings higher lead density compared conventional 1.27-mm packages. Table compares packaging efficiency 1.0-mm FineLine plastic quad flat pack (PQFP), thin quad flat pack (TQFP), 1.27-mm packages.
Table Package Type Comparison
Package TQFP
PQFP
1.27-mm
FineLine
Package Size (mm) Board Area (in2) Lead Count Lead Density
Table shows, 144-lead TQFP package uses (leads/in2) almost same amount area 672-lead FineLine package, while 356-lead conventional Figure FineLine 1.27-mm Package Comparisons package requires almost twice area 672-lead 1.27-mm Ball Pitch FineLine package. average, 1.0-mm FineLine packages less than half board space 1.27-mm packages. addition lower package costs, board space savings significantly minimizes manufacturing costs. Figure
356-Lead Package
256-Lead Package
600-Lead Package
484-Lead FineLine Package 672-Lead FineLine Package
256-Lead FineLine Package
1.0-mm Ball Pitch
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1998
Technical Articles
FIFO Solutions FLEX Devices
Altera offers multiple first-in first-out (FIFO) buffer design solutions FLEX® devices. FIFO buffer used buffer data transferred from subsystem another design. instance, FIFO buffers used hold data driving from multiple sources shared bus. When busy, data stored FIFO buffer; when free, FIFO buffer sends data bus. most FIFO buffers, FLEX embedded array blocks (EABs) provide high performance, large size, logic-vs.-memory tradeoffs. FIFO buffers implemented logic elements (LEs) also provide good solution, depending upon your FIFO needs. When using FIFO buffers, must consider various system requirements. example, must consider whether FIFO buffer needs read from written simultaneously. Some FIFO buffers require separate read write clocks, while others have same clock reading writing. Altera offers FIFO solutions meet these requirements. Interleaved-Memory FIFO interleaved-memory FIFO buffer well-suited relatively deep buffers that have read/write clock. this FIFO buffer, EABs used each bits width. implement FIFO buffer words deep without using additional EABs. Each read written given clock cycle. using EABs, implement simultaneous reads writes. Data pre-fetched from non-written EAB, which prevents conflicts that occur during simultaneous reads writes same EAB. This FIFO buffer achieve 80-MHz performance FLEX 10KA device. Cycle-Shared FIFO cycle-shared FIFO buffer well-suited designs that require many EABs addition FIFO buffer, because uses fewer EABs than interleaved-memory FIFO buffer. This FIFO buffer read/write clock, EABs time-domain multiplexed with doubled clock. That read written subsequent doubled clock cycles. example, cycle-shared FIFO buffer with 33-MHz throughput implemented with 66-MHz clock will achieve 40-MHz performance FLEX 10KA device. Arbitrated FIFO some FIFO applications, simultaneous read write required. instance, asynchronous transfer mode (ATM) design have FIFO buffers where entire 53-byte cell read written burst. Adesign have multiple FIFO buffers, where port writes cell FIFO buffer while another port reads cell from different FIFO buffer. application that does require simultaneous reads writes arbitrated FIFO buffer. arbitrated FIFO buffer uses store buffered data. parameter allows prioritize reading writing. arbitrated FIFO buffer uses read/write clock, running over FLEX 10KA device. Synchronous LE-Based FIFO Sometimes more FIFO buffers required than available EABs target device. Alternatively, FIFO buffer required FLEX 6000 design. either case, synchronous LE-based FIFO buffer provides cost-effective solution; creates shift registers store data FIFO buffer. This FIFO buffer ideal multiple shallow, wide FIFO buffers with read/write clock. synchronous LE-based FIFO buffer good high-speed applications, achieve over 100-MHz performance. Asynchronous LE-Based FIFO applications that require distinct read write clocks, asynchronous LE-based FIFO buffer offers ideal solution. FIFO buffer buffer data coming from 33-MHz 50-MHz back end. These FIFO buffers referred "asynchronous," "two-clock," "bisynchronous." asynchronous LE-based FIFO buffer created using bank registers store data. write counter decoded determine which registers write multiplexer used determine which registers read. memory structure created from registers multiplexers read written simultaneously, because reading multiplexer independent write decoders. This structure written read with different clocks. FIFO buffer control circuitry prevents metastable disturbances system.
continued page
Altera Corporation
News Views
1998
Design Tips
Altera Applications
Creating Efficient State Machine
This article second four-part series that discusses practical design tips from Altera Applications. This article shows create efficient state machine when using VHDL. Upcoming issues News Views will feature following topics:
Figure Sample State Machine
32-Bit Counter
Using arithmetic operators MAX+PLUS® VHDL Importance hierarchical instantiation
Eight Multiplexers
using design techniques discussed this article, will learn distinguish between efficient inefficient state machines, which help maximize your design's overall performance. inefficient state machines, your design achieve your performance requirements. ensure that your design achieves performance needed, Altera Applications recommends that follow these state machine coding guidelines:
State Machine
Remove arithmetic functions data paths from state machine. Only state machine control logic inside Statements. control variables signals right-hand side signal assignments, except state assignments.
Figure illustrates state machine that directly controls counter eight multiplexers. following MAX+PLUS VHDL examples show different ways create state machine shown Figure Example shows inefficient create this state machine, while Example presents more efficient method. Example Inefficient Coding Method ELSIF (clk'EVENT `1') THEN muxout muxa; CASE state WHEN
(sm_in(4) sm_in `1') THEN state muxout muxc; count count `1'; ELSIF (sm_in(1) `1') THEN state count count `1'; ELSE state muxout muxb; WHEN Example multiplexer output signals controlled within Statement, which create extra logic multiplexer control signals. counter also incremented decremented within Statement, which cause counters inferred.
Altera Corporation
News Views
1998
Design Tips Example Efficient Coding Method ELSIF (clk'EVENT `1') THEN muxsel "00"; count_en "0"; count_ud "0"; count count down CASE state WHEN (sm_in(4) sm_in `1') THEN state muxsel "10"; count_en "1"; ELSIF (sm_in(1) `1') THEN state count_en "1"; count_ud "1"; ELSE state muxsel "01"; contrast, Example control signals inside Statement, counter multiplier declared outside Statement. This style more efficient because allows state machine control only counter multiplexer, without creating extra logic. counter multiplexer declared separate structures, inferred state machine. Separating counter multiplexer from state machine gives more efficient results. more information creating efficient state machine, contact Altera Applications (800) 800-EPLD.
Coming Soon: AMPP Catalog, Version
AMPP Catalog version will available June 1998 from Altera Literature Services. This catalog describes Altera Megafunction Partners Program (AMPP), includes megafunction descriptions profiles each AMPPSM partner. Contact Altera Literature Services (888) 3-ALTERA your Altera sales representative copy. AMPP Catalog also available Altera site http://www.altera.com. FIFO Solutions FLEX Devices, continued from page This FIFO buffer ideal applications with independent read write clocks, combined with other FIFO buffers create larger FIFO buffers with independent read write clocks. achieve 60-MHz performance FLEX 10KA device. Combination Functions Conclusion Altera also offers combination FIFO solutions certain designs. instance, asynchronous FIFO buffer built using small asynchronous LE-based FIFO buffer with EAB-based FIFO buffer. This type FIFO buffer combines size performance store data while using buffer clock rates. FLEX devices, combined with FIFO functions, provide good solutions designs with FIFO requirements. These solutions meet wide variety FIFO requirements offer high performance large size costs. more information Altera FIFO buffer solutions, contact Altera Applications (800) 800-EPLD your local Field Applications Engineer.
Altera Corporation News Views 1998
cycle-shared FIFO buffer available csfifo provided MAX+PLUS software. Other functions will included future MAX+PLUS releases. functions parameterizable, simply need parameters your system requirements create custom logic your design.
Questions
&ANSWERS
name output pin, MAX+PLUS software will give following error message: "Illegal assignment- a[12.9], b[2.0] <number>" example, name array input pins a[12.9], b[2.0]. name output pins: must break group into output buses: a[12.9] output b[2.0] separate output pin.
configure EPF10K100B FLEX® 10KE device with FLEX FLEX 10KA configuration file? cannot FLEX FLEX 10KA configuration file configure EPF10K100B FLEX 10KE devices, because these devices have different features. example, EPF10K100B device pin-by-pin switchable clamp feature that available EPF10K100A devices. Additionally, FLEX 10KE device enhanced structure differs from that FLEX FLEX 10KA devices.
must WIRE primitive rename with single name matching width: c[7.0].
check setup/hold time violation messages when performing VITAL simulation MAX+PLUS® VHDL output file? default, VITAL simulator does return setup/hold time violation messages when performing VITAL simulation MAX+PLUS output file. show setup/hold time violation messages, perform following steps: Edit VHDL/VITAL file atl_vtl.vhd /usr/maxplus2/vhdl93/vital/v3_0 UNIX workstations <drive letter>\maxplus2\vhdl93\ vital\v3_0 PCs) change Constant Definition True Statement that matches following line:
CONSTANT DefTimingMsgOn BOOLEAN TRUE
obtain in-system programmability (ISP) support programming Altera® devices with embedded processors in-circuit testers? using Altera embedded processor in-circuit tester environment, register join Altera Support Program. With this program, Altera Application Engineers offer extensive support your implementations. When join program, Altera will send authorization code e-mail that enables Serial Vector Format (.svf) File JamComposer support your MAX+PLUS software. Altera recommends that upgrade your MAX+PLUS software latest version ensure support File Composer. inquire about Altera Support Program, send e-mail ispembed@altera.com using embedded processors, ispate@altera.com using in-circuit testers.
Reanalyze modified alt_vtl.vhd library file. VITAL simulator returns setup/hold violation messages. What maximum input leakage current FLEX MAX® 7000A devices with
Although FLEX Embedded Programmable Logic Family Data Sheet (1998 Data Book) states that maximum input leakage current when GND, this specification actually valid when maximum recommended input voltage, which
perform in-system programming with suffix 7000 devices?
MAX+PLUS sequential group bus) naming feature name input output pin?
sequential group bus) naming feature used only name input internal node, output pin. using this feature
In-system programming performed with either adaptive constant algorithm. Because some in-circuit test (ICT) platforms have difficulties supporting adaptive algorithm, Altera offers devices tested with constant algorithm. 7000 devices tested constant algorithm marked with suffix ordering code.
Altera Corporation
News Views
1998
Questions Answers 7000 devices also programmed systems that adaptive algorithms, such systems that BitBlasterserial download cable, ByteBlasterparallel download cable, ByteBlasterMVparallel download cable, embedded processors.
Reflow recommendations surface-mount devices located Application Note (Reflow Soldering Guidelines Surface-Mount Devices), which found 1998 Data Book Altera site.
What minimum transaction length a16450 universal asynchronous receiver/transmitter (UART) MegaCorefunction? minimum transaction length a16450 UART MegaCore function single-cycle read write. default, a16450 MegaCore function uses following settings: input signals registered dout[] output signal registered
have special system power-up sequence when using FLEX 10KE (including EPF10K100B), FLEX 10KA (including EPF10K50V EPF10K130V), FLEX 6000 devices? have special power-up sequence when using FLEX 10KE, FLEX 10KA, 3.3-V FLEX 6000 devices. They tolerate power-up sequence. MultiVolt interface allows device bridge between systems operating different voltages. example, 5.0-V input signals drive FLEX 10KE, FLEX 10KA, 3.3-V FLEX 6000 device before 3.3-V applied device, drive signals into them before power-up.
these default settings, a16450 MegaCore function uses clock cycles perform read write. first cycle, valid input signals need asserted enable input registers. first clock edge, input signals written into registers. write second cycle, must assert write data second clock edge. read second cycle, must assert valid data appear dout[] signal after second clock edge. change parameters that control registering input output signals, eliminate input registers signals, and/or output register dout[] signal. Eliminating these input output registers allow perform single-cycle reads writes.
receive following error message: "Initialization failed. Check licensing server name port number license file?" receive this network licensing error message when trying MAX+PLUS PLS-WEB version 8.2. This error message occurs using network license file that generated PLS-WEB version 8.1. obtain license file PLS-WEB version from Altera site http://www.altera.com. This error message also occur your license.dat file contains carriage returns. Make sure that feature line contained line with carriage returns.
Where find information regarding moisture sensitivity related handling recommendations Altera devices? There three sources information moisture sensitivity related handling recommendations Altera devices: JEDEC moisture ratings Altera devices found Altera Customer Notifications page Altera site http://www.altera.com. Drypack handling guidelines given Application Note (Guidelines Handling J-Lead Devices), which found 1998 Data Book Altera site.
drive 5.0-V device input pins before VCCINT powered
Altera does recommend driving 5.0-V device input signals before VCCINT powered Applying VCCINT before driving inputs correctly biases device substrate. This process ensures that these input signals overshoot undershoot specified limit acceptable logic levels, which also prevents device from latching
Altera Corporation
News Views
1998
Customer
Application
Creates Simple Node Using Altera Devices
"The issues were understanding customer needs reflecting them product, time market," said Yusuke Nishimura.
With demands faster better communication, volume traffic corporate public networks increasing rapidly. cope with demand, networking engineers seeking create type network, that distinguish between voice data signals transmit them efficiently over existing systems leased lines, ISDN lines, public networks. system should also future system. This challenge that motivated engineers Shizuoka, design center Corporation, design Simple Node. Integrated Node with Hybrid Multiplexing time delays both transmitted efficiently, reducing communication costs. Simple Node processes low-speed, short-time-delay voice data signals, well low-speed, longer-time-delay hostterminal data signals high-speed, burst inter-LAN data signals. assigns optimum bandwidth band-pass these different types signals, outputs data transmission line. With Simple Node, circuit switching time-division multiplexing accomplished compact system. designers used Altera® FLEX® 8000 MAX® 7000 devices Simple Node boards. Their decision Altera devices based their desire satisfy customer needs bring product market quickly. "The issues were understanding customer needs reflecting them product, time-to-market," said Yusuke Nishimura, assistant manager transmission engineering department Shizuoka. flexibility Altera PLDs ease MAX+PLUS® software allowed them specifications design boards simultaneously, adding features modifying designs necessary. "One reasons selected Altera devices quality design tool. MAX+PLUS software very easy use," said Yusuke Nishimura. Figure shows Simple Node block diagram. Dynamic Band Assign Module (DBM) product's innovative feature, where hybrid multiplexing takes place. Figure shows block diagram. controls bandwidth assigns both fixed variable band-pass. boards shown Figure page
"One reasons selected Altera devices quality design tool. MAX+PLUS software very easy use."
Simple Node integrated node that uses hybrid multiplexing combine functions time-division multiplexer (TDM) with private branch exchange (PBX). Hybrid multiplexing optimizes both bandwidth band-pass circuits that voice data signals with differing speeds
Figure Simple Node Block Diagram
Main Signal Transmission line
Fixed channel
DMINS DMCH Demand channel DMCH
NET64
FF/FR port
FRAD
FRAD: LIF: DMCH: DBM: DMINS:
Frame assembly/disassembly Router Frame forward Frame relay Line interface Demand channel Dynamic band assign module Information network system line interface card dynamic band assign module
Frame Interface
Control Pass
DMINS Interface
Altera Corporation
News Views
1998
Customer Application Simple Node contains following Altera devices:
EPF8820AQC160-4 devices line interface (LIF) that connects frame relay. EPM7160ELC84-15 device alarm that monitors hardware transmission interrupt frame-to-frame transfer. EPF8452AQC160-4 devices EPF8820AQC160-4 devices time slot assign that allots signal board. EPM7128ELC84-10 devices control pass that sets control path through band-assign modules. EPF8452AQC160-4 device demand watchdog that monitors demand from low-speed channel.
Forward/Frame Relay port Frame Assembly/Disassembly (FRAD), which performs logic multiplexing them. data from FRAD output time-division multiplexer (TDM), which multiplexes data frame relay bandwidth (see Figures outputs through line interface transmission line. networks based traditional TDMs, bandwidth fixed therefore occupied even when being used. bandwidth sharing frame relay band-pass demand band-pass provided FRAD allows bandwidth flexibility improves circuit efficiency.
Contact Information: Corporation Corp. Communications System Division 33-7 Tokuei Bldg. Chome Shiba Minato-ku, Tokyo Japan Phone: (81) 3340 9480
continued page
Figure Dynamic Band Assign Module Block Diagram
Simple Node Simple Node functions fixed channel interface demand channel interface connecting through main signal bus. Low-speed, short-time-delay data passed from fixed channel interface DBM, which multiplexes data fixed bandwidth (see Figure page outputs transmission line through Line Interface (LIF). Connection calls carrying voice data passed from demand channel interface DBM. confirms changes needed bandwidth assignment, changes required bandwidth demand band-pass (see Figures page 20), then outputs data transmission line through line interface using high-quality voice compression that complies with ITU-T G.728/G729. Low-speed, longer-time-delay data signals high-speed, burst data signals passed from Frame
Altera Corporation News Views 1998
Frame Interface
DMINS Port
DBUS
Frame Synchro
Loop
Alarm CBUS Control Path Interface
Time Slot Assign
Demand Watchdog
Information Processing
Test DMINS Control Board
Time Management
Customer Application Customer Application, continued from page
Figure Three PCBs Comprising
Conclusion
Figure Transmission Band Dynamic Variable Bandwidth
Band-pass low-speed, short-time-delay data
Demand band-pass
With Altera devices MAX+PLUS software, transmission engineers were full control design schedule Simple Node integrated node. They were able incorporate changes into specifications, integrate features into design, still bring this innovative product market time.
Band-pass low-speed, longer-time-delay data high-speed, burst data
Figure Band-Pass Assignment
Bandwidth
Fixed band-pass Demand band-pass
Frame relay band-pass Time
Altera Corporation
News Views
1998
Altera
Benchmarks Measuring Design Performance
When selecting programmable logic devices (PLDs), most designers compare density, price, performance decide which devices meet their design requirements. Designers generally compare density price looking price list contacting sales representative. Comparing performance, however, more challenging process. determine performance, must consider numerous factors such signal routing, logic complexity, type memory interface, fan-out. With many factors involved determining performance, difficult predict performance accurately. develop general guidelines selecting PLDs determining design performance, Altera® Applications recently completed multiple experiments that several independent benchmarks. evaluating results from these experiments, estimate design's performance before implementation. Likewise, will allow compare performance Altera devices with other manufacturers' PLDs under identical conditions. This article summarizes five main benchmarks used upcoming experiments. Typical Applications typical applications benchmark measures design performance using large designs that commonly found high-density applications such interface, digital signal processing (DSP) functions, control circuitry. designs used this benchmark were created VHDL Verilog independent consultants compiled with timing-driven compilation. Because manual optimization design techniques were used this benchmark, results show worst-case performance designs similar type. Logic Routing Analysis Conclusion logic routing analysis benchmark analyzes routing logic utilization using varying routing distances logic complexities determine performance. Although this benchmark effective predicting real design performance particular design, helpful determining performance differences between different architectures.
Altera Corporation News Views 1998
Pre-Optimized Functions optimized functions benchmark measures design performance using large, pre-optimized functions that were chosen because they commonly implemented PLDs. following functions were used:
Finite impulse response (FIR) filter (8-bit 16-tap) multiplier Master/target peripheral component interconnect (PCI) function Viterbi decoder
Because these designs were pre-optimized each vendor, results eliminate performance variability associated with design methodology design tool efficiency. Consequently, benchmark results excellent tool comparing silicon performance comparable PLDs from different vendors. Additionally, these benchmarks show best-case performance designs similar structure size devices analyzed. Memory memory benchmark measures design performances implemented PLDs. Different sizes (i.e., width depth) structures (i.e., single port dual port) were tested. This benchmark measured maximum interface performance RAM. Performance performance benchmark analyzes input setup hold times, output clock-to-output times. This benchmark important determining whether device will meet critical system design parameters.
order help designers with system performance estimation process, Altera will present results through series technical documents that downloaded from Altera site http://www.altera.com. more information about benchmarks measuring design performance, contact Altera Applications (800) 800-EPLD.
Altera News
Altera News
FLEX 6000 Devices Compete Sucessfully with ASICs
FLEX® 6000 devices combine traditional programmable logic device (PLD) benefits fast time-to-market flexibility with exceptionally cost high-volume applications. Since FLEX 6000 devices were introduced June 1997, these devices have successfully been used logical alternatives application-specific integrated circuits (ASICs). Cornet, Inc. such company that switched successfully FLEX 6000 devices. Cornet high-speed switch manufacturing leader, providing solutions traffic control systems, data centers, LAN/WAN management, applications requiring high-speed data handling. FLEX 6000 Devices Used Prototyping Before FLEX 6000 devices were introduced, Cornet used PLDs prototyping ASICs high-volume production. With help local distributor, Wyle Electronics, Inc., Cornet started using FLEX 6000 devices their switch product several corresponding special function cards. Cornet also used FLEX 6000 device upgrade functionality their older switch products, allowing existing customers features their needs grow. FLEX 6000 Devices Provide Flexibility Because FLEX 6000 devices reprogrammable, they provide more flexibility than ASICs. According Crews, Cornet Engineer, "The EPF6016 device design criteria well, were able design EPF6016TC144-3 device into different boards port switches. used ASIC, would have different devices; with Altera, only needed purchase added benefit reprogrammability." Cost-Competitive FLEX 6000 Devices Cornet quickly discovered that using costcompetitive FLEX 6000 devices production, they could still reduce usage cost during prototyping obtain added benefits fast time-to-market flexibility during high-volume production. FLEX 6000 devices cost-competitive with gate arrays because their sizes similar. Figure
Figure Relative Size Comparison
1.06
Gate Array Pins
FLEX 6000 Pins
Although Cornet satisfied with using ASICs high-volume production, they decided switch FLEX 6000 devices because they were directly cost competitive with ASICs. Even though their ASIC vendor quotes very aggressive prices ASICs, Cornet still considered FLEX 6000 devices more logical solution. Kumar, president Cornet, stated, appreciate benefits reprogrammability need keep costs low. gave [Altera] very aggressive price comparable that ASIC. surprise, they came back price!" Altera able offer low-cost solution with added benefits reprogrammability. Cornet plans purchase thousands FLEX 6000 devices over next several months. Annual usage will increase over next years Cornet expands product offerings redesigns older products. This type response confirms that FLEX 6000 family viable alterative ASICs high-volume production. Conclusion Because FLEX 6000 devices offer comparable cost density ASICs plus benefits reprogrammability, they being used both prototyping high-volume production. FLEX 6000 devices continue ideal reprogrammable alternative ASICs. more details about Cornet, Inc. their high-speed switching solutions, Cornet site http://www.cornet.com. more information FLEX 6000 devices, contact Altera Applications (800) 800-EPLD Altera site http://www.altera.com.
Altera Corporation News Views 1998
Altera News
Language Hardware Support
growing number programming hardware vendors support JamProgramming Test Language, industry-standard interpreted language. language vendor- platformindependent optimized in-system programmability (ISP)-capable devices IEEE Std. 1149.1 (JTAG) interface. most recent vendors announce language hardware support Hi-Lo System Research (also known Tribal Microsystems United States) Xeltek Corporation. This article describes each vendor's universal programmer support language. Hi-Lo System Research: ALL-11 Universal Programmer ALL-11 universal programmer sixth-generation universal programmer product from Hi-Lo System Research. ALL-11 programmer supports over Altera® MAX® 9000A 7000S devices. programmer consists universal base exchangeable pack options. These packs range from general purpose multiple sockets multi-device programming. ALL-11 programmer offers following features:
Xeltek Corporation: Superpro Universal Programmer Xeltek recently introduced Superpro universal programmer, low-cost programmer that supports more than 4,000 devices. Superpro offers following features:
Supports Files created MAX+PLUS software Supports devices instantly they become available from manufacturers universal drivers Dual-range switching power supply adapter V/240 Optional 100-pin expansion module Optional universal socket multi-device adapters various device packages Printer port interface Windows MS-DOS user interface Parallel port Large variety socket adapters available most device packages
Table shows Altera ISP-capable devices that currently supported Superpro programmer.
Table ISP-Capable Devices Supported Superpro
Family
9000 7000S
Device
EPM9400 EPM9320 EPM7032S EPM7160S EPM7128S EPM7256S EPM7064S
Supports Files (.jam) created MAX+PLUS® software Supports devices instantly they become available from programmable logic device (PLD) manufacturers Supports 300-pin devices drivers fully programmable High-speed expandable memory buffer (from Mbit Mbytes) High-speed serial port interface kbyte baud) port interface (optional) Windows MS-DOS user interface Free software updates bulletin board service (BBS) site
Conclusion addition full support Altera devices, ALL-11 Superpro programmers support vendors' devices that programmed with Files. more information hardware support language from Hi-Lo, Xeltek, other third-party programmer vendors, site http://www.jamisp.com.
Altera Corporation
News Views
1998
Altera News
Tools Supported through ACCESS Program
Altera® Commitment Cooperative Engineering Solutions (ACCESSSM) program alliance between Altera vendors that provides direct support Altera programmable logic devices (PLDs) integration with Altera's MAX+PLUS® development software. ongoing effort simplify seamlesss design flow between MAX+PLUS software other tools, Altera developed MAX+PLUS ACCESS Guidelines, which provide complete instructions create, compile, simulate your design with tools from leading vendors such Cadence, Exemplar Logic, Mentor Graphics, Synplicity, Synopsys, Viewlogic, MAX+PLUS software. guidelines found
addition guidelines, Altera recently introduced first ACCESS PROGRAM several technical briefs that demonstrate ease with which designers interface their existing tools with MAX+PLUS software. These technical briefs provide steps setting environment generating necessary files simple design target Altera devices. Available technical briefs include:
Altera site http://www.altera.com MAX+PLUS CD-ROM (version higher)
guidelines organized vendor, tool, functionality make easy find information need quickly. MAX+PLUS ACCESS Guidelines part Altera's ongoing plan give designers state-of-the-art tools that enhance productivity even highest-density devices.
Technical Brief (Using Synopsys Design Compiler FPGA Compiler Synthesize Designs MAX+PLUS Software) Technical Brief (Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software) Technical Brief (Using Synplicity Synplify Software Synthesize Designs MAX+PLUS Software) Technical Brief (Importing Synthesized Files from Software into MAX+PLUS Software)
obtain these documents from following sources:
Altera Literature Services (888) 3-ALTERA Altera site http://www.altera.com Your local Altera sales representative
Altera European Technical Center
March 1998, Altera announced establishment first European Technical Center. role center
enabling staff stay constant contact with Altera personnel worldwide. center will employ many engineers next years. addition research development center United Kingdom existing research development operations Penang, Malaysia, Altera headquarters Jose, California, advances Altera's fulfillment ongoing research development worldwide. more information about Altera European Technical Center, Altera site http://www.altera.com.
Provide locally based technical support Altera® European hardware software customers Execute research development activities focused device design development MegaCoremegafunctions MegaWizardPlug-Ins
European Technical Center will housed Altera's current facility outside London, already equipped with videoconferencing,
Altera Corporation
News Views
1998
Altera News
AMPP Megafunctions
your digital signal processing (DSP), telecommunications, ALTERA MEGAFUNCTION PARTNERS PROGRAM interface design needs, Altera introduced three Altera Megafunction Partners Program (AMPP) partners several megafunctions. These megafunctions, targeted specific Altera device architectures, allow focus proprietary sections your overall design. megafunctions optimized AMPP partner then verified Altera.
functional emulation verification Simple Silicon megafunctions performed using Altera FLEX® devices. pricing information prototyping boards, contact Simple Silicon directly Simple Silicon, Inc. 10430 South Anza Blvd, Suite Cupertino, 95014. Phone: (408) 873-2260 Fax: (408) 873-2261 E-mail: info@simplesi.com http://www.simplesi.com NComm, Inc. NComm, Inc. enters AMPP program with years experience designing programmable logic telecommunications applications. NComm already implemented Altera MegaWizardPlug-Ins, developed parameterized tone generation megafunction called ToneGen. encrypted evaluation copy ToneGen megafunction, enabled OpenCore feature, available contacting NComm NComm, Inc. Main Street, Suite Salem, 03079 Telephone: (603) 893-6186 Fax: (603) 893-6534 E-mail: info@ncomm.com http://www.ncomm.com Conclusion Up-to-date information AMPP program, including partner profiles megafunction descriptions, available AMPP Catalog version Altera's site http://www.altera.com.
evaluate megafunctions prior purchasing license using OpenCoreevaluation feature Altera MAX+PLUS® software. OpenCore feature allows compile megafunctions determine megafunction's size speed. generate programming files, must license function. HammerCores HammerCores, AMPP partner, currently offers following high-performance, user-parameterizable megafunctions applications:
Reed-Solomon Encoder/Decoder Cordic Cordpol Function Ultra-Fast Reed-Solomon Coder Zero-Forcing Equalizers Embedded Processor FlexCore
HammerCores megafunctions available OpenCore evaluation HammerCores site http://www.hammercores.com. Simple Silicon Simple Silicon provides leading-edge digital connectivity solutions networking, consumer electronics, computing, audio, video, mass storage devices. Simple Silicon provides proven expertise IEEE Std. 1394 physical link layer controllers, offers following megafunctions:
Si-Link: IEEE Std. 1394 Link Layer Controller Si-Phy: IEEE Std. 1394 Physical Layer Controller Si-Hub: Controller Si-Function: Function Controller Si-Enable USB-86: Host Controller
Altera Corporation
News Views
1998
Every
Third-Party Programming Support
Data Microsystems provide programming hardware support selected Altera devices. Algorithms supplied Data I/O's Keep Current Express-Bulletin Board Service (KCE-BBS) Microsystems' BBS. Programming support Configuration EPROM, MAX® 9000A, 7000 devices shown table below. information subject change.
Third-Party Programming Hardware Support
Device
EPC1064 EPC1213 EPC1 EPC1441 EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7128A EPM7160E EPM7192E EPM7192S EPM7256E EPM7256S EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
Altera Publications
publications available from Altera Literature Services. Individual documents available Altera's world-wide site http://www.altera.com. Document part numbers shown parentheses.
AMPP Catalog (A-CAT-AMPP-03) FLEX 10KE Embedded Programmable Logic Family Data Sheet (A-DS-F10KE-01) FLEX Embedded Programmable Logic Family Data Sheet Supplement (A-DSS-F10K-03.1) ByteBlasterMV Parallel Port Download Cable Data Sheet (A-DS-BYTBLMV-01) Technical Brief Using Synopsys Design Compiler FPGA Compiler Synthesize Designs MAX+PLUS Software (M-TB-039-01) Technical Brief Advantages MAX+PLUS Fitting (M-TB-040-01) Technical Brief Power Measurements: FLEX 10KA XC4000 Devices (M-TB-041-01) Technical Brief Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software (M-TB-042-01) Technical Brief Using Synplicity Synplify Software Synthesize Designs MAX+PLUS Software (M-TB-044-01) Technical Brief Importing Synthesized Files from Software into MAX+PLUS Software (M-TB-045-01)
Data
Microsystems
Notes: These devices supported Data 3900 version UniSite version programmers. These devices supported Microsystems programmers version 3.31. This device will supported Data 3900 version Microsystems programmers version 3.36 July 1998. Earlier programming support available sooner than scheduled release date.
Current Software Version
latest version Altera software product shown below: MAX+PLUS® version (PC, SPARCstation, 9000 Series 700/800, RISC System/6000 platforms)
Altera Corporation News Views 1998
Every Issue
Programming Hardware Support
Table contains latest programming hardware information Altera devices. correct programming, software version shown "Current Software Version" page
Table Altera Programming Adapters (Part Note
Device
EPC1064 (2), EPC1064V (2), EPC1441 EPC1 EPC1213, EPM9320A
Table Altera Programming Adapters (Part Note
Device
EPM7128, EPM7128E
Package
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
Adapter
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMQ7128/7160-160NC
EPM7160S
J-lead PQFP (100-pin) PQFP (160-pin)
Package
DIP, J-lead TQFP J-lead J-lead (84-pin) RQFP (208-pin) RQFP (240-pin)
Adapter
EPM7160E J-lead PQFP (100-pin) PQFP (160-pin) EPM7192S EPM7192E EPM7256S EPM7256E PQFP (160-pin) (160-pin) PQFP (160-pin) RQFP (208-pin) PQFP (160-pin) (192-pin) RQFP (208-pin) EPM7256A PQFP (208-pin) TQFP (144-pin)
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMQ7192/256-160NC PLMG7192-160 PLMQ7192/7256-160 PLMQ7256-208NC PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMR7256-208 PLMT7000-144NC
PLMJ1213 PLMT1064 PLMJ1213 PLMJ1213 PLMJ9320-84 PLMR9000-208NC PLMR9000-240NC PLMG9000-280 PLMJ9320-84 PLMR9000-208 PLMJ9400-84 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMR9000-208NC PLMR9000-240NC PLMG9000-280 PLMR9000-208 PLMR9000-240 PLMR9000-304 PLMJ7000-44 PLMT7000-44
PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44 PLMT7000-100NC PLMJ7000-4 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-84 PLMQ7000-100NC PLMT7000-100NC PLMT 7000-144NC PLMQ7128/160-160NC PLMJ7000-84 PLMT7000-100NC PLMT 7000-144NC
EPM9320
J-lead (84-pin) RQFP (208-pin)
EPM9400
J-lead (84-pin) RQFP (208-pin) RQFP (240-pin)
EPM9480
RQFP (208-pin) RQFP (240-pin)
EPM9560A
RQFP (208-pin) RQFP (240-pin)
EPM9560
(280-pin) RQFP (208-pin) RQFP (240-pin) RQFP (304-pin)
Notes: Refer Altera 1998 Data Book device adapter information 5000 Classic devices. Altera offers adapter exchange program 0.8-micron EPM5032, EPM5064, EPM5130 programming adapters. FLEX 8000 Configuration EPROM. FLEX 10K, FLEX 8000, FLEX 6000 Configuration EPROM. These devices shipped carriers.
EPM7032S
EPM7032, EPM7032V
J-lead (44-pin) TQFP (44-pin)
J-lead (44-pin) PQFP (44-pin) TQFP (44-pin)
Table shows provides programming configuration compatibility information BitBlasterserial port, ByteBlasterparallel port, ByteBlasterMVparallel port download cables.
Table BitBlaster ByteBlaster Cable Compatibility
Device
FLEX FLEX 10KA FLEX 10KE FLEX 8000 FLEX 6000 9000 9000A 7000S 7000A
EPM7064S
J-lead (44-pin) TQFP (44-pin) TQFP (100-pin)
BitBlaster
ByteBlaster
ByteBlasterMV
EPM7064
J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
EPM7096
J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
EPM7128S
J-lead (84-pin) PQFP (100-pin) TQFP (100-pin) TQFP (144-pin) PQFP (160-pin)
EPM7128A
J-lead (84-pin) TQFP (100-pin) TQFP (144-pin)
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Altera Device Selection Guide
current information Altera FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices listed here. Information other Altera devices located Altera 1998 Data Book. most up-to-date information about Altera products, Altera site http://www.altera.com. Contact Altera your local sales office current product availability.
FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A
GATES
10,000 10,000 20,000 30,000 30,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin RQFP, 240-Pin PQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-pin BGA1, 356-Pin BGA, 484-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 256-pin BGA1, 484-pin BGA1 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1, 484-Pin BGA1
PINS
102, 662, 102, 134, 1502 102, 147, 147, 189, 102, 147, 189, 1912, 246, 2462 102, 147, 1762, 2202 147, 189, 274, 189, 274, 3102 102, 147, 189, 1912, 2562 189, 189, 274, 3712, 147, 189, 1912 147, 189, 1912, 3402 470, 186, 3712, 4262 182, 470, 4702 470, 179, 470, 4702
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728
BITS
6,144 6,144 12,288 12,288 12,288
EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E
30,000 40,000 50,000 50,000 50,000
1,728 2,304 2,880 2,880 2,880
24,576 16,384 20,480 20,480 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E EPF10K130V EPF10K130E EPF10K200E EPF10K250A EPF10K250E
70,000 100,000 100,000 100,000 100,000 130,000 130,000 200,000 250,000 250,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1, 600-pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA1 208-Pin PQFP, 240-Pin PQFP, 256-pin BGA1, 484-pin BGA1 599-Pin PGA, 600-Pin 240-Pin PQFP, 484-Pin BGA1, 672-Pin BGA1 240-Pin RQFP, 599-Pin PGA, 672-pin BGA1 599-Pin PGA, 600-Pin 240-Pin RQFP, 599-Pin PGA, 672-Pin BGA1
3,744 4,992 4,992 4,992 4,992 6,656 6,656 9,984 12,160 12,160
18,432 24,576 24,576 24,576 49,152 32,768 65,536 98,304 40,960 81,920
Notes: This package space-saving FineLine package. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
FLEX 8000 Devices
DEVICE
EPF8282A EPF8282AV EPF8452A EPF8452A EPF8636A EPF8636A EPF8820A EPF8820A EPF81188A EPF81500A
GATES
2,500 2,500 4,000 4,000 6,000 6,000 8,000 8,000 12,000 16,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 100-Pin TQFP 100-Pin TQFP 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
PINS
118, 112, 120, 112, 120, 148, 181,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,188 1,500
LOGIC ELEMENTS
1,008 1,296
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FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A EPF6024A
GATES
10,000 16,000 16,000 24,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin BGA1
PINS
117, 171, 199, 117, 171, 2182 117, 171, 199, 218, 2182
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320 1,960
LOGIC ELEMENTS
1,320 1,320 1,960
Notes: This package space-saving FineLine package. This data preliminary. most up-to-date information, contact Altera Applications (800) 800-EPLD.
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480A EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-10, -15, -15, -10, -15, -10, -15,
7000 Devices
DEVICE MACROCELLS PIN/PACKAGE OPTIONS PINS SUPPLY VOLTAGE
SPEED GRADE
EPM7032A EPM7032S EPM7032 EPM7032V EPM7064A EPM7064S EPM7064 EPM7096 EPM7128A EPM7128S EPM7128E EPM7160S EPM7160E EPM7192S EPM7192E EPM7256A EPM7256S EPM7256E EPM7384A EPM7512A EPM71024A
1,024
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP/PQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin BGA1 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin PQFP/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP/PGA 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 208-Pin RQFP/PQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 208-Pin PQFP, 256-Pin BGA1
100, 120, 164, 132, 132, 120, 176, 120, 176, 176,
-10, -12, -12, -15, -10, -12, -10, -12, -10, -10, -12, -15, -10, -10, -12, -15, -10, -12, -15, -10, -12, -15, -10, -10, -10,
Note: This package space-saving FineLine package.
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Information Type
Literature
Access
Altera Literature Services World-Wide
U.S. Canada
(888) 3-ALTERA lit_req@altera.com http://www.altera.com (800) SOS-EPLD (408) 544-6403 (800) 800-EPLD (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Other Locations
(408) 544-7144 lit_req@altera.com http://www.altera.com (408) 544-7000 (408) 544-6403 (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Non-Technical Customer Service Technical Support
Telephone Hotline Telephone Hotline a.m. p.m. Pacific Time) Electronic Mail Site
General Product Information
Telephone World-Wide
Notes:
MAX+PLUS Getting Started Manual available from Altera site. obtain other MAX+PLUS software manuals, contact Altera Customer Service your local distributor. also contact your local Altera sales office sales representative. Altera site listing.
Toll-Free Number Renewing Software Maintenance
Software maintenance ensures that always receive most up-to-date version MAX+PLUS software. should renew your software maintenance each year continue latest software. When your maintenance about expire, Altera will mail notification with renewal quote. make easier renew your software maintenance agreement, Altera dedicated support line North American customers. renew your maintenance, simply call (888) 800-0631; this number highlighted maintenance quotes North American customers. Customers outside North America should continue work with their existing sales representative.
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