FLEX 10K-1 FLEX 10K-2 devices faster system speeds existing members hi

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

FLEX 10K-1 FLEX 10K-2 devices faster system speeds existing members hi

Datasheet Thumbnail

Top Searches for this datasheet

Faster FLEX DeviceTo meet increasing performance requirements system designers, Altera recently unveiled plans next generation programmable logic. Altera introduced additions FLEX® family:
FLEX 10K-1 FLEX 10K-2 devices faster system speeds existing members highdensity FLEX family. FLEX 10KB devices offer high-density, highperformance devices-based 0.25-micron, 5-layer-metal process-at lower cost.
performance FLEX devices. migrating from 0.5-micron, three-layer-metal process 0.35-micron, fourlayer-metal process, Altera offer 3.3-V-based FLEX 10KA devices. This process improvement smaller size translate directly increased performance lower cost. FLEX devices outperform competing fieldprogrammable gate arrays (FPGAs) similar density. recent comparison, Altera® Applications implemented customer designs into FLEX 10K-2 device, FLEX 10K-1 device, competing FPGA device comparable density. Figure Design
These devices provide low-cost solution your high-density, high-performance programmable logic needs. Breakthrough Performance
Process improvements combined with enhancements continued page MAX+PLUS® software have resulted performance Figure Altera FPGA Performance increases FLEX 10K-2 devices (see Table page faster FLEX 10K-1 devices provide over 100% performance improvements. performance increases respond directly market demand faster devices. With these increases, these Performance devices applications that (MHz) experiencing rapid increase performance requirements, such 100-Mbit 1-Gbit Ethernet communications designs.
EPF10K50V-1, Note EPF10K50V-2, Note Competing FPGA, Note
Advanced Process Increases Speed
Altera worked closely with long-standing partner, TSMC, improve size
Design
Notes: Performance numbers estimated upcomiong release MAX+PLUS version software. Performance numbers derived using MAX+PLUS version software. These designs were compiled with software from competing FPGA vendor.
A-NV-Q497-01
Altera Corporation
News View
December 1997
ContentFeatures Faster FLEX Devices Altera Viewpoint: Achieving Performance Goals Customer Application: Success with Language Altera News Altera Forms Design Consultants Alliance Altera ICSPAT World Expo Altera Target Applications Altera World Devices Tools EPF10K100A Devices Available EPF10K250A Coming First Quarter 1998 FLEX 6000 Device Availability EPC1441 Device: Low-Cost Configuration EPROM 9000 Update Support Strategy Faster 7000S Speed Grade Devices 7000A Family 7000 Product Transitions 5000 Classic Product Transitions Microperipheral MegaCore Library: Cost-Effective Alternative
MAX+PLUS Version Limited Time Offer Altera Tools Synthesis Support Entry-Level Software Discontinued Support Windows Windows Workgroups Discontinued Devices
Technical Articles Configuring FLEX 10KA Devices Using Language Configure FLEX FLEX 10KA Devices Implementing Counter Using One-Hot Shift Register Questions Answers Tips Boost Registered Performance Every Issue Altera Publications Third-Party Programming Support Current Software Versions Altera Programming Hardware Support Altera Device Selection Guide Access Altera Response Form
information about this newsletter, submit questions, contact: Erica Heidinger, Publisher Craig Lytle, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 E-mail: n_v@altera.com
Printed recycled paper.
Altera, ACAP, AMPP, Atlas, BitBlaster, ByteBlaster, Classic, ClockLock, ClockBoost, FastFLEX, FastTrack, FLASHlogic, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KB, FLEX 8000, FLEX 6000, FLEX DSP, µPitch, 9000, 7000, 7000E, 7000S, 7000A, 5000, MAX, MAX+PLUS, MAX+PLUS MegaCore, MultiVolt, OpenCore, OptiFLEX, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: SuperBGA registered trademark Amkor/Anam. Verilog registered trademark Cadence Design Systems. Data registered trademark Data Corporation. registered trademark International Business Machines Corporation. Synopsys registered trademark Synopsys, Inc. Viewlogic registered trademark Viewlogic Systems. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1997 Altera Corporation. rights reserved.
Altera Corporation
News View
December 1997
Features Faster FLEX Devices continued from page compiled with MAX+PLUS software achieved higher performance compared designs compiled with software from competing FPGA vendor. addition, FLEX 10K-2 FLEX 10K-1 devices achieved higher average performance:
FLEX 10K-2 devices averaged 38.36 MHz. FLEX 10K-1 devices averaged 47.95 MHz. competing FPGA averaged only 26.44 MHz.
FLEX 10K-1 FLEX 10K-2 devices operate 3.3-V 5.0-V core voltage offer MultiVoltI/O interface option, which allows these devices interface with 2.5-V, 3.3-V, 5.0-V devices. These devices offer densities 130,000 gates available variety package options. FLEX 10K-1 FLEX 10K-2 devices available have "-1" "-2, respectively, appended their device ordering codes (for example, EPF10K100ARC240-1). Altera also shipping speed grade versions these devices. Contact Altera Marketing more information.
Improvements MAX+PLUS development system have made significant contribution overall performance increase FLEX 10K-1 FLEX 10K-2 devices. Better optimization routing algorithm improvements have resulted improvement compilation times MAX+PLUS software. With most compilation times under averaging minutes, implement changes test results quickly. Moreover, according benchmark tests performed Altera Applications, MAX+PLUS software compiles designs consistently faster than other programmable logic development tool. giving quick feedback utilization performance your design, MAX+PLUS software helps bring your product market faster. addition, with MAX+PLUS version 8.1, designers with current software maintenance agreement receive upgrades well free hardware description language (HDL) synthesis-VHDL Verilog HDL. more information, "MAX+PLUS Version 8.1" page High-Performance, Low-Cost FLEX 10KB Devices FLEX 10KB devices will bring higher performance lower cost programmable logic. Implemented 0.25-micron, five-layer metal process, FLEX 10KB devices offer lower costs, 75-MHz in-system performance, densities 250,000 gates. FLEX 10KB devices have 2.5-V core voltage, resulting reduction power consumption compared 5.0-V FLEX devices. Further, with MultiVolt feature, these devices interface with 2.5-V, 3.3-V, continued page
MAX+PLUS Software ImprovementThe MAX+PLUS software offers architectureindependent development environment, enabling designers customize their designs target device family. software also provides seamless integration with leading tools, such tools from Cadence, Exemplar Logic, Mentor Graphics, Synplicity, Synopsys, Viewlogic, allowing designers their preferred design entry methodology.
Table FLEX Performance ImprovementDevice
EPF10K30A EPF10K50V EPF10K50V EPF10K70 EPF10K100A EPF10K100A EPF10K130V
Speed Grade
Gate30,000 50,000 50,000 70,000 100,000 100,000 130,000
Logic Element1,728 2,880 2,880 3,744 4,992 4,992 6,656
Embedded
Kbits Kbits Kbits Kbits Kbits Kbits Kbit
Performance Improvement
40%, Note 110%, Note 40%, Note 22%, Note 107%, Note 35%, Note 38%, Note
Supply Voltage
Notes: Estimated performance with speed grade using MAX+PLUS version compared speed grade using MAX+PLUS version 8.0. Estimated performance with speed grade using upcoming release MAX+PLUS version compared speed grade using MAX+PLUS version 8.0.
Altera Corporation News Views December 1997
Features Faster FLEX Devices continued from page 5.0-V devices. These devices provide fast time-to-market unprecedented performance levels cost broad range system-level designs. FLEX 10KB process migration provides performance improvement over existing FLEX devices, enabling programmable logic support system performance MHz. Figure addition higher performance, process migration also provides lower cost. metal-intensive FLEX architecture efficiently maps metal interconnect additional process metal layers, allowing Altera offer smaller sizes lower cost. Altera plans begin shipping FLEX 10KB devices second quarter 1998. Table shows sample projected volume pricing FLEX 10KB devices. Table summarizes FLEX 10KB device features.
Table FLEX 10KB FeatureFeature
Typical gates Logic elements bits Package option
Figure Sample FLEX 10KB Performance
Performance (MHz)
EPF10K100 EPF10K100A
8-Bit 512-Point
EPF10K100B 4-Stage Pipelined Multiplier 16-Bit, Up/Down Loadable Counter
Design
Table Sample FLEX 10KB Volume Price ProjectionDevice
EPF10K30B EPF10K50B EPF10K100B
Gate30,000 50,000 100,000
Package
144-Pin TQFP 208-Pin PQFP 208-Pin PQFP
Price Note
$8.00 $10.00 $20.00
Note: Projected 50,000-unit volume pricing second half 1999 (North American direct, slowest speed grade).
EPF10K30B
30,000 1,728 12,288 144-pin TQFP 208-pin 240-pin 356-pin
EPF10K50B
50,000 2,880 20,480 208-pin 240-pin 356-pin Second half 1998
EPF10K100B
100,000 4,992 24,576 208-pin 240-pin 356-pin 600-pin Second quarter 1998
EPF10K130B
130,000 6,656 32,768 240-pin 356-pin 599-pin 600-pin Second half 1998
EPF10K180B
180,000 9,728 32,768 240-pin 356-pin 600-pin Second half 1998
EPF10K250B
250,000 12,160 40,960 356-pin 599-pin 600-pin Second half 1998
Maximum user pins Availability
Second half 1998
Altera Corporation
News View
December 1997
DeviceEPF10K100A Devices Available
&TOOLS
FLEX Update
Table FLEX 6000 Availability
Device
EPF6016
Package
144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin
Speed Grade-2,
Availability
1998 1998 1998 1998 1998 1998 1998
November 1997, Altera began shipping EPF10K100A devices 240-pin power quad flat pack (RQFP) packages. Altera plans ship 356-pin ball-grid array (BGA) packages December 1997 600-pin packages first quarter 1998. Built 0.35-mm, quad-layer metal process, EPF10K100A devices pin-compatible with FLEX devices 240-pin RQFP 356-pin packages. instance, migrate from 3.3-V EPF10K50V devices higher-density EPF10K100A devices without changing your board layout. 100,000-gate EPF10K100ARC240-3 devices priced $165 each 100-unit quantities. EPF10K100ARC240-2 EPF10K100ARC240-1 also available; contact your local Altera representative pricing information. EPF10K250A Coming First Quarter 1998 Altera plans make initial shipments 250,000gate EPF10K250A devices March 1998. With 12,160 logic elements embedded array blocks (40,960 memory bits), EPF10K250A will largest programmable logic device available. EPF10K250A devices expected available 599-pin ceramic pin-grid-array (PGA) 600-pin ballgrid array (BGA) packages. will also pincompatible with other FLEX devices 599-pin 600-pin packages. FLEX 6000 Device Availability FLEX® 6000 programmable logic device (PLD) family provides low-cost alternative high-volume gate array designs industry's most costeffective family. FLEX 6000 family offers extensive package options, including 144-pin thin quad flat pack (TQFP), 208- 240-pin plastic quad flat pack (PQFP), 256-pin ball-grid array (BGA) packages. Table describes package options, speed grades, availability each FLEX 6000 device.
EPF6016A
144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin
EPF6024A
208-pin PQFP 240-pin PQFP 256-pin
Configuration EPROM Update
EPC1441 Device: Low-Cost Configuration EPROM EPC1441 device-the newest Configuration EPROM device Altera® serial EPROM family-is most cost-effective serial Configuration EPROM industry. EPC1441 devices have density Kbits offer 3.3- 5.0-V operation. single EPC1441 device configure FLEX devices 30,000 gates, including:
FLEX 6000 devices FLEX 8000 devices EPF10K10, EPF10K20, EPF10K30 FLEX device
EPC1441 devices available 8-pin plastic dual inline (PDIP), 20-pin plastic J-lead chip carrier (PLCC), 32-pin thin quad flat pack (TQFP) packages. EPC1441 devices cost $3.50 each 100-unit quantities. more information EPC1441 devices other Altera Configuration EPROMs, Configuration EPROMs FLEX Devices Data Sheet
Update
9000 Update Altera performing process migration MAX® 9000 devices. devices will fabricated continued page
Altera Corporation
News View
December 1997
Devices Tools Devices Tools, continued from page 0.5-micron, triple-layer-metal process. With propagation delays fast 9000A devices offer significant performance enhancement over existing 9000 devices. Production quantities high-performance 9000A devices will available beginning January 1998; samples 10-ns EPM9560A devices available now. Table shows 9000 device availability.
Table 9000 Device Availability
Device
EPM9320A EPM9480A EPM9560A
devices available speed grades, respectively. Table shows speed grades availability 7000S devices.
Table 7000S Device Availability
Device
EPM7032S EPM7064S
Package
44-pin PLCC 44-pin TQFP 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
Speed Grade
-10, -10,
Availability
March 1998 March 1998 December 1997 1998
(ns)
Availability
February 1998 Second Half 1998 January 1998
84-Pin 208-Pin 240-Pin 356-Pin PLCC RQFP RQFP
EPM7128S
84-pin PLCC 100-pin TQFP
100-pin PQFP -10, 160-pin PQFP -10, EPM7160S 160-pin PQFP -10, 160-pin PQFP -10, 208-pin PQFP -10,
EPM7192S EPM7256S
Support Strategy 7000A Family Devices that support in-system programmability (ISP), such 9000 7000S devices, programmed during final printed circuit board (PCB) testing stage using automated test equipment (ATE). This programming method offers ability combine device programming with board-level test methods. program using ATE, designers must fixed-algorithm devices, which have ordering code ending (e.g., EPM9560RC208-15F). Both 9000 7000S fixed-algorithm devices available today. Faster 7000S Speed Grade Devices macrocell count, 7000S family fastest product-term-based programmable logic device (PLD) family world. 7000S family offers even faster performance with devices fast EPM7064S shipping with 5-ns speed grade. EPM7128S EPM7256S
Table 7000A Device Availability
Device
EPM7032A EPM7064A EPM7128A EPM7256A EPM7384A EPM7512A EPM71024A
7000A device family (formerly known Michelangelo), which supports 3.3-V in-system programmability (ISP), will begin shipping March 1998. Manufactured 0.35-micron, quad-layer-metal EEPROM process, 7000A devices pincompatible with 7000S devices have MultiVoltI/O feature, enabling these devices interface with 5.0-V, 3.3-V, 2.5-V devices. Table summarizes 7000A device availability. 7000 Product Transitions Altera migrating existing 7000 devices from 0.65-micron process 0.5-micron process. Evaluation packets containing sample devices documentation available from your local Altera sales representative. Table page outlines process migration schedule.
(ns)
Availability
Second half 1998 Second half 1998 March 1998 Second quarter 1998 1999 Second half 1998 1999
44-Pin PLCC
44-Pin TQFP
84-Pin PLCC
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin
December 1997
Altera Corporation
News View
Devices Tool
Table 7000 Migration Schedule
Device
EPM7064 EPM7064S EPM7128E EPM7128S EPM7192E EPM7192S EPM7256S EPM7256E
Note
Proces0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron
MAX+PLUS UpdateMicroperipheral MegaCore Library: Cost-Effective Alternative Designing with existing intellectual property just became much more cost-effective. Instead licensing entire library functions, Altera microperipheral MegaCorefunctions licensed individually downloaded directly from Altera world-wide site http://www.altera.com. Contact your local Altera sales representative license following MegaCore functions (ordering codes shown parentheses):
Reference
Date
Complete Complete January 1998 Complete February 1998 Complete
Note
PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9708
Notes: This process transition will result changes data sheet parameters ordering codes. Altera provides advisories process change notices. Altera world-wide site http://www.altera.com these reference documents.
5000 Classic Product Transitions Altera's migration 5000 Classicdevices 0.65-micron process complete. Table more details.
Table 5000 Classic Product Migration Schedule
Description
5000 devices fabricated 0.65-micron proces
Reference
9407 9515 9606
Device
EPM5032 EPM5064 EPM5128 EPM5130 EPM5192
a8237 programmable controller (PLSM-8237) a8251 programmable communications interface (PLSM-8251) a8255 programmable peripheral interface adapter (PLSM-8255) a6402 universal asynchronous receiver/ transmitter (PLSM-6402) a16450 universal asynchronous receiver/ transmitter (PLSM-16450) a6850 asynchronous communications interface adapter (PLSM-6850) a8259 programmable interrupt controller (PLSM-8259)
MAX+PLUS Version Altera® MAX+PLUS® software, most powerful programmable logic development system industry, regularly updated ensure state-ofthe-art support Altera device families. Altera maintenance program allows automatically benefit from Altera's ongoing product development. With current software maintenance agreement, receive support latest Altera devices well software features, performance enhancements, up-to-date online documentation. Altera recently added variety features MAX+PLUS version 8.1, such synthesis options improved compilation times, help more productive create more successful designs. example, Altera offers synthesis additional cost. Starting with MAX+PLUS version 8.1, VHDL Verilog synthesis continued page
Note
Classic devices fabricated 0.65-micron process 9510 9607 9621
EP6xx EP9xx EP18xx
Notes: Data sheet parameters ordering codes will change. Altera world-wide site advisories process change notices. Devices manufactured 0.65-micron process must programmed with programming adapters.
Altera Corporation
News View
December 1997
Devices Tools Devices Tools, continued from page available standard feature designers with current software maintenance agreement. VHDL synthesis available MAX+PLUS version 8.1. have current maintenance agreement, enable synthesis support obtaining authorization code from Altera world-wide (WWW) site http://www.altera.com/authcode. Verilog synthesis will available MAX+PLUS version will only available 32-bit operating systems, such Windows Windows UNIX. download authorization code Verilog today, Altera will send software soon available. Table shows free feature upgrades standard features available MAX+PLUS version 8.1. Limited-Time Offer Altera Tools Altera offering world-wide tools promotion Site License users MAX+PLUS design-site more information worldwide tools promotion, contact your local Altera distributor. users without current maintenance agreement. promotion continues through December 1997. When upgrade your software, will receive following features:
Four quarterly upgrades choice VHDL Verilog synthesis Functional simulation (for PLS-BASE) Extended features device support Altera devices (for PLS-MAGNUM)
Site License users-You will receive large discounts when upgrade either PLS-BASE PLS-MAGNUM design site with year software maintenance. Existing MAX+PLUS users without current maintenance agreement-You will receive software features when purchase maintenance, depending your existing design site. Table
Table Upgrade MAX+PLUS Version Receive These FeatureIf have.
PLS-ES, PLS-ADV, PLS-STD PLS-ES, PLS-ADV, PLS-STD (with migration product) PLS-ES, PLS-ADV, PLS-STD (with more than migration product), Note PLS-FLEX8 (with migration products) PLS-FLEX8 (with migration product) Note PLS-MAGNUM PLS-HPS, Note
upgrade
PLS-BASE PLS-BASE your existing migration product PLS-MAGNUM
receive these standard features.
VHDL Verilog synthesis Functional simulation VHDL Verilog synthesis Functional simulation VHDL Verilog synthesis Support FLEX 6000, FLEX 10K, FLEX 8000,
9000 device families PLS-BASE PLSM-6K/8K PLS-MAGNUM
VHDL Verilog synthesis Functional simulation VHDL Verilog synthesis Support FLEX 9000 device
families PLS-MAGNUM PLS-MAGNUM
VHDL Verilog synthesis VHDL Verilog synthesis Support FLEX 6000, FLEX 10K, FLEX 8000,
9000 device families PLS-QUARTET, Note PLS-MAGNUM
VHDL Verilog synthesis Support FLEX 9000 device
families PLS-WS PLS-WS
VHDL Verilog synthesis Schematic editor Timing functional simulation Static timing analysi
Note: have current software maintenance agreement, upgrade PLS-MAGNUM system free with MAX+PLUS version 8.1.
Altera Corporation
News View
December 1997
Devices Tools entry-level feature MAX+PLUS software, enabled through authorization device density grows, designers moving code obtained from Altera's site towards high-level design methodology. support http://www.altera.com/authcode. PLS-WEB this trend, Altera regularly enhances MAX+PLUS Site License software include following features: software provide optimal synthesis solutions users experience levels. example, help Schematic text-based design entry users transition high-level design flow, Altera Static timing analysis offering free synthesis tool users with current Graphical floorplan editing software maintenance agreement. advanced users, Compilation support Classic, 5000, Altera works with major synthesis tool vendors, such 7000, 7000S, EPF8282A, EPF8452A, Synopsys, Synplicity, Exemplar Logic, ensure EPM9320, EPF10K10 devices that these sophisticated synthesis tools optimized Altera device architectures. Table shows Altera's Discontinued Support Windows Windows synthesis solution different experience levels. Workgroups Evaluation copies Synopsys, Synplicity, Exemplar Logic tools downloaded from their Compilation synthesis processing requirements respective sites. large programmable logic devices (PLDs) continue demand advanced computer system configurations. MAX+PLUS software kept pace with this Table Synthesis Solution demand providing fastest compilation times Design Synthesis Solution Tool industry. Synthesis Support
Expertise
synthesis user Sophisticated synthesis user synthesis included purchased MAX+PLUS design sites Synopsys
Design Compiler FPGA Compiler FPGA Expres
Synplicity Exemplar Logic
Synplify Galileo Galileo Extreme Leonardo
Because 32-bit operating systems, such Windows Windows UNIX, provide most efficient performance compilers, Altera focusing 32-bit operating systems MAX+PLUS 16-bit operating systems, such Windows Windows Workgroups, support 32-bit processing bandwidth enhanced Windows user interface. addition, 32-bit designs 16-bit operating systems, design must processed inefficient abstraction layer, which degrades performance. Therefore, Altera discontinuing support Windows Windows Workgroups with MAX+PLUS version 1998. However, Altera stand-alone programmer, PL-ASAP2, will continue support Windows Windows Workgroups through remainder 1998.
Entry-Level Software With MAX+PLUS version 8.1, Altera making easier designers obtain entry-level software. PLS-WEB, Altera's free entry-level development software, downloaded from Altera worldwide site. addition, Site License software,
Altera Corporation
News View
December 1997
Technical
ARTICLES
Configuring FLEX 10KA Device
Because Altera's 3.3-V FLEX 10KA devices (including EPF10K50V EPF10K130V devices) have 5.0-V-tolerant inputs, configure devices using 5.0-V BitBlasteror ByteBlasterdownload cables. These download cables channel configuration data FLEX 10KA devices located system circuit boards that have both 3.3-V 5.0-V power planes. download cables 5.0-V power supply, while FLEX 10KA devices 3.3-V power supply. downloading design changes directly device, easily prototype devices accomplish multiple design iterations quick succession.
connect VCCINT VCCIO pins FLEX 10KA device 3.3-V power plane. However, should connect VCCIO 2.5-V power plane, because 2.5-V output pins cannot drive 5.0-V logic levels.
Configuration
FLEX 10KA devices configured using configuration scheme. should guidelines above determine which configuration pins should pulled which power plane. instance, DCLK, DATA0, nCONFIG configuration pins that driven BitBlaster ByteBlaster output pins. This article discusses passive serial (PS) IEEE Therefore, these pins should pulled 5.0-V Std. 1149.1 (JTAG) configuration FLEX 10KA devices power supply. Because CONF_DONE nSTATUS pins with BitBlaster ByteBlaster download cables, bidirectional, open-drain (i.e., they drive tristate) pins driven FLEX 10KA device, should discusses system circuit board should wired also pull them 5.0-V 3.3-V supply. support these device configurations. Figure Wiring Circuit Board JTAG Configuration Before configuring FLEX 10KA device with FLEX 10KA devices configured using BitBlaster ByteBlaster download cable, system circuit board should properly wired support industry-standard JTAG interface. should JTAG configuration. BitBlaster ByteBlaster guidelines above determine which JTAG-dedicated download cables have 5.0-V input output pins configuration pins pull which power plane. instance, ByteBlaster output pins TDI, TCK, drive 5.0-V compatible signals with required high-level voltage (VOH) FLEX 10KA should pulled 5.0-V power supply. devices have MultiVoltI/O interface option, nCONFIG TRST pins connected which allows pins accept 5.0-V inputs drive 5.0-V 3.3-V supply. Because CONF_DONE output voltage levels compatible with nSTATUS pins bidirectional, open-drain pins driven Before configuring FLEX 10KA device with FLEX device, they should also pulled BitBlaster ByteBlaster download cable, should 5.0-V 3.3-V supply. Figure consider following guidelines: more information FLEX devices, pull FLEX 10KA device outputs FLEX Embedded Programmable Logic Family Data 5.0-V power supply, pull BitBlaster Sheet. more information BitBlaster ByteBlaster outputs 3.3-V supply. ByteBlaster download cables, BitBlaster Serial Violating this rule provides current path between Download Cable Data Sheet ByteBlaster Parallel 5.0-V 3.3-V power supplies. However, Port Download Cable Data Sheet, respectively. FLEX 10KA open-drain outputs pulled 5.0-V 3.3-V supply.
Altera Corporation
News View
December 1997
Technical Article
Figure Configuration Using ByteBlaster Download Cable
FLEX 10KA Device
DCLK DATA0 nCONFIG MSEL1 MSEL0 CONF_DONE nSTATUS
10-Pin Male Header (Top View)
5.0-V
Figure JTAG Configuration Using ByteBlaster Download Cable
FLEX 10KA Device
Note
TRST, Note nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
10-Pin Male Header (Top View)
Note
Notes: Because FLEX 10KA devices 144-pin TQFP packages have TRST pin, ignore this connection. nCONFIG, MSEL0, MSEL1 pins must connected support FLEX configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. TRST nCONFIG connected directly either 3.3-V 5.0-V power plane. nSTATUS CONF_DONE pins pulled either 3.3-V 5.0-V power plane.
Altera Corporation
News View
December 1997
Technical Article
Using Language Configure FLEX FLEX 10KA DeviceUsing in-circuit reconfigurability (ICR) embedded processor provides designers with greater flexibility during device configuration. Jamprogramming test language supports embedded processor using MAX+PLUS® development system version higher. This article describes language embedded processor configure FLEX® FLEX 10KA devices (including EPF10K50V EPF10K130V devices). This article should used with (Using Language Embedded Processor) Programming Test Language Specification. more information about Altera's support language, Altera world-wide site http://www.altera.com/jam-isp. Embedded System Interface Embedded systems typically consist embedded processor, EPROM system memory, optional interface logic. Configuration programming data stored system memory (i.e., EPROM FLASH memory). ICR, embedded processor transfers data from system memory programmable logic device (PLD). Figure shows block diagram embedded system FLEX FLEX 10KA devices. embedded processor connects system memory that stores optional interface logic. Although connect JTAG chain directly four embedded processor data pins,
Figure FLEX FLEX 10KA Embedded System Block Diagram
Embedded System
to/from ByteBlaster
Control Control d[3.0] adr[19.0] Control d[7.0] adr[19.0] TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
Interface Logic (Optional)
[7.0]
JTAG Device
Embedded Processor EPROM System Memory
Note
ard[19.0]
FLEX FLEX 10KA Device JTAG Device
Notes: Because FLEX 10KA devices 144-pin TQFP packages have TRST pin, ignore this connection. nCONFIG, MSEL0, MSEL1 pins should connected support FLEX configuration scheme. only JTAG configuration used, connect nCONFIG MSEL0, MSEL1 ground.
Altera Corporation
News View
December 1997
Technical Articles should interface logic save these four pins. Using interface logic will treat JTAG chain address location existing bus. download JTAG chain configuration data BitBlaster ByteBlaster cables, install 10-pin male header your circuit board. Using Language Embedded Configuration Programming language implemented steps. First, must create File (.jam)-using MAX+PLUS software-for configuring your FLEX FLEX 10KA device(s). should store File system memory. Second, Player that resides embedded processor. Player parses File, interprets instructions, reads writes data from JTAG chain.
Figure Creating File Configuration Programming
Player
Player parts: main program functions. main program performs basic functions without requiring modification. will need modify functions, which contained jamstub.c file, cusomtize Player your application. These functions specify addresses pins, delay routines, operating system-specific functions, routines file I/O. execute Player command prompt. processor acts embedded processor ByteBlaster download cable interface JTAG chain. create Player using following command: [-h] [-v] [-p<Hexadecimal parallel port address>] [-m<Memory size bytes>] -d<Initialization list> <Jam File>
Table Variables Configure FLEX DeviceVariable Name
DO_CONFIGURE READ_UESCODE
File
When Create File command (File menu), MAX+PLUS Programmer generates Files from SRAM Object Files (.sof) Programmer Object Files (.pof). When creating Files JTAG chain containing both FLEX MAX® devices, should create separate Files configure FLEX devices independently. Unlike 9000, 7000S, 7000A devices, FLEX devices require configuration upon power-up. Your FLEX File bypass devices JTAG chain want reprogram devices in-system. Create File dialog MAX+PLUS software create File configuration programming. sample JTAG chain shown Figure EPM7128S device first device EPF10K130V device last device JTAG chain. EPM7128S, EPM9560, EPM9560A devices bypassed during configuration. complete instructions create edit Files, search "Creating Files" MAX+PLUS Help.
Value
Function
configure device. Configure device. read JTAG code. Read report code.
continued page
Altera Corporation
News View
December 1997
Technical Article
Implementing Counter Using One-Hot Shift Register
Binary counters used many applications because they fast minimal logic. However, FLEX device applications that have many critical decoding paths, implementing counter using one-hot shift register better alternative. Consider 5-bit binary counter that requires values decoded. This function would require logic elements (LEs) counter minimum additional decode logic. counter registers likely placed single contiguous area counter's five outputs would need routed wherever decode logic resides (most likely spread over device). comparison, same 32-bit counter implemented using one-hot shift register uses only logic cell each counted value. This counter needs logic cells implementation requires additional decode logic. one-hot counter simple logic spread over throughout device without impacting performance. result, one-hot counters generally best used highly-decoded counters. Standard one-hot counters always require register Because registers Altera devices powerup difficult correctly code one-hot counter. resolve this problem, should place gate before after first register.
Figure One-Hot Counter Block Diagram
decode0 decode1 decode2 decode3 decode4
first will inverse standard one-hot counter. following table compares count values standard one-hot counter with Altera one-hot counter.
Table Counter ValueValue
Standard Counter
100000 010000 001000 000100 000010 000001
Altera One-Hot Counter
000000 110000 101000 100100 100010 100001
Figure shows block diagram Altera one-hot counter that iterates through these values. one-hot counters varying lengths, function from library parameterized modules (LPM). Figure shows design from Figure implemented VHDL using function lpm_shiftreg. Because lpm_shiftreg parameterizable function, modified easily large small one-hot counters. Because gates must placed before after first register, they cannot included shift register. Figure shows simulation VHDL example.
DFFE CLRN
DFFE CLRN
DFFE CLRN
DFFE CLRN
DFFE CLRN
DFFE decode5
CLRN
Altera Corporation
News View
December 1997
Technical Article
Figure VHDL Counter using lpm_shiftreg
LIBRARY ieee; ieee.STD_LOGIC_1164.ALL; LIBRARY lpm; lpm.lpm_components.ALL; ENTITY onehot PORT( aclr decode onehot; PORT MAP( clock clk, enable shiftin aclr aclr, sr_out, shiftout PROCESS (clk, aclr) BEGIN aclr THEN first_reg '0'; ELSIF clk'EVENT THEN THEN first_reg PROCESS; first_reg; decode(5 DOWNTO sr_out(4 DOWNTO decode(0) altera;
STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(5 DOWNTO 0));
ARCHITECTURE altera onehot SIGNAL SIGNAL first_reg SIGNAL sr_out BEGIN lpm_shiftreg GENERIC (LPM_WIDTH STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(4 DOWNTO
Figure One-Hot Counter Simulation VHDL Example
aclr decode5
decode4 decode3 decode2 decode1 decode0
Altera Corporation
News View
December 1997
Question&ANSWERS
configure 3.3-V FLEX® device with ByteBlasteror BitBlasterdownload cable?
EPM7192S: EPM7256S: EPM9320: EPM9400: EPM9480: EPM9560:
Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbyte
5.0-V BitBlaster ByteBlaster download cable configure 3.3-V FLEX devices. download cables should connected 5.0-V power supply 3.3-V FLEX devices should connected 3.3-V power supply. Ensure that FLEX device connected 3.3-V power supply before attempting configuration with BitBlaster ByteBlaster download cables. "Configuring FLEX 10KA Devices" page complete details.
Where total number devices programmed.
activate MegaCorefunction?
following steps explain activate MegaCore function with MAX+PLUS software. MAX+PLUS version 8.1, choose Authorization Code (Options menu). Choose MegaCore/AMPP Licenses button. MegaCore/AMPP Licenses dialog box, enter appropriate megafunction code Megafunction box. (See following table).
Ordering Code
PLSM-MICROLIB PLSM-6402 PLSM-6850 PLSM-16450 PLSM-8237 PLSM-8251 PLSM-8255 PLSM-8259 PLSM-FFT PLSM-CSC PLSM-PCI/A PLSM-CRC
large JamFiles generated Altera devices?
vendors supporting Jam, Altera developed support Files 7000S 9000 devices. data provided following table correlates designs that utilize over 7000S devices, over 9000 devices.
Device
EPM7064S EPM7128S EPM7192S EPM7256S EPM9320 EPM9400 EPM9480 EPM9560
Megafunction Code
6AF8-1 6AF8-8 6AF8-9 6AF8-A 6AF8-B 6AF8-C 6AF8-D 6AF8-E 6AF8-2 6AF8-3 6AF8-4 6AF8-5
Typical File Size (Kbytes)
Note: File size data calculated using MAX+PLUS version 8.1.
File sizes will vary depending much device used. format compresses program verify data. compression algorithm looks repetitive strings data. device with high utilization, probability algorithm finding repetitive data will decrease. files that target multiple Altera devices, estimate file size using following equations. These equations assume that devices chain same. example, File targeting three EPM7064S devices would Kbytes. EPM7064S: Kbytes Kbytes EPM7128S: Kbytes Kbyte16
License Authorization Code box, enter license authorization code. will given authorization code when license function from Altera. test-driving megafunction using OpenCorefeature, skip this step. However, cannot generate programming configuration files design using megafunction unless have licensed function. Choose then choose enable function.
generate pin-out Programmer Object File (.pof) EPF6016BC256 device MAX+PLUS version 8.1? EPF6016BC256 devices will fully supported MAX+PLUS software version higher.
Altera Corporation News Views December 1997
Questions Answers generate pin-out EPF6016BC256 devices MAX+PLUS software version 8.1, must enter password performing following steps: MAX+PLUS Programmer, choose Device (Assign menu). Device dialog box, choose FLEX 6000 Device Family drop-down list box. Choose Choose Select Device (Options menu). Select Device dialog box, select FLEX 6000 Device Family drop-down list box. Select EPF6016BC256 from Available Devices drop-down list box. Choose Enable button enter 4SBNYL Password box. Choose Add. should password Existing Passwords box. Choose algorithm will posted Data I/O's Keep Current Bulletin Board Service (BBS) early December 1997. Data site more information (http://www.dataio.com).
aren't assignments visible Graphic Design File (.gdf)?
assignments invisible following reasons:
Show Pins/Locations/Chips command MAX+PLUS Graphic Editor turned off. turn choose Show Pins/Locations/Chips (Options menu). have made assignments pin. Assign each signal individual pins label them accordingly. Ensure that brackets ([]) removed from names, because "a[0]" specifies with width one. hold time violations when simulating FLEX design MAX+PLUS version 8.1?
MAX+PLUS software support EPF6016BC256 devices.
what order program EPC1 devices FLEX device configuration?
EPC1 devices required configure EPF10K100 larger devices. MAX+PLUS software automatically generates Programmer Object Files (.pof) devices. first EPC1 device chain (i.e., EPC1 device with CONF_DONE connected pin) programmed with <project name>.pof. second EPC1 device chain programmed with <project name>_1.pof further information, Configuration EPROMs FLEX Devices Data Sheet.
When using EPF10K70, EPF10K100, EPF10K100A devices speed grade, hold time violations when simulating with MAX+PLUS Simulator third-party simulator. hold time violation caused register driving clock enable another register same logic array block (LAB), spurious hold time violation occurred. This violation ignored. other hold time violations still valid. software update (MAX+PLUS version 8.14) that corrects this hold time violation available Altera site http://www.altera.com.
Which programming adapter should program EPC1441 Configuration EPROM?
When programming EPC1441 Configuration EPROMs, should PLMJ1213 adapters 8-pin 20-pin PLCC packages PLMT1064 adapters 32-pin TQFP packages. When will Data provide programming support EPC1441 devices?
When MAX+PLUS Compiler creates EDIF Output File, file should contain numbers input, output, bidirectional pins. However, when Optimize Timing command (Processing menu) turned EDIF Output File will list input numbers. Turn Optimize Timing command include input numbers your EDIF Output File. Optimize Timing command used make simulations faster. Turning this option does change functionality performance design; UNIX workstations makes .edo files smaller.
MAX+PLUS version 8.1, don't input numbers show EDIF Output File (.edo)?
algorithm programming EPC1441 devices currently under final testing. algorithm will included Data software version 5.7, which scheduled release March 1998. programming
Altera Corporation News Views December 1997
Altera
VIEWPOINT
Achieving Performance GoalHistorically, designers developing digital logic clear options. designs requiring high density, high performance, lowest unit cost, ASICs were best choice. designs that required flexibility fast time-to-market, programmable logic devices (PLDs) offered solid solution. Choosing Development Tool Today's synthesis tools have powerful features that allow make area/ speed tradeoffs achieve your design goals. Depending tool, able indicate preference area speed, specify timing constraints given clock data path, balance register-to-register delays maximize clock performance (see Figure When choosing development tool, should weigh features capabilities tool versus price. Many tool vendors provide different tiers tools different prices. design flow goals should drive designers select right development tool. Using Effective Design Techniques far, most effective strategy improving design's area utilization performance working with design's source files. performance, goal reduce logic levels critical path tailoring design source code. either design gate level remove inefficiency caused
Jack Ogawa Senior Product Planning Manager
decision process today's digital logic marketplace quite different. With advent 250,000-gate devices cost-per-gate price that rivals gate arrays, today's PLDs provide solution that once exclusively domain ASICs. Like ASICS, designing these highdensity PLDs challenge. Higher levels abstraction required design entry efficiency, making optimization process much more challenging. Once design been functionally verified part top-down design flow, common tactics used minimize logic levels design's critical path. simplest method best synthesis tool task. second technique modify design files optimize area performance.
Figure Balancing Register-to-Register DelayCombinatorial Logic Combinatorial Logic Combinatorial Logic Combinatorial Logic
CRIT clock speed limited tCRIT
Combinatorial Logic
Combinatorial Logic
Combinatorial Logic
Combinatorial Logic
CRIT
CRIT Moving register data path reduces tCRIT, resulting increased clock speed
Altera Corporation
News View
December 1997
Altera Viewpoint synthesis tool, change implementation critical function. first, this procedure seems like painful task. However, designing hierarchically minimize pain allow "what-if" scenarios implemented easily Verilog examples Figure show implementations down counter function. optimized counter yields dramatically improved results, both resource area performance. design hierarchy, these implementations easily switched determine which yields best results. When implementing examples from Figure EPF6016 device, using pre-developed, optimized counter more than doubled clock performance reduced logic element (LE) usage fourth original size (see Table
Table Performance Optimization Improvement
Item
Clock speed
Figure Inferred Instantiated Verilog Counter
Inferred
module cntr(din, load, up_dn, reset, clk_en. clk, count); input [15:0] din; input load; input up_dn; input reset; input clk_en; input clk; output [15:0] count; [15:0] creg; wire [15:0] nreg; assign count creg; assign nreg (~reset) (load) (up_dn) creg creg always @(posedge clk) begin creg nreg; endmodule
Instantiated
module updn_ctr_rpl (data, up_dn, load, clk, reset, count); parameter width input [width-1 data; input up_dn, load, clk, reset; output [width-1 count; Synopsys dc_script_begin set_implementation instantiate DW03_UPDN_CTR DW03_updn_ctr (width) U0(data, up_dn, load, clk, reset, count); endmodule
Inferred
Instantiated
Another option functions from library parameterized modules (LPM). With functions, implement commonly used functions that controlled user-specified parameters. Figure shows symbol function lpm_mult. parameters lpm_mult function changed easily achieve desired design results, example, using pipeline stages improve clock speeds. Conclusion density performance PLDs grown accommodate system-level functional blocks. This growth also brings renewed awareness area performance requirements these blocks, much like traditional ASIC design flows. plan optimization process selecting right development tools using hierarchical design structure, full
Figure lpm_mult Multiplier
INPUT_A_IS_CONSTANT= INPUT_B_IS_CONSTANT= LPM_PIPELINE= LPM_REPRESENTATION= LPM_WIDTHA= LPM_WIDTHB= LPM_WIDTHS=LPM_WIDTHA
LPM_MULT clock dataa[] sum[] datab[] aclr result[]
potential solution realized, offering best both worlds.
Altera Corporation
News View
December 1997
Customer
Cisco Systems designers used Serial Vector Format (.svf) File, they would have devote large amount memory management software properly store .svf file.
Application
Success with Language
Since introduction July 1997, there have been several successful applications Jamprogramming test language. language, softwarelevel standard in-system programmability (ISP), successfully addressed issues concerning ease-of-use, fast programming times, small file sizes. With these capabilities, language provided solutions problems that have plagued in-system programming. Cisco Systems Cisco Systems, Inc. currently using language program EPM7192S device main controller board. processor this board only programs EPM7192S device in-system, also identifies programs EPM7128S device that attached JTAG chain expandable daughter card. Using Serial Vector Format Files (.svf) would have required large amount memory management software properly store Files. Instead, Cisco used Files (.jam), which much smaller. Because Files small enough memory location, extra memory available other tasks files, giving designers more flexibility. Lauterbach Datentnik GMBH Heitec Datentechnik Gmbh first company implement working system. their recent projects develop testing hardware base stations. goal project high system performance (i.e., 90-MHz system clock). Additionally, designers wanted able upgrade system field. Heitec Datentechnik design team chose combination EPM7128S EPM9560 devices their project. Because devices programmed in-system JTAG ports, team able implement prototype system quickly. took only three hours port Player their 32-bit Siemens processor. language allowed designers program EPM7128S devices using ByteBlastercable, Player, which reduced their overall cost board size. Designers were also able replace 500-Kbyte File with 25-Kbyte File. Before language created, Heitec Datentechnik recall boards from field make system changes. Using Files allows boards upgraded field, saving time costs. "Before used language, problems updating boards field," explained Joerg Czech, member hardware systems development team. "With language, save time money. send updated Files Player customers e-mail, they update boards themselves." Conclusion customers such Cisco Systems Heitec Datentechnik, language successfully reduced file sizes programming times. Because language both silicon-vendorindependent platform-independent, address other concerns such proprietary file formats, vendor-specific programming algorithms, ability work with existing future devices manufactured different processes. open standard, language benefit silicon vendors, manufacturers, programmers. more information about programming test language, Altera's world-wide site http://www.altera.com.
News Views December 1997
"Before used language, problems updating boards field," explained Joerg Czech, member hardware systems development team Heitec Datentechnik Gmbh. "With language, save time money. send updated Files Player customers email, they update boards themselves."
Altera Corporation
Technical Articles Using Language Configure FLEX FLEX 10KA Devices continued from page Brackets ([]) indicate optional parameters. Table shows variables required after option configure FLEX device with language. example, type following text command prompt, Player will configure device, limit memory Mbyte, write/read data through parallel port base address 0x378 File chiptrip.jam: -p378 -m1000000 -dDO_CONFIGURE=1 chiptrip.jam JTAG Timing Parameters Waveforms should JTAG timing parameters waveforms ensure proper Player operation system. Table shows state machine timing specifications. These timing parameters consistent with those given IEEE Std. 1149.1 specification. Figure illustrates waveforms that correspond each timing parameter.
Figure JTAG WaveformTMS
Table JTAG Timing Parameters FLEX FLEX 10KA DeviceSymbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Parameter
clock period clock high time clock time JTAG port setup time JTAG port hold time, Note JTAG port clock output JTAG port high-impedance valid output JTAG port valid output highimpedance Capture register setup time Capture register hold time Update register clock output Update register high-impedance valid output Update register valid output high-impedance
Unit
Note: hold time dependent falling edge JTAG configuration clock (TCK).
tJCP tJCH tJCL tJPSU tJPH
JPZX tJPCO tJPXZ
tJSSU tJSH
Signal Captured Signal Driven
tJSZX
tJSCO
tJSXZ
Altera Corporation
News View
December 1997
Technical Article
Tips Boost Registered Performance
Coercing your design meet desired speed (e.g., assigning re-assigning cliques, adjusting synthesis settings, etc.) complicated task. Although each project should analyzed caseby-case basis, reducing number critical paths that meet specified speed often give your design extra help needs. This article describes tips boost registered performance:
Recompile re-analyze your project. project still does meet desired performance, select next longest delay path repeat steps through Instead assigning cliques, assign cells timing path same row. Floorplan Editor, select timing path, choose Pin/Location/Chip (Assign menu) assign functions row. This process keeps related logic same without locking down exact logic cells. Reduce Longest Delay Path This section describes ways reduce longest delay path:
Identify logic paths that cross routing rows group related logic same Reduce longest delay path
Identify Logic Paths that Cross Routing Rows Group Related Logic Same Logic paths that cross rows incur additional column delay. Grouping time-critical paths same reduce overall delay. identify paths that cross rows, perform following steps MAX+PLUS® Timing Analyzer Registered Performance display: Perform timing analysis your project. Choose List Paths review number paths that meet specified performance frequency. performance frequency, select Time Restrictions (Options menu) Timing Analyzer adjust settings Registered Performance Options needed your design. Begin with slowest path work your down list. Sometimes, making adjustments slowest path alone will boost project desired speed. After selecting slowest path MAX+PLUS Meggage Processor, perform following steps: Turn Locate Floorplan Editor Message Processor window. Choose Locate All. Floorplan Editor, select logic cells that cross routing rows assign them clique. Figure When assigning clique, Compiler usually groups paths together within same row. However, should make sure that paths actually same row. find assigned clique, choose Find Clique Floorplan (Utilities menu). Search "Clique Assignments Section" MAX+PLUS Help more information.
Register balancing Pipelining your project Using look-ahead decode method
Register Balancing
project will sometimes have longer delay between registers than desired, shorter delay between other adjacent registers same path. this situation, shifting delay from register another balance registered performance, thereby boosting project's speed. Figure moving register shortens longest path (i.e., from ns).
Figure Using Floorplan Editor
Altera Corporation
News View
December 1997
Technical Article
Pipelining your Project
Pipelining your project similar register balancing because balances delay from register another. pipelining, however, registers project. Each pipeline stage (i.e., each added register) one-clock latency delay. Because FLEX® architecture includes register with each lookup table (LUT), pipelining your project generally does require additional device resources. Figure
adding pipeline stage reduces longest path (i.e., from ns).
Using Look-Ahead Decode Method
levels logic associated with decoding data 16-bit counter. decoded data fans combinatorial logic, delay path becomes longer. reduce delay path, decode data clock cycle earlier register output provide shorter delay path. Figure
Figure Shifting Delay from Register Another
nDFF
nDFF
nDFF
Combinatorial Logic
Combinatorial Logic
Combinatorial Logic
CLRN
CLRN
CLRN
Move Register Equalize Critical Path
Figure Pipelining your Design
Combinatorial Logic
Combinatorial Logic
CLRN
CLRN
CLRN
CLRN
Registers Added Create Pipelined Stage
Figure Using Look-Ahead Decode Method
Original Design Look-Ahead Decode Design
Counter
Decode Value
Combinatorial Logic
Counter
Decode Value
Combinatorial Logic
CLRN
Altera Corporation
News View
December 1997
Altera
Altera Forms Design Consultants Alliance
programmable logic device (PLD) densities continue increase, Altera recognizes that designers require innovative tools design expertise boost their productivity enable them take advantage growing capacity. Today's increasing densities encourage more complex designs, complex designs usually require more expertise design time. Thus, demand both intellectual property design consultation increased. address increasing demand intellectual property, Altera created Altera Megafunction Partners Program (AMPP) Altera MegaCorefunctions. AMPPSM MegaCore functions provide growing library megafunctions targeted specific Altera® device architectures. meet design consultation demand, Altera recently created another innovative alliance. September 1997, Altera announced formation Altera Consultants Alliance Program (ACAP). ACAPSM partnership worldwide alliance between Altera specially trained design consultants that broadens support designers using Altera PLDs. ACAP consultants provide design services that target Altera devices, giving designers resource reduce design cycle times time-to-market. ACAP goal attract experienced design consultants familiar with Altera PLDs, certify them, make their skills available designers worldwide. Before Altera certifies recommends ACAP consultants, consultants receive advanced training Altera architectures software, equipped with state-of-the-art design tools. After training, Altera lists ACAP consultants geography, area expertise, third-party development tool knowledge. Certified ACAP consultants currently working North America Europe. review consultants' qualifications areas expertise referring Altera world-wide site http://www.altera.com. Current ACAP consultants shown below:
Advanced Logical Design, Inc. ASIC Designs, Inc. Design Analysis Associates, Inc. Eberwein Associates, Inc. I/F/I Locke's Digital Development, Ltd. Northwest Logic Design Software Systems Engineering, Inc. Systems Design Group
Contact ACAP consultants directly more information. independent contractors, consultants solely responsible contractual agreements. Altera does participate negotiating consulting terms fees, warrant consultants' work. inquire comment about ACAP program, please send e-mail acap-info@altera.com. find more about becoming ACAP member, please send e-mail acap@altera.com.
Altera ICSPAT World Expo
Altera participated International Conference Signal Processing Technology (ICSPAT) World Expo September through Diego, California. Altera engineers presented papers, Pipelined Adaptive Filters Altera PLDs Processor Core FLEX 10Kand co-presented PLD, Based FFTs PLD-Based Solution Cable Modem with AMPP partner Integrated Silicon Systems. four papers were presented "FPGAs DSP" session. Over customers stopped Altera World Expo booth FLEX presentation, Total Solution Your Most Complex Applications. more information Altera's solutions, Altera's site http://www.altera.com.
Altera Corporation
News View
December 1997
Altera
Altera Target ApplicationTarget Applications provide solutions application-specific needs. Target Applications leverage MegaCorefunctions Altera Megafunction Partners Program (AMPPSM) functions provide integrated solutions that deliver significant time-to-market benefits. complete Target Applications solution includes both megafunctions documentation that critical these megafunctions reference designs working. Altera Target Applications focuses markets such digital signal processing (DSP), peripheral component interconnect (PCI), wireless broadband communications. more information, Altera world-wide site http://www.altera.com. Altera Target Applications include:
FLEX Building Blocks Imaging Functions Wireless Broadband Communications Interfaces Universal Serial (USB) Communications Communications Data Communications Telecommunications Asynchronous Transfer Mode (ATM)
Altera PublicationNew Altera publications available from Altera Literature Services. Individual documents available Altera's world-wide site http://www.altera.com. Document part numbers shown italic type.
Configuration EPROMs FLEX Devices Data Sheet (A-DS-EPROM-07) FLEX Embedded Programmable Logic Family Data Sheet Supplement (A-DSS-F10K-2.5) EPF10K100A Embedded Programmable Logic Family Data Sheet Supplement (A-DSS-F10K-2.6) EPF10K50V Embedded Programmable Logic Device Data Sheet Supplement (A-DSS-F10K-2.7)
EPF10K100A Embedded Programmable Logic Device Data Sheet Supplement (A-DSS-F10K-2.8) FLEX 6000 Programmable Logic Device Family Data Sheet Supplement (A-DSS-F6KPLD-2.1) Megafunction (A-SB-022-01) Internal Tri-State Emulation (M-TB-029-01) Authorization Codes (M-TB-030-01) Advantages FLEX Devices Lucent Orca Devices (M-TB-031-01) Programming Methods Ordering Codes (M-TB-032-01)
Discontinued DeviceIn recent months, Altera announced that various products will discontinued (see table below). Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera sales representative. Selected ADVs, PDNs,
Discontinued Device Ordering CodeDevice Family
FLASHlogic 5000 7000
complete listing discontinued devices also available Altera's world-wide site http://www.altera.com. Rochester Electronics, aftermarket supplier, offers support many discontinued Altera products. Contact Rochester Electronics (508) 462-9332 more information. also their site http://www.rocelec.com.
Device
EPX880 EPX8160 (all packages, temperature grades, speed grades) EPM5032SC-15 EPM7256SRC208-12
Last Order Last Shipment Reference Date Date
6/30/97 6/30/97 12/31/97 6/30/98 12/31/97 3/31/98 9625 9624 9713
Altera Corporation
News View
December 1997
Altera
Every
Altera World
annual Altera World show, hosted Altera Japan, held October Tokyo, Japan. This one-day event featured latest Altera products strategies, raised awareness programmable logic devices (PLDs), tools, design methodologies, positioned Altera gate-array alternative. presentations given Altera employees included:
Third-Party Programming Support
Data Microsystems provide programming hardware support selected Altera devices. Algorithms supplied Data I/O's Keep Current Express-Bulletin Board Service (KCE-BBS) Microsystems' BBS. Programming support Configuration EPROM, MAX® 9000, 7000 devices shown table below. information subject change.
Third-Party Programming Hardware Support
Device
EPC1064 EPC1213 EPC1 EPC1441 EPM7032 EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7192E EPM7192S EPM7256E EPM7256S EPM9320 EPM9400 EPM9480 EPM9560
Reshaping ASIC Landscape (keynote address) Rodney Smith Altera: Proven Platform Masaru Hamada Altera Data Communication High-End Video Applications Wong Gate Array Design Flow Wong Challenges Solutions Millenium Craig Lytle
Data
Microsystems
Note
Additional presentations were given each participating third-party companies, including many Altera's ACCESSSM AMPPSM partners. Companies participating World this year included Synopsys, Viewlogic, Data I/O. photographs below illustrate some Altera's booths show.
Notes: These devices supported Data 3900 version 5.6, UniSite version programmers. These devices supported Microsystems programmers version 3.28. Data plans support EPC1441 devices. Contact Data directly more information.
Current Software VersionThe latest versions Altera software products shown below:
MAX+PLUS version (PC, SPARCstation, 9000 Series 700/800, RISC System/6000 platforms)
Altera Corporation
News View
December 1997
Every Issue
Altera Programming Hardware Support
following tables contain latest programming hardware information Altera devices. correct programming, software version shown "Current Software Versions"on page Table
Table Altera Programming Adapters (Part Note
Device
EPC1064 (2), EPC1064V (2), EPC1441 EPC1 EPC1213, EPM9320A
Table Altera Programming Adapters (Part Note
Device
EPM7128, EPM7128E
Package
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
Adapter
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC, PLMQ7128/7160-160NC,
Package
DIP, J-lead TQFP J-lead J-lead (84-pin) RQFP (208-pin) RQFP (240-pin)
Adapter
PLMJ1213 PLMT1064 PLMJ1213 PLMJ1213 PLMJ9320-84 PLMR9000-208NC, PLMR9000-240NC, PLMG9000-280 PLMJ9320-84 PLMR9000-208 PLMJ9400-84 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMR9000-208NC, PLMR9000-240NC, PLMG9000-280 PLMR9000-208 PLMR9000-240 PLMR9000-304 PLMJ7000-44 PLMT7000-44 PLMJ7000-44 PLMQ7000-44 PLMT7000-44
PLMJ7000-44 PLMT7000-44 PLMT70000-100NC, PLMJ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-84 PLMQ7000-100NC, PLMT7000-100NC, PLMQ7128/160-160NC
EPM7160S
J-lead PQFP (100-pin) PQFP (160-pin)
EPM7160E J-lead PQFP (100-pin) PQFP (160-pin) EPM7192S, EPM7192E EPM7256S, EPM7256E PQFP (160-pin) (160-pin) PQFP (160-pin) RQFP (208-pin) PQFP (160-pin) (192-pin) RQFP (208-pin) PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMQ7192/256-160NC PLMG7192-160 PLMQ7192/7256-160 PLMQ7256-208NC PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208
EPM9320
J-lead (84-pin) RQFP (208-pin)
EPM9400
J-lead (84-pin) RQFP (208-pin) RQFP (240-pin)
EPM9480
RQFP (208-pin) RQFP (240-pin)
EPM9560A
RQFP (208-pin) RQFP (240-pin)
EPM9560
(280-pin) RQFP (208-pin) RQFP (240-pin) RQFP (304-pin)
EPM7032S
J-lead (44-pin) TQFP (44-pin)
Notes: Refer Altera 1996 Data Book device adapter information 5000 Classic devices. Altera offers adapter exchange program 0.8-micron EPM5032, EPM5064, EPM5130 programming adapters. "MAX 5000 Classic Product Transitions" page this newsletter more information. FLEX 8000 Configuration EPROM. FLEX 10K, FLEX 8000, FLEX 6000 Configuration EPROM. These devices shipped carriers.
EPM7032, EPM7032V
J-lead (44-pin) PQFP (44-pin) TQFP (44-pin)
EPM7064S
J-lead (44-pin) TQFP (44-pin) TQFP (100-pin)
Table provides programming configuration compatibility information BitBlasterserial ByteBlasterparallel port download cables.
Table BitBlaster ByteBlaster Cable Compatibility
Device
FLEX FLEX 10KA FLEX 10KB FLEX 8000 FLEX 6000 9000 7000S 7000A
EPM7064
J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
Package
package
Hardware
PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER
packages packages packages package
EPM7096
J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
EPM7128S
J-lead (84-pin) PQFP (100-pin) TQFP (100-pin) PQFP (160-pin)
Altera Corporation
News View
December 1997
Every Issue
Altera Device Selection Guide
current information Altera FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices listed here. Information other Altera products located Altera 1996 Data Book. Contact Altera your local sales office current product availability.
FLEX DeviceDEVICE
EPF10K10 EPF10K10 EPF10K10A EPF10K10A EPF10K20 EPF10K20 EPF10K30 EPF10K30 EPF10K30A EPF10K30A EPF10K30B EPF10K30B EPF10K40 EPF10K50 EPF10K50 EPF10K50V EPF10K50V EPF10K50B EPF10K50B EPF10K70 EPF10K100 EPF10K100A EPF10K100A EPF10K100B EPF10K100B EPF10K130V EPF10K130B EPF10K130B EPF10K180B EPF10K250A EPF10K250A EPF10K250B EPF10K250B
Note
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin 144-Pin TQFP, 208-Pin 144-Pin TQFP, 208-Pin 144-Pin TQFP, 208-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin 208-Pin QFP, 240-Pin QFP, 356-Pin 208-Pin QFP, 240-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin QFP, 256-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin QFP, 256-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin QFP, 256-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin QFP, 256-Pin 208-Pin QFP, 240-Pin 240-Pin QFP, 356-Pin BGA, 403-Pin 240-Pin 240-Pin QFP, 356-Pin 240-Pin QFP, 356-Pin 208-Pin QFP, 240-Pin QFP, 256-Pin BGA, 356-Pin 208-Pin QFP, 240-Pin QFP, 256-Pin BGA, 356-Pin 240-Pin QFP, 503-Pin 503-Pin 240-Pin QFP, 356-Pin BGA, 600-Pin 240-Pin QFP, 356-Pin BGA, 600-Pin 208-Pin QFP, 240-Pin QFP, 356-Pin BGA, 600-Pin 208-Pin QFP, 240-Pin QFP, 356-Pin BGA, 600-Pin 599-Pin PGA, 600-Pin 240-Pin QFP, 356-Pin BGA, 599-Pin PGA, 600-Pin 240-Pin QFP, 356-Pin BGA, 600-Pin 240-Pin QFP, 356-Pin BGA, 600-Pin 599-Pin PGA, 600-Pin 600-Pin 356-Pin BGA, 599-Pin PGA, 600-Pin 356-Pin BGA, 600-Pin
GATES
10,000 10,000 10,000 10,000 20,000 20,000 30,000 30,000 30,000 30,000 30,000 30,000 40,000 50,000 50,000 50,000 50,000 50,000 50,000 70,000 100,000 100,000 100,000 100,000 100,000 130,000 130,000 130,000 180,000 250,000 250,000 250,000 250,000
PINS Note
107, 107, 107, 107, 107, 147, 107, 147, 147, 189, 147, 107, 147, 189, 107, 147, 189, 107, 147, 189, 107, 147, 189, 147, 189, 274, 189, 189, 147, 189, 189, 147, 189, 189, 189, 189, 274, 189, 274, 147, 189, 274, 147, 189, 274, 470, 189, 274, 470, 189, 274, 189, 274, 470, 274, 470, 274,
TEMP.
SPEED GRADE
FLIPFLOPS
1,344 1,344 1,968 1,968 1,968 1,968 1,968 1,968 2,576 3,184 3,184 3,184 3,184 3,184 3,184 4,096 5,392 5,392 5,392 5,392 5,392 7,120 7,120 7,120 10,534 12,624 12,624 12,624 12,624
LOGIC ELEMENTS 1,152 1,152 1,728 1,728 1,728 1,728 1,728 1,728 2,304 2,880 2,880 2,880 2,880 2,880 2,880 3,744 4,992 4,992 4,992 4,992 4,992 6,656 6,656 6,656 9,728 12,160 12,160 12,160 12,160
BITS
6,144 6,144 6,144 6,144 12,288 12,288 12,288 12,288 12,288 12,288 12,288 12,288 16,384 20,480 20,480 20,480 20,480 20,480 20,480 18,432 24,576 24,576 24,576 24,576 24,576 32,768 32,768 32,768 32,768 40,960 40,960 40,960 40,960
Notes: Select FLEX 10KA FLEX 10KB devices will available 1998. pins dedicated inputs.
FLEX 6000 DeviceDEVICE
EPF6016 EPF6016A EPF6024A
GATES
16,000 16,000 24,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 208-Pin QFP, 240-Pin PQFP, 256-Pin 208-Pin QFP, 240-Pin PQFP, 256-Pin
PINS
117, 171, 199, 117, 171, 199, 117, 171, 199, 117, 171, 199, 171, 199, 171, 199,
TEMP.
SPEED GRADE
FLIPFLOPS
1,320 1,320 1,320 1,320 1,960 1,960
LOGIC ELEMENTS
1,320 1,320 1,320 1,320 1,960 1,960
Notes: Four pins dedicated inputs. indicates 3.3-V voltage supply. faster commercial temperature speed grade devices de-rated operate over industrial temperature range.
Altera Corporation
News View
December 1997
Every Issue
FLEX 8000 DeviceDEVICE
EPF8282A
GATES
2,500
PIN/PACKAGE OPTIONS
84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 100-Pin TQFP 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
PINS
118, 118, 112, 120, 112, 120, 112, 120, 148, 148, 148, 181, 181, 181,
TEMP.
SPEED GRADE
FLIP- LOGIC FLOPS ELEMENTS
EPF8282AV EPF8452A
2,500 4,000
EPF8636A
6,000
EPF8820A
8,000
EPF81188A
12,000
1,188
1,008
EPF81500A
16,000
1,500
1,296
Notes: Four pins dedicated inputs. indicates 3.3-V voltage supply.
9000 DeviceDEVICE
EPM9320 EPM9320A EPM9400 EPM9480 EPM9480A EPM9560 EPM9560A
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 356-Pin
PINS
132, 132, 132, 132, 139, 146, 146, 146, 153, 191, 153, 191, 153, 191, 153, 191,
TEMP.
SPEED GRADE
-15, -15, -10, -10,
Note: Four pins dedicated inputs.
7000 DeviceDEVICE
EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032 EPM7032 EPM7032V EPM7032V EPM7032V EPM7064S EPM7064, EPM7064S EPM7064, EPM7064S EPM7064, EPM7064S EPM7064 EPM7064
(Part
MACROCELLS
PIN/PACKAGE OPTIONS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP (2)/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP (2)/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP (2)/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP
PINS
TEMP.
SPEED GRADE (ns) (MHz)
90.9 76.9 90.9 76.9 62.5 178.6 90.9 76.9
continued page
Altera Corporation News Views December 1997
Every Issue Altera Device Selection Guide, continued from page
7000 DeviceDEVICE EPM7096 EPM7096 EPM7096 EPM7096 EPM7128S EPM7128E, EPM7128S EPM7128E, EPM7128S EPM7128E EPM7128E, EPM7128S EPM7128E EPM7160S EPM7160E, EPM7160S EPM7160E EPM7160E, EPM7160S EPM7160E EPM7192S EPM7192S EPM7192E EPM7192E, EPM7192S EPM7192E EPM7256S EPM7256S EPM7256E, EPM7256S EPM7256E, EPM7256S EPM7256E
(Part
MACROCELLS PIN/PACKAGE OPTIONS
68-Pin PLCC (1), 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC (1), 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (2), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (2), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (2), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (2), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (2), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 208-Pin RQFP, 208-Pin PQFP 208-Pin RQFP, 208-Pin PQFP 160-Pin PQFP (1), 192-Pin (1), 208-Pin RQFP, 208-Pin PQFP 160-Pin PQFP (1), 192-Pin (1), 208-Pin RQFP, 208-Pin PQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP, 208-Pin PQFP
PINS
TEMP.
SPEED GRADE (ns) (MHz) -10(P) -10(P) -12(P) -12(P) 90.9 76.9 90.9 76.9 62.5 90.9 76.9 62.5 90.9 76.9 62.5 90.9 76.9 62.5
132, 132, 132, 132, 132,
Notes: available 7000S devices. Available 7000S devices only.
Access Altera
Getting information services from Altera easier than ever. table below lists some ways reach Altera:
Information Type
Literature
AccesAltera Literature Services World-Wide
U.S. Canada
(888) 3-ALTERA lit_req@altera.com http://www.altera.com (800) SOS-EPLD (408) 544-6403 (800) 800-EPLD (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Other Location(408) 544-7144 lit_req@altera.com http://www.altera.com (408) 544-7000 (408) 544-6403 (408) 544-7000 (408) 544-6401 sos@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com
Non-Technical Customer Service Technical Support
Telephone Hotline Telephone Hotline a.m. p.m. Pacific Time) Electronic Mail Site
General Product Information
Telephone World-Wide
Notes:
MAX+PLUS software manuals, contact Altera Customer Service your local distributor. also contact your local Altera sales office sales representative. Altera site listing.
Altera Corporation
News View
December 1997
Response Form
Your Name: Organization: Street Address: City, State, ZIP: Phone: E-Mail:
would like subscription News Views. would like have design featured News Views. Please correct address.
Tell What Think
Please take moment help improve News Views rating usefulness following sections. Your answers will help shape content future issues. Useful Devices Tools Altera Publications Questions Answers Technical "How Articles Information Altera's Partners Interface Support Customer Applications Software Utilities Current Software Versions Altera News Very Useful
Please write your comments about News Views space below (use additional pages necessary). Which subjects getting enough coverage? What questions still have? What features would like see?
Please mail copy this page
Altera Literature Distribution Services Altera Corporation Innovation Drive Jose, 95134 Fax: (408) 544-7809 E-mail: n_v@altera.com
Altera Corporation News Views December 1997

FLEX 10K-1 FLEX 10K-2 devices faster system speeds existing members hi

Top Searches for this datasheet

Other recent searches