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Altera Ships New, Low-Cost FLEX 6000 Family
Altera recently began shipping new, low-cost FLEX® 6000 programmable logic device family, which offers size cost that directly comparable those gate arrays. Figure result technological advances architecture enhancements, FLEX 6000 family combines traditional benefits fast time-to-market flexibility with exceptionally cost high-volume applications. Gate array development often requires hidden costs that commonly overlooked, including nonrecurring engineering (NRE) costs, cost lengthy design cycle, cost market opportunities that missed slow time-to-market. contrast, FLEX 6000 devices cost less than comparable ASIC devices when these hidden costs added into unit cost gate arrays. example, 10,000-gate EPF6010 device 144-pin TQFP package expected cost just $6.00 quantities 50,000 mid-1998. System-Level Features FLEX 6000 device family contains number powerful system-level features boost your design efficiency:
MultiVoltI/O interface supports 5.0-V, 3.3-V, 2.5-V mixed-voltage systems. Power consumption less than standby mode. In-circuit reconfigurability (ICR) available external Configuration EPROM intelligent controller.
OptiFLEX Architecture Redefines Programmable Logic Efficiency competitive pricing FLEX 6000 device family made possible Altera's OptiFLEXarchitecture. Every feature OptiFLEX architecture targeted producing maximum performance utilization smallest possible area. FLEX 6000 architecture shown Figure Through innovative feature called interleaved logic array blocks (LABs), each logic element (LE) drive local interconnects, optimizing global column resource utilization within FLEX device. FLEX 6000 logic arrays routed through Altera's patented FastTrackInterconnect, series fast, continuous column channels that entire length width device. Each FastTrack column feeds multiple elements (IOEs), which provide programmable slew-rate individual tri-state output enable control each pin. FLEX 6000 family also supports FastFLEXI/O. This innovative feature provides direct path from fast clock-to-output timing. FLEX 6000 devices offer benefits dedicated peripheral registers with smallest possible size.
Devices fully compliant with peripheral component interconnect (PCI) standard. Built-in JTAG boundary-scan test (BST) circuitry available without consuming device resources.
Figure FLEX 6000 Gate Array Pricing
Relative Unit Cost
FLEX 6000
Gate Array
1996 1997 1998
continued page
A-NV-Q397-01
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Contents
Features Altera Ships New, Low-Cost FLEX 6000 Family Altera Viewpoint: Pricing Roadmap Shows Steeper Reductions Customer Application: Bailey Controls Uses Megafunctions Solve Challenge Altera News Site License Authorization Codes Nova Engineering Introduces Megafunction Development System Advantages EABs Applications Altera Power Play Scores Altera Target Applications Altera World Expo Altera Moved 7000 Beats Kasparov Test-Drive Megafunctions with OpenCore Feature Devices Tools Altera Increases FLEX Performance FLEX Pricing Availability EPF10K100A Coming Soon 9000A Update 7000S Pricing Availability Faster 7000S Speed Grades 7000S Supports
Conventional 7000S Device Programming 7000 Product Transitions Product Transitions Improvement High-Density Compilation Times MAX+PLUS Version Ship September 1997 Discontinued Devices
Technical Articles Implementing Encoder Using Functions Configuring FLEX 6000 Devices Introducing Open-Standard Programming Test Language Frequently Asked Language Questions Customer Training Brings Speed Advantages Questions Answers Altera's Failure Analysis Service Every Issue Altera Publications Third-Party Programming Support Altera Programming Hardware Support Current Software Versions Altera Device Selection Guide Access Altera Response Form
information about this newsletter, submit questions, contact: Erica Heidinger, Publisher Craig Lytle, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-0348 E-mail: n_v@altera.com
Printed recycled paper.
Altera, AMPP, Atlas, BitBlaster, ByteBlaster, Classic, ClockLock, ClockBoost, FastFLEX, FastTrack, FLASHlogic, FLEX, FLEX 10K, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX DSP, µPitch, 9000, 9000A, 7000, 7000E, 7000S, 5000, MAX, MAX+PLUS, MAX+PLUS MegaCore, MultiVolt, OpenCore, OptiFLEX, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: SuperBGA registered trademark Amkor/Anam. Verilog registered trademark Cadence Design Systems. Data registered trademark Data Corporation. registered trademark International Business Machines Corporation. Synopsys registered trademark Synopsys, Inc. Viewlogic registered trademark Viewlogic Systems. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1997 Altera Corporation. rights reserved.
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Feature Altera Ships New, Low-Cost FLEX 6000 Family continued from page µPitch Bond Technology With µPitchbond feature, FLEX 6000 devices contain bond pitch just mils microns) achieve maximum size reduction. Therefore, 16,000-gate FLEX 6000 device 240-pin package will only larger than gate array with same count, shown Figure FLEX 6000 Family Members FLEX 6000 device family offers from 5,000 24,000 usable gates logic manufactured 0.5-micron, triple-layer metal SRAM process. Later 1997, manufacturing will move 0.35-micron triple-layer metal process. Table outlines FLEX 6000 family. Cost without Sacrificing Performance FLEX 6000 device family achieves size efficiency without sacrificing utilization performance. example, stringent timing requirements
Figure OptiFLEX Architecture
compliance achieved through FastFLEX I/O, without dedicated element registers. FLEX 6000 device, 16-bit loadable counter runs MHz, more than double speed competing field programmable gate arrays, which typically slower. performance FLEX 6000 device family shown Table continued page
Table FLEX 6000 Family Features
Feature
Process geometry Supply voltage migration Gate count Logic elements User pins (maximum) Package options
EPF6010
5,000 10,000 144-pin TQFP
EPF6016
8,000 16,000 1,320 144-pin TQFP
EPF6016A
0.35 8,000 16,000 1,320 144-pin TQFP
EPF6024A
0.35 12,000 24,000 1,960
208-pin PQFP 208-pin PQFP 208-pin PQFP 208-pin PQFP 240-pin PQFP 240-pin PQFP 240-pin PQFP 256-pin 256-pin 256-pin
FastTrack Interconnect
FastFLEX
Column Interconnect
FLEX 6000
(not shown scale)
Interconnect
Interleaved LABs
Interconnect Column Interconnect
Local Interconnect
µPitch Technology
Local Interconnect
Bond Pads
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Feature Altera Ships New, Low-Cost FLEX 6000 Family continued from page Availability, Packaging Pricing 16,000-gate EPF6016 available now. first 0.35-micron, 3.3-V family member, 24,000-gate EPF6024A, will available January 1998. rest FLEX 6000 family expected available first half 1998. Contact your local Altera sales representative availability specific packages. Examples mid-1998 projected pricing quantities 50,000 units shown Table Conclusion Altera's FLEX 6000 device family provides designers with ideal programmable alternative gate arrays high-volume production. Using efficient OptiFLEX architecture, FLEX 6000 family delivers flexibility time-to-market programmable logic prices that competitive with gate arrays.
Figure Relative Size Comparison
Devices shown actual size.
further details, refer FLEX 6000 Programmable Logic Device Family Data Sheet (Configuring FLEX 6000 Devices), contact your local Altera representative.
Table FLEX 6000 Performance
Benchmark
16-bit loadable counter 16-bit accumulator 24-bit accumulator 16-to-1 multiplexer multiplier, 4-stage pipeline 8-bit, 16-tap parallel finite impulse response (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) 16450 universal asynchronous receiver/transmitter (UART) target with wait state
Used
1,162
Speed Grade
MSPS MSPS
Speed Grade
MSPS MSPS
1.06
Table FLEX 6000 Volume Price Projections
Device
EPF6010 EPF6016 EPF6016A EPF6024A
Note
Process
micron micron 0.35 micron 0.35 micron
Projected Pricing 50,000 Units
$6.00 $7.50 $7.00 $10.00
Gate Array Pins
FLEX 6000 Pins
Note: Prices U.S. dollars direct orders.
Site License Authorization Codes
Beginning with MAX+PLUS® version 8.1- scheduled ship September 1997-you obtain MAX+PLUS Site License authorization code world-wide web. Simply Altera's site http://www.altera.com/es fill registration form. Your authorization code will e-mailed within minutes. Using Internet fast easy started with MAX+PLUS software.
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Devices
Devices Tools 240-pin power quad flat pack (RQFP)packages. first quarter 1998, Altera expects provide devices 356-pin 600-pin ball-grid array (BGA) packages. Built 0.35-mm, quad-layer-metal (QLM) process, EPF10K100A will pin-compatible with current FLEX devices 240-pin RQFP 356-pin packages. instance, will able migrate from current 3.3-V, triple-layer-metal (TLM) EPF10K50V device higher density without changing your board layout.
&TOOLS
FLEX
Altera Increases FLEX Performance August, Altera announced plans increase FLEX® performance introducing new, faster speed grade devices. These performance increases will allow Altera continue lead high-density programmable logic performance. Contact your local Altera sales representative more details regarding speed grade devices. FLEX Pricing Availability June Altera reduced prices FLEX devices 49%. This price direct result advances process technology reduced size cost. price cuts high-density FLEX family have been among most aggressive industry, making cost these devices competitive with gate arrays. Since introduction 1995, 100unit list price 50,000-gate FLEX 10K/FLEX 10KA device dropped from $995 $99. FLEX devices available variety quad flat pack (QFP), ball-grid array (BGA), pin-grid array (PGA) packages. Sample 100-unit pricing shown below:
FLEX Price Reductions Note
Device
EPF10K100GC503-4 EPF10K70RC240-4 EPF10K50VRC240-4 EPF10K50RC240-4 EPF10K40RC208-4 EPF10K30RC208-4 EPF10K20TC144-4 EPF10K10LC84-4
9000
9000A Update MAX® 9000A family, manufactured 0.5micron, triple-layer-metal process, will offer speeds fast family pin-compatible with 9000 family will offer reduced power consumption. family also supports Altera's MultiVolt interface, making 9000A devices ideal mixed-voltage systems. following table shows 9000A device availability.
9000A Device Availability
Device
EPM9320A EPM9320A EPM9400A EPM9480A EPM9560A
Fastest Availability 84-Pin 208-Pin 240-Pin 356-Pin (ns) PLCC RQFP RQFP
October 1997 1998 1998 1998 September 1997
100-Unit 100-Unit Percent Price Price Reduction
$595.00 $261.00 $195.00 $195.00 $117.00 $87.50 $43.50 $22.00 $445.00 $195.00 $99.00 $145.00 $92.00 $70.00 $34.00 $19.00
7000
7000S Pricing Availability June Altera reduced prices 7000S devices 49%. This price direct result advances process technology reduced size costs. latest price reductions 7000S family result continuing process continued page
Note: Prices U.S. dollars suggested resale.
EPF10K100A Coming Soon Altera plans ship 100,000-gate EPF10K100A November 1997. Initially, this device will offered
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Devices Tools Devices Tools continued from page improvements increased production volumes. Examples 100-unit pricing shown below:
7000S Price Reductions
Device
EPM7256SRC208-15 EPM7192SQC160-15 EPM7128SLC84-15 EPM7064SLC44-10
Conventional 7000S Device Programming program 7000S devices using Altera's Master Programming Unit (MPU), MAX+PLUS software, appropriate programming adapter. ordering codes these adapters shown below:
7000S Devices that Support Socketed Programming
Devices
7000S devices 100-pin PQFP packages 7000S devices 100-pin TQFP packages EPM7128S EPM7160S devices 160-pin PQFP packages
100-Unit Price
$68.50 $42.00 $18.75 $9.70
100-Unit Percent Price Reduction
$51.00 $31.00 $11.25 $5.00
Ordering Code
PLMQ7000-100NC PLMT7000-100NC PLMQ7128/160-160NC
Note: Prices U.S. dollars suggested resale.
Faster 7000S Speed Grades 7000S family faster than ever with 6-ns 7.5-ns speed grade devices. following table shows speed grades availability.
7000S Device Availability
Device
EPM7064S
EPM7192S devices 160-pin PQFP PLMQ7192/256-160NC packages
Third-party programmers such programmers from Data Microsystems also support socketed programming 7000S devices. 7000 Product Transitions
Package
44-pin PLCC 44-pin TQFP 100-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10,
Availability
October 1997
EPM7128S
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP
Altera migrating existing 7000 devices from 0.65-micron process 0.5-micron process. Evaluation packets containing device samples documentation available from your local Altera sales representative. following table outlines process migration schedule.
7000 Migration Schedule, Note
Device
EPM7256S EPM7256E EPM7192S EPM7192E EPM7128S EPM7128E EPM7064S EPM7064
EPM7192S EPM7256S
160-pin PQFP 208-pin RQFP
Reference
PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9708 PCN9703 ADV9708 Complete
Date
September 1997 November 1997
Process
0.5-micron 0.5-micron 0.5-micron 0.5-micron 0.5-micron
7000S Supports Altera plans begin shipping 7000S devices that support automated test equipment (ATE) beginning September 1997. Products that support have last character ordering code, e.g., EPM7128SQC100-7F. Contact your local Altera sales representative information availability lead times 7000S devices that support ATE.
October 1997 September 1997
Notes: This process transition will result changes data sheet parameters ordering codes. Altera provides advisories process change notices. Altera world-wide site these reference documents.
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Devices Tools
5000 Classic
Product Transitions Altera migrating existing 5000 Classicdevices from 0.8-micron process 0.65-micron process. Evaluation packets containing device samples documentation available from your local Altera sales representative. Table outlines process migration schedule. Altera programming adapters required program 0.65-micron 5000 devices (0.65micron Classic devices require adapters). Altera will exchange existing EPM5032, EPM5064, EPM5130 programming adapters adapters free. These adapters backwards-compatible support existing revisions. Table lists existing 5000 adapters that exchanged adapters. Contact your local Altera representative more information.
Table Product Migration Schedule
Description
5000 devices fabricated
MAX+PLUS
Improvement High-Density Compilation Times MAX+PLUS version significantly reduces compilation times required FLEX devices. designs that target FLEX 8000 devices FLEX devices with 50,000-gates, MAX+PLUS version provides compilation times that times faster than previous version MAX+PLUS software both UNIX workstations. designs that target large FLEX devices 250,000 gates), compilation times faster. table below. Watch additional product announcements with MAX+PLUS version 8.1.
MAX+PLUS Compilation Improvements
Density Improvement Median Median Factor Compilation Time Compilation Time MAX+PLUS MAX+PLUS Version Version (minutes) (minutes)
21.24 183.75 8.41
Reference
9407 9515
Device
Date
3,000 logic elements (LEs) 8,000 9,000 9,000 10,000
EPM5032 Complete EPM5064 October 1997 EPM5128 Complete EPM5130 September 1997 EPM5192 Complete
0.65-micron process 9606
Note
Classic devices fabricated
9510 9607
EP6xx EP9xx EP18xx
Complete Complete Complete
MAX+PLUS Version Ship September 1997 MAX+PLUS version provides host features continuing effort provide value customers. This latest release MAX+PLUS significantly improves timing-driven compilation capability support designers want create high-density designs. Additional features this version include:
0.65-micron process 9621
Notes: Data sheet parameters ordering codes will change. Altera world-wide site advisories process change notices. Devices manufactured 0.65-micron process must programmed with programming adapters.
Table 5000 Replacement Adapters
Existing Adapter
PLEJ5064 PLMJ5064 PLEG5130 PLEJ5130 PLMJ5130 PLEQ5130 PLMQ5130
Adapter
PLMJ5064A PLMJ5064A PLMG5130A PLMJ5130A PLMJ5130A PLMQ5130A PLMQ5130A
HP-UX 10.10 support Packed register support FLEX 6000 family Internal global support FLEX family
Altera's software maintenance program keeps upto-date with latest features gives access newest devices. more information purchase software maintenance agreement, contact your local Altera representative.
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Devices Tools
Discontinued Devices
recent months, Altera announced that various products will discontinued (see table below). Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera sales representative. Selected ADVs, PDNs,
Discontinued Device Ordering Codes
Device Family
FLASHlogic 5000 Classic FunctionSpecific
complete listing discontinued devices also available Altera's world-wide site http://www.altera.com. Rochester Electronics, aftermarket supplier, offers support many discontinued Altera products. Contact Rochester Electronics (508) 462-9332 more information.
Device
EPX880 EPX8160 (all packages, temperature grades, speed grades) EPX740 (all packages, temperature grades, speed grades) EPM5032SC-15 EPM5016 (all packages, temperature grades, speed grades) EP220, EP224, EP312, EP324 (all packages, temperatures, speed grades) EPS448, EPS464 (all commercial industrial temperature grades; military devices have earlier last order last shipment dates)
Last Order Last Shipment Reference Date Date
6/30/97 3/31/97 6/30/97 3/31/97 3/31/97 3/31/97 6/30/98 9/30/97 12/31/97 9/30/97 9/30/97 9/30/97 9625 9516 9624 9516 9516 9516
Altera Publications
Altera publications available from Altera Literature Services. Individual documents available Altera world-wide site. Document part numbers shown italics.
FLEX 6000 Programmable Logic Device Family Data Sheet A-DS-F6000-02 Describes FLEX 6000 device architecture, features, operating conditions, pin-outs. (Configuring FLEX 6000 Devices) A-AN-087-01 Describes passive serial, passive serial asynchronous, Configuration EPROM modes configure FLEX 6000 devices. Programming Test Language Specification A-SP-JAM-01 Provides overview technical information language. (Using Language Embedded Processor) A-AN-088-01 Discusses language achieve benefits in-system programmability (ISP) with embedded processors. In-System Programmability Handbook M-HB-ISP-01 Contains current technical literature insystem programmability feature available Altera 9000 7000S families. Microperipheral MegaCore Function Data Book A-DB-MEGA-02 This revised version provides information a8259 programmable interrupt controller, well
information existing Altera microperipheral MegaCore functions. FLEX Embedded Programmable Logic Family Data Sheet Supplement A-DSS-F10K-2.4 Summarizes device capacitance timing specifications FLEX devices. MegaCore Function Parameterized Generator/ Checker Data Sheet A-DS-CRC-01 Describes parameter port values fullyparameterized Altera MegaCore function. Altera Digital Library CD-ROM P-CD-ADL-02 This revised version provides electronic version current Altera technical literature. FLEX Devices: Density Leader M-TB-022-01 FLEX Power Consumption M-TB-023-02 Advantages M-TB-024-01 Using OpenCore Evaluation Feature M-TB-025-01 FLEX pci_a: Complete Solution M-TB-026-01 Evaluating FLEX 6000 Performance M-TB-027-01 Advantages Altera ISP-Based CPLDs M-TB-028-01 Early/Late Gate Synchronizer Megafunction A-SB-017-01 Function Controller Megafunction A-SB-024-01 Host Controller Megafunction A-SB-028-01
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Technical
ARTICLES
Implementing Encoder Using Functions
GENERIC (LPM_WIDTH LPM_DIRECTION "RIGHT") PORT (data datacode, clock clk, shiftin datain, load eq(7), shiftout datax); count lpm_counter GENERIC (LPM_WIDTH PORT (clock clk, eq); PROCESS BEGIN datacode ((datain q(7)) q(7) DOWNTO (q(4) q(3)) q(3) DOWNTO 1)); PROCESS;
devices grow density, designs will more prebuilt functions, such functions from library parameterized modules (LPM). This article describes create encoder using functions. implementation written VHDL, other written Altera Hardware Description Language (AHDLTM). both implementations, serial data enters shift register. When shift register full, counter will coding 8-bit word will take place. Then, 8-bit word shifted serially datax port more data enters shift register (the datax port provides coded output). data stream constant, therefore, handshaking required. MAX+PLUS VHDL example references library statements shown blue text. Generic Statement describes parameters function. AHDL example uses Include Statements (shown blue text) import contents Include File containing Function Prototypes functions. Instance Declaration (shown text) implements instance function.
VHDL Encoder
LIBRARY ieee; ieee.std_logic_1164.ALL; LIBRARY lpm; lpm.lpm_components.ALL; ENTITY coder PORT datain, STD_LOGIC; datax STD_LOGIC); coder; ARCHITECTURE coder SIGNAL std_logic_vector(7 DOWNTO SIGNAL datacode std_logic_vector(7 DOWNTO SIGNAL std_logic_vector(15 DOWNTO BEGIN shift lpm_shiftreg
AHDL Encoder
INCLUDE "lpm_shiftreg.inc"; INCLUDE "lpm_counter.inc"; SUBDESIGN 'encoder' (clk, datain INPUT; datax OUTPUT;) VARIABLE shift lpm_shiftreg WITH (LPM_WIDTH LPM_DIRECTION "RIGHT"); count lpm_counter WITH (LPM_WIDTH BEGIN Connect ports 8-bit shifter shift.clock clk; shift.shiftin datain; shift.load count.eq7; shift.data[] ((datain shift.q7), shift.q7, !shift.q[6.5], (shift.q4 shift.q3), shift.q3, !shift.q[2.1]); datax shift.shiftout; Connect counter count.clock clk; END;
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Technical Articles
Configuring FLEX 6000 Devices
EPC1 Configuration EPROM microprocessor configure FLEX 6000 devices using following configuration schemes:
Configuration mode, configuration controlled microprocessor. Configuration begins with microprocessor driving nCONFIG high. microprocessor then asserts inputs FLEX 6000 device; these inputs must remain asserted until configuration initialization complete. microprocessor places configuration DATA input FLEX 6000 device pulses FLEX 6000 device. rising edge nWS, FLEX 6000 device latches data drives RDYnBSY indicate that processing data. While data being processed, microprocessor perform other system functions. microprocessor monitor CONF_DONE INIT_DONE ensure successful configuration. microprocessor sent configuration data CONF_DONE does become asserted, FLEX 6000 device must reconfigured. error detected during configuration, FLEX 6000 device drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration. Alternatively, Auto-Restart Configuration Frame Error option turned MAX+PLUS software, FLEX 6000 device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure FLEX 6000 device. FLEX 6000 device initialize itself mode. Therefore, CONF_DONE asserted device initializes before data sent. microprocessor stop sending configuration data when CONF_DONE asserted. Figure shows configuration circuit Figure shows state device during configuration, initialization, user modes. Arrows show which signal transitions dependent other transitions. mode used configure multiple FLEX 6000 devices. Multi-device configuration similar single-device configuration, except that FLEX 6000 devices cascaded. After first FLEX 6000 device configured, nCEO asserted,
Configuration EPROM Passive serial (PS) Passive serial asynchronous (PSA)
Configuration EPROM passive serial configuration schemes similar Configuration EPROM passive serial configuration schemes used configure FLEX 8000 FLEX devices. This article focuses scheme, configuration method that supported only FLEX 6000 devices. Configuration EPROM Configuration built-in clock EPC1 Configuration EPROM device controls configuration FLEX 6000 devices. Configuration EPROM device large enough configure FLEX 6000 device, configure multiple FLEX 6000 devices with more EPC1 Configuration EPROM devices. Programming support EPC1 Configuration EPROM available Altera Master Programming Unit (MPU) thirdparty programmers. mode, FLEX 6000 devices controlled clocked with following configurations:
BitBlaster download cable ByteBlaster download cable Microcontroller other intelligent interface
BitBlaster ByteBlaster download cable generates low-to-high transition nCONFIG initiate configuration. programming hardware then places configuration data DATA FLEX 6000 device time. data clocked into FLEX 6000 device until nCONFIG goes high. programming hardware used FLEX configuration mode, multi-device JTAG configuration programming mode. configure multiple FLEX 6000 devices with programming hardware connecting nCEO device subsequent device. other configuration pins connected FLEX 6000 devices chain. FLEX 6000 device CONF_DONE pins must tied together, that FLEX 6000 devices initialize enter user mode same time.
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Technical Articles which asserts second device, causing begin configuration. FLEX 6000 device CONF_DONE pins tied together, that FLEX 6000 devices initialize enter user mode simultaneously. Additionally, device detects error, entire chain will stop configuration because nSTATUS lines tied together. additional information FLEX 6000 devices, refer (Configuring
Figure FLEX 6000 Configuration
CONF_DONE nSTATUS MSEL
FLEX 6000 Devices) FLEX 6000 Programmable Logic Device Family Data Sheet.
Timing Parameters
Symbol
STATUS CF2ST1 ST2WS
Parameter
nCONFIG pulse width nCONFIG pulse width nCONFIG high nSTATUS high nSTATUS high first rising edge nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge
Units
FLEX 6000 Device
CF2WS CSSU WS2B BUSY
Microprocessor
pulse width rising edge RDYnBSY RDYnBSY pulse width
DATA nCONFIG RDYnBSY
RDY2WS RDYnBSY rising edge falling edge CF2CD CF2ST0
nCONFIG CONF_DONE high nCONFIG nSTATUS
Figure Timing Waveform
tCFG tCF2ST1
nCONFIG nSTATUS CONF_DONE DATA
tRDY2WS tCSSU tCF2WS tST2WS
tDSU
tWSP
tWS2B tBUSY
RDYnBSY
tSTATUS tCF2ST0 tCF2CD
User I/Os INIT_DONE
High-Z
Notes: Upon power-up, nSTATUS held five microseconds. Upon power-up, CONF_DONE low. After configuration, state nCS, nWS, RDYnBSY depends design programmed into
FLEX 6000 device. Device pins user mode.
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Technical Articles
Introducing Open-Standard Programming Test Language
coalition leading programmable logic device (PLD) manufacturers, programming equipment makers, test equipment manufacturers recently announced programming language, called JamTM, that compatible with in-system programmability (ISP)-capable PLDs. language planned submitted industrystandard language Joint Electronic Devices Engineering Council (JEDEC). Altera Cypress Semiconductor support language method simplifying ISP. Also endorsing language standardization programming equipment vendors Microsystems Data Corporation, well test equipment manufacturers Asset InterTech Corporation, GenRad Corporation, Gopel Electronic, JTAG Technologies, Teradyne Corporation. Addresses Dilemma Currently, in-system programming plagued proprietary file formats, vendor-specific programming algorithms, large file sizes, long programming times. result confusing array options, poor return investment design manufacturing engineers trying implement using PLDs. language addresses each these issues providing software-level standard ISP. standard vendor-independent, produces small file sizes, reduces programming times. While created Altera, language will freely licensed interested parties. Brian Moyer, chairman this JEDEC 23.1 subcommittee, said language will considered next JEDEC meeting. Importance In-system programmability important designers PLDs because offers distinct time-to-market advantages throughout product life-cycle. example, with ISP, design revisions prototyping stage compiled programmed into device within minutes. production, simplifies manufacturing flow allowing devices programmed during board testing with automated test equipment (ATE), minimizing coplanarity quad flat pack (QFP) packages reducing need store programmed devices inventory. addition, systems using ISP-capable devices easily upgraded field downloading configurations
modem other data links. There three standard programming methods:
Download cable Embedded processor
download cable method been most popular with designers expected remain near future. What Language? language allows creation single file that specifies both data programmed into device algorithm required accomplish programming. language supports methods well standard programmers, which used program devices bulk. language consists parts, Composer Player. Composer writes files that contain user data programming algorithm device. Player interprets file manages JTAG port program devices. instruction includes JTAG-based algorithmic instructions. These elements create universal language tools that address PLDs programming methodologies. Figure addition, language addresses issues associated with current programming solutions, including smaller file sizes, faster programming times, ability work with existing future devices manufactured different processes. Smaller File Sizes Currently, file formats used ISP: "bed nails" vectors JTAG instructions. vectors simple, low-level design representation ideal testing. JTAG instructions ASCIIbased files that generally created silicon vendors. However, both methods create large files, making them impractical some design flows using ISP. example, file size critical embedded processor, which must manage both design data programming algorithm. same time, fully expanded vectors impractical environment. instance, fully expanded code required program 128-macrocell device typically exceeds Mbytes size. contrast, file same 128-macrocell device would about
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Technical Articles
Figure Flow Using Language
Vendor Specific Vendor Platform Independent Platform Specific
Composer
File (.jam)
Player
JTAG Device
guarantee that every device been adequately programmed, which challenging requirement because programming pulse exponential function oxide thickness EEPROM, FLASH, EPROM processes. Therefore, programming pulses specified orders magnitude longer than given device require. language allows required programming pulse width determined real-time reading from each device. Devices that require short pulse programmed quickly, while ensuring that devices requiring longer pulse will meet requirements. average this technique reduces programming times approximately factor Conclusion In-system programmability increasingly important feature systems designers manufacturers seeking shorten time-to-market. While several methods programming reprogramming use, they have drawbacks terms file size programming times. language addresses these concerns and, open standard, would benefit silicon vendors, manufacturers, programmers.
Target Device
JTAG Chain
JTAG Device
Kbytes. This file, created using compression ratios 50:1, comparable size Programmer Object File (.pof) generated Altera's MAX+PLUS software. Faster Programming Times longer takes system manufacturers program device, more expensive testing becomes. Current methods require that silicon vendors provide programming pulse time that long enough
Frequently Asked Language Questions
With release MAX+PLUS version June 1997, Altera began supporting open-standard programming test language called Jam. language designed devices that support insystem programmability (ISP). This article answers some common questions about language. What Language? language interpreted language optimized programming devices standard IEEE 1149.1 controller (i.e., JTAG interface). This interpreted language supports both existing ISP-capable devices, small interpreter code file size, provides faster programming times, silicon vendor- platform-independent, open standard that freely licensed. would Language? language could used designer programming JTAG-compliant ISP-capable device. Whether device programmed with proprietary
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download cable, embedded processor, automated test equipment (ATE), language provides efficient quick solution. Language? Many existing programming vector formats used with ISP-capable devices large difficult work with. many instances, size these existing vector format files measured Mbytes because they support data compression algorithmic instructions. small size files eliminates this problem. Language? Contact your local Altera sales representative receive Developers authorization code enabling support within MAX+PLUS version 8.0. also download Internet http://www.altera.com/jam.
Technical Articles
Customer Training Brings Speed
Altera's Customer Training Department revised expanded course offering. Classes created specifically meet different experience levels, provide realistic design examples labs, offer sound, realistic advice hardware design techniques software settings. These one-day sessions give knowledge that might otherwise require months trial error work. Introductory courses ideal designers beginning Altera devices. will learn about architecture features Altera device families, access these features with MAX+PLUS software, analyze design results. Discussions include basic recommendations design layout software settings. experienced Altera users interested gaining higher speed utilization, advanced courses focus fitting performance specific architectures. These classes contain more labs than introductory courses. Faster paced more challenging, advanced labs require knowledge MAX+PLUS software well basic understanding Altera device family architectures. Valuable both beginners experienced users, Designing with MAX+PLUS explores features MAX+PLUS software, including design entry with Text Editor Graphic Editor, Floorplan Editor, Timing Analyzer, Simulator well synthesis fitting. users discover what MAX+PLUS software offer, experienced users learn about software options that they have used before. Altera also offers VHDL AHDL courses experience levels. These classes cover basic syntax program structure, inferring instantiating elements, creating overall design with languages. Instructors emphasize common problems coding, particularly VHDL course. summary available courses shown below. also find more detailed information registration form Altera's world-wide site http://www.altera.com.
Introduction Altera's Device Families Introduction Altera's FLEX Device Families Advanced Design Techniques Altera's Device Families Advanced Design Techniques Altera's FLEX Device Families Designing with MAX+PLUS Designing with MAX+PLUS using AHDL Designing with MAX+PLUS using VHDL
Advantages
designers seek take full advantage capacity performance high-density PLDs, such Altera's FLEX family, design methodology evolved. Instead using traditional schematic-based design techniques, designers turning modern design techniques that hardware description languages (HDLs), megafunctions, library parameterized modules (LPM). functions offer many advantages, especially when designing with FLEX devices. LPM? allows create architectureindependent designs, while still maintaining silicon efficiency. Instead spending time replicating standard logic functions, using functions enables focus adding value your design. Using also frees from deciding target architecture until late design flow. Design entry simulation architecture-independent; device targeted during logic synthesis fitting. part EDIF standard, supported wide range tools. additional information about download synthesizable simulatable models functions, refer worldwide http://www.edif.org. Currently, standard contains functions. Each function parameterized, i.e., parameters customize module your design needs. example, LPM_PIPELINE parameter used with multiplier, lpm_mult, specify number pipeline stages used. Altera, member EIA's committee, broadest software support vendor, shown Table
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Technical Articles Parameterized Multiplier Example Multipliers basic building blocks that used wide variety applications, from digital modulation image compression. Multiplier performance
Table Modules
Module
lpm_abs lpm_add_sub lpm_and lpm_bipad lpm_bustri lpm_clshift lpm_compare lpm_constant lpm_counter lpm_decode lpm_ff lpm_fsm lpm_inpad lpm_inv lpm_latch lpm_mult lpm_mux lpm_or lpm_outpad lpm_ram_dq lpm_ram_io lpm_rom lpm_shiftreg lpm_ttable lpm_xor
multiplier pipelined multiplier nonpipelined multiplier pipelined multiplier non-pipelined multiplier pipelined multiplier non-pipelined multiplier pipelined
critical because often limits overall system performance. Table compares unsigned multiplier performance FLEX devices. Using function lpm_mult MAX+PLUS tools, create multiplier size minutes. maximum performance, lpm_mult pre-defined parameter, LPM_PIPELINE, that allows automatically pipeline multiplier. modifying LPM_PIPELINE, easily optimize speed efficiency your multiplier application.
Table Multiplier Comparison
Logic FLEX FLEX 8000 FLEX 6000 Speed Grade Speed Grade Speed Grade (MHz) (MHz) (MHz)
Supported Altera
Note
Note
Notes: Source: Altera Applications. multiplier large FLEX 8000 FLEX 6000 devices.
Nova Engineering Introduces Megafunction Development System
AMPP partner Nova Engineering introduced Constellation FLEX Hardware Development System megafunction companion. system ideal real-time hardware verification, rapid prototype development, reconfigurable computers/accelerators. Constellation PLD-based, hardware development system with modular architecture that easily molded into prototype configuration. This system delivers flexibility ease necessary rapid prototype development. low-cost, off-theshelf product that provides support wide range Altera's FLEX devices, including 3.3-V 5.0-V devices. FLEX development board operate standalone configuration expanded include additional PLDs analog subsystems. Modular interconnects provide "plugand-play" access high-speed converters, creating base development system communication, signal processing, data acquisition, control, graphics products. more information, Nova Engineering's site http://www.nova-eng.com.
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Questions
&ANSWERS
DATA0 used user mode FLEX designs?
What problems occur Iomega software hardware system with MAX+PLUS version 7.1?
DATA0 cannot used user mode FLEX designs. avoid conflicts between configuration user mode, FLEX DATA0 dedicated configuration pin. DATA1, DATA2, DATA3, DATA4, DATA5, DATA7 pins pins user mode because these pins used configuration modes.
MAX+PLUS version installation fail have Iomega software hardware installed your system. remove Iomega software hardware, MAX+PLUS software will install correctly. While reinstall Iomega software hardware after MAX+PLUS version installation, should never MAX+PLUS software guard Iomega drive simultaneously. MAX+PLUS software guard connected Iomega drive, software guard will destroyed.
drive pins Altera device before power-up?
Applying power inputs most devices before power-up cause latch However, apply power inputs FLEX 10KA devices before power-up (except EPF10K130V EPF10K50V devices).
Intel-format Hexadecimal File (.hex) program EPC1 Configuration EPROM device?
define hexadecimal number using MAX+PLUS VHDL? following example shows define hexadecimal number using MAX+PLUS VHDL:
should program EPC1 Configuration EPROM devices with Files. must Programmer Object File (.pof) program EPC1 Configuration EPROM devices, regardless whether using Altera third-party programming hardware.
LIBRARY ieee; ieee.std_logic_1164.ALL; ieee.std_logic_arith.ALL; ENTITY PORT( STD_LOGIC_VECTOR DOWNTO hex; ARCHITECTURE BEGIN following line will convert hexadecimal value STD_LOGIC_VECTOR VHDL 1993. x"FC"; following line will convert hexadecimal value STD_LOGIC_VECTOR VHDL 1987. DOWNTO <=TO_STD_LOGIC_VECTOR (x"FC");
program revision EPC1 Configuration EPROM using Data programmers version 5.3?
program revision EPC1 Configuration EPROMs using Data programmers version 5.3, will receive device errors. This problem corrected Data programming software version 5.4, which available from following sources: Data site (ftp.data-io.com) Data Bulletin Board Service (BBS) (206) 882-3211
Revision EPC1 devices have date codes "yCxxxx" marked device, where letter number. example, date code AC9707, device revision device.
provide licenses multiple applications using same license file? following guidelines explain license multiple applications using same license file.
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Questions Answers Ensure that host specified each license file same. version lmgrd different between applications, latest version. However, application uses lmgrd pre-version 3.0, application must licensed separately with copy lmgrd.
MAX+PLUS version higher, perform following steps Compiler:
Choose Global Project Device Options (Assign menu). Turn Voltage option. Choose
After these requirements met, following format combined license file:
SERVER <host name> <host <TCP/IP port number> DAEMON <daemon application <path/daemon file name> DAEMON <daemon application <path/daemon file name> DAEMON <daemon application <path/daemon file name> FEATURE <feature name> <daemon> <version> <expiration date> <authentication code>
cannot perform this action MAX+PLUS version 7.22 lower. obtain correct timing parameters using these MAX+PLUS software versions, refer appropriate device family data sheet. Substitute tOD2 tOD1 proper delay.
single SERVER line gives TCP/IP port number used applications when accessing licensing information. Specifying multiple license files LM_LICENSE_FILE environment variable using operator indicates that separate TCP/IP ports should used communication. individual DAEMON lines, required applications being licensed, listed order. lmgrd will start daemons order which they listed. list FEATURE lines order after DAEMON lines. After application daemon started, FEATURE lines read.
"blind interrogation" devices JTAG chain accomplished?
IEEE 1149.1-1990 specification provides optional IDCODE instruction mode that permits blind interrogation devices JTAG chain. Upon power-up, device that supports IDCODE will automatically load IDCODE instruction into instruction register. device that does support IDCODE will automatically load BYPASS instruction into instruction register. After power-up, blind interrogation accomplished shifting data from data register. device that supports IDCODE will shift 32-bit value with least significant (LSB) device that does will shift BYPASS register. determine device supports IDCODE, simply check whether first shifted "0." additional information refer (JTAG Boundary-Scan Testing Altera Devices).
Multi-Device JTAG Chain command turned (JTAG menu) programming devices JTAG chain, checksum will appear MAX+PLUS Programmer because each device individual checksum (there checksum entire JTAG chain). However, view checksum individual devices JTAG Chain turning MultiDevice JTAG Chain command selecting each programming file individually. instruct MAX+PLUS Compiler generate timing Simulator Netlist File (.snf) device that supports mixed-voltage interface with MultiVolt feature?
obtain checksum device JTAG chain?
program 7000S device with 7000E Programmer Object File .pof)?
Yes, program 7000S device with 7000E POF. 7000S device features superset 7000E device features. Therefore, program 7000S device with 7000E POF, MAX+PLUS software will automatically disable superset features 7000S device. This programming (often called cross-programming) supported MAX+PLUS software, well third-party programmers such programmers from Data (http://www.data-io.com) Microsystems (http://www.bpmicro.com).
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Altera
VIEWPOINT
Pricing Roadmap Shows Steeper Reductions
While ASIC suppliers provide variety information tools help designers determine performance integration density, sometimes difficult designers obtain volume price projections. This difficulty somewhat ironic, device price significant factor up-front decision process system designer. fact, several recent surveys both programmable logic ASIC users have shown that device price commonly been identified most critical factor influencing device selection. price leader, Altera more focused than ever providing designers with necessary insight pricing, well technical attributes both existing future products. Over next three years, Altera anticipates acceleration cost reduction that will lead price cuts much annually. value using high-density programmable logic high volume expected increase from current level about gates dollar about 5,000 gates dollar year 2000 (see Figure These price reductions, combined with traditional time-tomarket risk reduction benefits PLDs, will serve further increase high-density PLDs volume applications where gate arrays were once used exclusively. Process Technology Advances Lead Size Reductions Altera been among industry leaders developing advanced process technologies. Since 1992, Altera's SRAM process geometry exhibited average linear shrink nearly year, compared industry average 11%. Altera already begun 0.25-micron process development plans release devices using this process first half 1998. Altera also plans launch project this year with wafer manufacturing partners, Taiwan Semiconductor Manufacturing Corporation (TSMC), develop 0.18micron SRAM process geometry production late 1999. Further size reductions obtained with addition metal layers circuit design. continuous interconnect structure Altera PLDs optimally leverages multilayer metal layout (see Figure Current Altera devices fabricated three-layer metal process, Altera plans ship devices using four-layer metal process later this year. Five-layer metal process development also underway 1998. Advanced Device Packaging Technology process geometries continue shrink, device packaging will take added importance. Because device packaging expected become increasing percentage total device cost, reducing package cost will become Altera's objectives. Altera working with packaging assembly partners develop lower-cost, production-worthy packages. Altera
Cliff Tong Senior Director, Product Marketing
Altera expects target process technology 0.18-micron year 2000.
value using highdensity programmable logic high volume will increase from current level about gates dollar about 5,000 gates dollar year 2000.
Figure Altera Value Pricing Trend
5,000
3,000
Gates Dollar
2,000
1994 1995
1996
1997
1998
1999
2000
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Altera Viewpoint also researching variety advanced packaging, including types ballgrid array flip-chip packages. ASIC designs, bond limitations often pacing item size perunit cost. Until recently, amount core logic been primary factor determining size cost. With acceleration process technologies, Altera PLDs becoming "pad limited," where size longer constrained total number gates, bond-pad pitch. Altera technology forefront programmable logic suppliers offering bonding pitch recently introduced FLEX 6000 devices, aggressively developing advanced bonding pitch next-generation, 0.25-µ process devices. Other Technological Improvements addition process geometry advanced packaging, Altera will evaluate other technological improvements lower device costs. Ongoing improvements circuit redundancy greatly enhance product yield, leading lower unit cost. Additional refinement continuous interconnect structure will further enhance device performance size, while maintaining routability. Continued investment advanced synthesis placement routing algorithms will allow further gains device resource usage. Price Projections Device pricing critical factor system design process. During next three years, Altera expects both FLEX family prices decrease greatly. FLEX device pricing expected fall much annually; device pricing macrocell projected fall annually. example, projected volume price Altera's 100,000-gate EPF10K100 device $140 1997; 1998, expected drop $50; year 2000, pricing this device projected (i.e., 5,000 gates dollar). Figure
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Figure EPF10K50 Size Comparison
Triple-Layer Metal 1.00
Triple-Layer Metal 0.78
0.35 Quad-Layer Metal 0.32
0.25 0.18 Five-Layer Five-Layer Metal Metal 0.19 0.12
Note: This value indicates normalized size. shown actual size.
Figure Projected Price Evolution 100,000-Gate PLDs (EPF10K100)
$350
Volume Price Projections
$140
1996
1997
1998
1999
2000
Conclusion Price reductions often larger than Dramatic feature size anticipated market. reductions expected future, Altera will advanced process decrease cost technologies further reduce size increase device density costs, which permits even lower prices performance. well dramatic increases device density, performance, functionality. Advanced packaging, proprietary circuit redundancy, improved development tools accelerate increasing value programmable logic solution. Figure Gate Array "Squeeze" combination flexibility faster Programmable Standard time-to-market gives Logic Cell users increasingly attractive Covers Highest complexity alternative Gate design starts Lowest unit cost Array traditional gate-array Provides fastest high volume time-to-market solutions highvolume applications (See Figure
August 1997
Customer
"New faster processors started hitting market every months just didn't have engineering bandwidth create design develop product every year." -Bill Mohat, Senior Design Engineer, Bailey Controls
Application
Bailey Controls Uses Megafunctions Solve Challenge
Bailey Controls, part international Elsag Bailey Process Automation N.V. group, needed create industrial controls product that enabled processor upgrading without imposing costly product redesign burdens. They found solution working with Eureka Technology, independent megafunction developer specializing architecture-independent megafunction solutions. Challenge engineers Bailey Controls were caught difficult situation: they needed ability easily upgrade microprocessors their industrial control products have resources completely redesign their single-board system. years, Bailey Controls designed products based Motorola 68000 family microprocessors proprietary ASICs. certain point, typical product life cycle five eight years using specific processor," said Bill Mohat, senior design engineer. "But faster processors started hitting market every months just didn't have engineering bandwidth create design develop product every year." Managers engineers decided they needed develop entirely product line. Designing ability upgrade without obsoleting entire printed circuit board (PCB) would require uncoupling custom elements from microprocessor, including proprietary networks channels. same time, Bailey Controls staff decided off-the-shelf hardware much possible remain with Motorola 68000 family. these requirements, they faced limited engineering resources. meet basic criteria, design needed that both processor clock-rate independent. peripheral component interconnect (PCI) bus-a common, complex technology-fit criteria, unfamiliar Bailey engineers. Finally, Bailey staff settled PCI-to-68030 bridge that would enable them create modular system enabling easy upgrades. Bailey engineers looked number alternatives implementing interface. However, general-purpose devices failed provide necessary flexibility. addition, they studied hardware solutions developed other divisions their parent company Elsag Bailey Process Automation, found these solutions demanding engineering resources meet specific needs project. Megafunction Solution Altera field applications engineer (FAE) worked with Bailey programmable logic solutions familiar with companies participating Altera Megafunction Partners
ALTERA MEGAFUNCTION PARTNERS PROGRAM
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Customer Application Program (AMPPSM), alliance independent developers. suggested Bailey work with Eureka Technology Altos, California, company that specializes PowerPC controller megafunctions. wanted generic interface possible else it," said Mohat. "Eureka took interface de-multiplexed They about dozen registers inside megafunction instead found standard products. And, they software hardware this project ground with minimum trouble. talked Simon (Eureka President) asked some changes. wanted multiple base address registers interrupt certain way. megafunction-containing requirements-that could dropped into Altera device turn into interface." with most products, there were final questions answer before system ready production. "Our PowerPC processor very abusive when there were back-toback transfers different boards, Eureka's megafunction mistakenly forwarded wrong data byte," said Mohat. made phone call Simon three hours later code e-mail. later design running." entire relationship with Eureka conducted through e-mail over telephone. Figure shows prototyping endproduct hardware developed Bailey using Eureka's megafunction. Looking Forward Mohat knows that megafunctions will vital future Bailey products. "Megafunctions designs going created over next years," said. more more people start selling larger pieces intellectual property-either form megafunctions, VHDL Verilog source code-designers will more pieces integrate them. simply don't have time resources anymore." first pass with Eureka's megafunction easy successful that Bailey went back Eureka directly next generation product-which just easy successful. megafunction only saved Bailey valuable engineering time, also cost less than designing solution inhouse, according Mohat. appears easier grab ASSP piece," said. "But unless you've worked with bus, don't understand fiendishly complex standard products don't eliminate that complexity. It's cheaper megafunctions when costs considered."
"Megafunctions designs going created over next years," Mohat said. more more people start selling larger pieces intellectual property-either form megafunctions, VHDL Verilog source code-designers will more pieces integrate them."
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Technical Articles
Altera's Failure Analysis Service
Altera offers Failure Analysis Service, which designed perform detailed analysis suspected failing devices. main goal Altera's Failure Analysis Service resolve these problems quickly. Altera recognizes that timely failure analysis critical meet time-to-market needs today's designers. Altera's Failure Analysis Service only includes device examination, also helps troubleshoot device-related issues. Resolving issue quickly, without requiring devices sent Altera analysis, helps Altera® devices your systems with greater ease. more difficult issues, Altera will analyze device determine cause failure. Altera will then inform cause failure, well suggest ways prevent failure from occurring future. Failure Analysis Capabilities Altera Applications your local Altera sales office. will review failure detail, even able resolve issue immediately. cannot resolve issue immediately device analysis warranted, will issue Evaluation Return Materials Authorization (ERMA) send Failure Analysis Kit. ERMA number authorizes send devices directly Altera failure analysis. would like credit devices, credit request form included Failure Analysis Kit. Failure Analysis Failure Analysis quickly safely return devices Altera analysis. Failure Analysis (see Figure contains following items:
pre-addressed, pre-paid Federal Express Altera uses state-of-the-art equipment failure package send failing devices Altera analysis. Depending type failure reported, Altera perform number tests resolve issues, Figure Device with Delamination including full C-SAM test non-destructively checks device delamination. Delamination (separation from molding compound) caused improper solder reflow techniques improper handling functional timing moisture-sensitive devices. This figure shows device with delamination. more information, refer tests, C-mode (Reflow Soldering Guidelines Surface-Mount Devices). scanning acoustic microscopy (C-SAM), scanning electron microscopy, emission microscopy, x-ray, liquid crystal testing. Figures
Using Altera's Failure Analysis Services Altera's failure analysis services, first contact your Altera Failure Analysis Specialist (FAS), been trained failure analysis techniques initiate failure analysis. unsure contact your FAS, contact
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Technical Articles
Figure Emmission Microscope Shows Leakage Pins
Emission microscopy isolate specific location failure. this test, device loaded with test vectors "exercise" device. emission microscope detect excessive current, pinpointing damaged circuitry. This figure shows results emission microscope test; high current leakage normally shown red, this publication, location shown with arrows.
Appropriate device packaging protect device during shipment Instructions questionnaire obtain more detailed information regarding failure completed form required processing) 3.5-inch diskette send back design, programming, simulation files (the diskette also includes soft copy questionnaires) Credit request form (must completely filled receive credit five devices)
Failure Analysis Results Altera will confirmation upon receipt FedEx package. initial analysis typically performed within three working days receipt devices Altera. initial production test results faxed directly you. further testing required, will keep informed progress failure analysis until issue closed with final report. final reports written results reviewed with ensure issue resolved your satisfaction.
Figure Test Shows Spiking
Altera also scanning electron microscope (SEM) analyze device. this figure, test found spiking under metal caused electrical overstress.
Altera provides this Failure Analysis Service part commitment quality customer service. Approximately half devices sent Altera failure analysis good devices. Thus, sending devices Altera without first fully checking setup pattern delay resolution issue. questions comments regarding Altera's Failure Analysis Services, please contact your Altera fas@altera.com.
Figure Failure Analysis Contents
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Advantages EABs Applications
FLEX embedded array blocks (EABs) provide significant advantages numerous applications. example, peripheral component interconnect (PCI) designs gain important benefits on-device first-in first-out (FIFO) function implemented FLEX EABs using megafunction. Importance FIFOs Without pre-built FIFO function, must choose three alternatives, each which drawbacks:
device FIFO function implemented FLEX EABs. Maximum Speed Including FIFO with interface allows operate maximum speed. Without FIFO buffer data, local side would have operate same speed, i.e., speed local side. FIFO provided with pci_a MegaCorefunction, example, allows operate maximum operating data rate MHz, even when local side cannot transfer data same rate. also architecture FLEX devices implement larger on-device FIFO buffers needed. Larger FIFO buffers support larger burst transfers therefore higher throughput. example, Altera's next generation functions will allow designers include on-device FIFO large 1,024 bytes (using EABs) EPF10K30 device still have EPF10K30 logic elements (LEs) available logic. Conclusion Using FLEX EABs implement on-device FIFO function design offers distinct advantages. With on-device FIFO, operate maximum speed, without concern speed local side. complete design, including FIFO, accommodated single device. Valuable logic conserved user-defined needs. Altera's FLEX architecture megafunctions offered Altera Altera Megafunction Partners Program (AMPP) provide winning combination. further information about Altera's solution, refer Master/Target MegaCore Function with Data Sheet contact your local Altera sales representative.
Operate local side interface same speed external FIFO second device Implement internal FIFO using logic
many applications, technically possible operate local side interface same speed bus. Even possible, overall cost high, higher operating frequency means faster, more expensive devices, more complicated printed circuit board (PCB) design. Using external FIFO function separate device leads higher costs, increased power consumption, increased space. problems result from converting logic into implement internal FIFO function. implementing FIFO function FPGA, example, unpredictable timing these devices makes almost impossible convert logic still meet rigorous timing requirements. Also, using logic RAM, less logic available other features, such integrating local side functionality into PLD. contrast, Altera's FLEX devices impose such tradeoff; neither speed area lost when
Altera Power Play Scores
June Design Automation Conference (DAC) Anaheim, Altera showcased "Power Play" solution, which combines cutting-edge high-density devices with advanced megafunctions powerful design tools. Over 1,000 designers visited Altera's booth, which featured hands-on demonstrations from Altera ACCESSpartners.
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Altera News
Altera Target Applications
Target Applications provides solutions designers' application-specific needs. Target Applications leverages MegaCore functions functions from Altera Megafunction Partners Program (AMPP) provide integrated solutions that deliver significant time-to-market benefits. complete Target Applications solution includes megafunctions documentation that critical these functions working in-system. Altera Target Applications focuses following areas:
Altera World Expo
Altera will participating International Conference Signal Processing Technology (ICSPAT) World Expo September through Diego. Altera engineers will present papers, Pipelined Adaptive Filters Altera PLDs Processor Core FLEX 10K, will co-present PLD-Based FFTs PLDBased Solution Cable Modem with AMPP partner Integrated Silicon Systems. These papers will presented FPGAs session. Altera will also showcasing FLEX solution World Expo floor. Stop booth latest demonstration Altera's solution.
FLEX building blocks imaging functions wireless broadband communications interfaces Universal serial (USB) Communications Data communications telecommunications Asynchronous transfer mode (ATM)
Altera Moved
July 1997, Altera moved corporate headquarters. contact Altera Altera Corporation Innovation Drive Jose, 95134 Telephone: (408) 544-7000 http://www.altera.com
Several interface functions have been developed recently, including:
AMPP partner Sapien Technology produced function node controller AMPP MegaCore functions
Future interface applications will include functions supporting I2C, CANbus, FireWire (IEEE 1394) interfaces. summary current interface functions shown table below.
Interface Functions
Function
Master/Target Interface Target Interface Master/Target Interface Target Interface Master/Target Interface Node Controller Function Controller
Source
Altera MegaCore Function Eureka Technology Eureka Technology Applications Applications Sapien Technology Sapien Technology
7000 Beats Kasparov
1997, reigning world chess champion bested computer. IBM's chess-playing computer Deep Blue defeated Garry Kasparov, reigning Grand Master, 2.5. This computing triumph also victory 7000 family; Altera 7000 devices were used construction Deep Blue. Kasparov valiant struggle against Deep Blue 7000, Deep Blue, powered 7000 devices, victorious.
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Altera News
Every
Test-Drive Megafunctions with OpenCore Feature
unique, no-risk OpenCoreevaluation feature offered Altera allows test-drive MegaCore functions before purchase them. Altera's MegaCore functions reusable, synthesizable megafunctions that optimized Altera programmable logic devices (PLDs). Simply download MegaCore function from Altera world-wide site http://www.altera.com free charge. Then, instantiate megafunction MAX+PLUS file, simulate verify your design. Once your design completed, license MegaCore function obtain authorization code. With fully licensed version MAX+PLUS software generate programming files, EDIF netlist files, VHDL Verilog output files simulation thirdparty tools. addition Altera MegaCore functions, OpenCore feature allows test-drive megafunctions offered partners Altera Megafunctions Partners Program (AMPP). Contact AMPP partners directly obtain encrypted AMPP megafunction file OpenCore evaluation authorization code. OpenCore feature allows compile megafunction determine megafunction's size speed. Once your design completed, license megafunction from AMPP partner obtain authorization code generate programming files other output files. Figure shows design flow when using either Altera MegaCore function AMPP megafunction.
Figure Design Flow Altera MegaCore Function AMPP Megafunction
Break project into functional blocks identify megafunctions that useful. Evaluate megafunctions using OpenCore feature.
Third-Party Programming Support
Data Microsystems provide programming hardware support selected Altera devices. Algorithms supplied Data I/O's Keep Current Express-Bulletin Board Service (KCE-BBS) Microsystems' BBS. Programming support Configuration EPROM, 9000, 7000 devices shown table below. information subject change.
Third-Party Programming Hardware Support
Device
EPC1064 EPC1213 EPC1 EPM7032 EPM7064 EPM7096 EPM7128E EPM7128S EPM7160E EPM7192E EPM7192S EPM7256E EPM7256S EPM9320 EPM9400 EPM9480 EPM9560
Data
Microsystems
Note Note Note Note
Notes tables: These devices supported Data 2900 version 5.5, 3900 version 5.5, UniSite version programmers. These devices supported Microsystems programmers version 3.25. Microsystems plans support 9000 devices future. Contact your local Altera representative Microsystems more information.
License megafunction. Instantiate megafunction, compile, simulate design. Generate programming files perform hardware verification.
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Every Issue
Altera Programming Hardware Support
following tables contain latest programming hardware information Altera devices. correct programming, software version shown "Current Software Versions" below. PLM-prefix adapters used only with Master Programming Unit (MPU). Table
Table Altera Programming Adapters (Part Note
Device
EPC1064, EPC1064V, EPC1213 (all FLEX 8000 devices) EPC1 (FLEX FLEX 8000 devices) 9000A EPM9320
Table Altera Programming Adapters (Part Note
Device
EPM7064
Package
J-lead (68-pin) J-lead (84-pin) PQFP J-lead (68-pin) J-lead (84-pin) PQFP
Adapter
PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100
EPM7096
Package
DIP, J-lead TQFP J-lead
Adapter
PLMJ1213 PLMT1064 PLMJ1213 PLMJ1213
EPM7128S, EPM7160S EPM7128, EPM7128E
PQFP (160-pin) PLMQ7128/160-160NC J-lead (84-pin) PLMJ7000-84 PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 J-lead PLMJ7000-84 PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 PQFP (160-pin) PLMQ7192/256-160NC PQFP PLMG7192-160 PLMQ7192/7256-160
EPM7160, EPM7160E
RQFP (208-pin) PLMR9000-208NC RQFP (240-pin) PLMR9000-240NC PLMG9000-280 J-lead (84-pin) PLMJ9320-84 RQFP (208-pin) PLMR9000-208 J-lead (84-pin) PLMJ9400-84 RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240
EPM7192S EPM7192, EPM7192E EPM7256S EPM7256E
EPM9400
RQFP (208-pin) PLMQ7256-208NC MQFP, RQFP PQFP PLMG7256-192 PLMR7256-208 PLMQ7192/7256-160
EPM9480 EPM9560
RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240 RQFP (208-pin) RQFP (240-pin) RQFP (304-pin) PLMG9000-280 PLMR9000-208 PLMR9000-240 PLMR9000-304
Table provides programming information BitBasterserial ByteBlasterparallel port download cables.
Table Programming with BitBlaster ByteBlaster
Device
FLEX FLEX 8000 FLEX 6000 9000
7000S EPM7032, EPM7032V
PQFP (100-pin) PLMQ7000-100NC TQFP (100-pin) PLMT7000-100NC J-lead PQFP TQFP J-lead TQFP PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44
Package
packages packages packages packages packages
Hardware
PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER PL-BITBLASTER PL-BYTEBLASTER
EPM7064S
Current Software Versions
latest versions Altera software products shown below:
7000S
MAX+PLUS version (PC, SPARCstation, 9000 Series 700, RISC System/6000 platforms)
Notes tables: Refer Altera 1996 Data Book device adapter information 5000 Classic devices. Altera offers adapter exchange program 0.8-micron EPM5032, EPM5064, EPM5130 programming adapters. "Product Transitions" page this newsletter more information. These devices shipped carriers.
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Altera Device Selection Guide
current information Altera FLEX 10K, FLEX 8000, 9000, 7000 devices listed here. Information other Altera products located Altera 1996 Data Book. Contact Altera your local sales office current product availability.
FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K50V EPF10K50A EPF10K70 EPF10K100 EPF10K100A EPF10K130V EPF10K130A EPF10K250A 250,000 600-Pin BGA, 599-Pin 12,624 12,160 40,960 130,000 600-Pin BGA, 599-Pin 7,120 6,656 32,768 70,000 100,000 240-Pin QFP, 503-Pin 240-Pin (2), 356-Pin (2), 503-Pin PGA, 600-Pin 189, 189, 274, 406, 4,096 5,392 3,744 4,992 18,432 24,576 40,000 50,000 20,000 30,000
GATES
10,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin 144-Pin TQFP, 208-Pin 144-Pin TQFP, 208-Pin QFP, 240-Pin 144-Pin TQFP (2), 208-Pin QFP, 240-Pin QFP, 356-Pin 240-Pin 208-Pin QFP, 240-Pin 240-Pin QFP, 356-Pin BGA, 403-Pin 240-Pin
PINS
107, 107, 107, 147, 107, 147, 189, 147, 189, 274,
TEMP. SPEED GRADE
FLIPLOGIC FLOPS ELEMENTS
1,344 1,968 2,576 3,184 1,152 1,728 2,304 2,880
BITS
6,144 12,228 12,228 16,384 20,480
Notes: devices currently available. Contact Altera FLEX 10KA device availability. Available FLEX 10KA devices only. available FLEX 10KA devices.
FLEX 8000 Devices
DEVICE EPF8282A GATES 2,500 PIN/PACKAGE OPTIONS 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP EPF8282AV EPF8452A 2,500 4,000 100-Pin TQFP 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP EPF8636A 6,000 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP EPF8820A 8,000 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP PINS 118, 118, 112, 120, TEMP.
SPEED GRADE
FLIP- LOGIC FLOPS ELEMENTS
144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 112, 120, 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 112, 120, EPF81188A 12,000 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP EPF81500A 16,000 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
Notes: Four pins dedicated inputs. indicates 3.3-V voltage supply.
148, 148, 148, 181, 181, 181,
1,188
1,008
1,500
1,296
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FLEX 6000 Devices
DEVICE
EPF6010 EPF6016 EPF6016A EPF6024A
GATES
10,000 16,000 16,000 24,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 208-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 208-Pin QFP, 240-Pin PQFP, 256-Pin 208-Pin QFP, 240-Pin PQFP, 256-Pin 208-Pin QFP, 240-Pin PQFP, 256-Pin
PINS
117, 117, 117, 171, 199, 117, 171, 199, 117, 171, 199, 117, 171, 199, 171, 199, 171, 199,
TEMP.
SPEED GRADE
FLIPFLOPS
1,320 1,320 1,320 1,320 1,960 1,960
LOGIC ELEMENTS
1,320 1,320 1,320 1,320 1,960 1,960
Notes: Four pins dedicated inputs. indicates 3.3-V voltage supply. faster commercial temperature speed grade devices de-rated operate over industrial temperature range.
9000 Devices
DEVICE
EPM9320 EPM9320A EPM9400 EPM9400A EPM9480 EPM9480A EPM9560 EPM9560A
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 304-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 304-Pin RQFP, 356-Pin
PINS
132, 132, 132, 132, 139, 139, 139, 146, 146, 146, 153, 191, 153, 191, 153, 191, 153, 191,
TEMP.
SPEED GRADE
-15, -10, -15, -10, -10,
Note: Four pins dedicated inputs.
7000 Devices
DEVICE EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032 EPM7032 EPM7032V EPM7032V EPM7032V EPM7064, EPM7064S EPM7064, EPM7064S EPM7064, EPM7064S EPM7064 EPM7064
(Part
MACROCELLS PIN/PACKAGE OPTIONS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP (2)/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP (2)/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP (2)/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP
PINS
TEMP.
SPEED GRADE (ns) (MHz) 178.6 90.9 76.9 90.9 76.9 62.5 90.9 76.9
continued page
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7000 Devices
DEVICE EPM7096 EPM7096 EPM7096 EPM7096 EPM7128E, EPM7128S EPM7128E, EPM7128S EPM7128E EPM7128E, EPM7128S EPM7128E EPM7160S EPM7160E, EPM7160S EPM7160E EPM7160E, EPM7160S EPM7160E EPM7192S EPM7192S EPM7192E EPM7192E, EPM7192S EPM7192E EPM7256S EPM7256S EPM7256E, EPM7256S EPM7256E, EPM7256S EPM7256E
(Part
MACROCELLS PIN/PACKAGE OPTIONS
68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP/TQFP 68-Pin PLCC (2), 84-Pin PLCC, 100-Pin PQFP/TQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (1), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (1), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (1), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (1), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP/TQFP (1), 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 208-Pin RQFP 208-Pin RQFP 160-Pin PQFP, 192-Pin (2), 208-Pin RQFP 160-Pin PQFP, 192-Pin (2), 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP
PINS
TEMP.
SPEED GRADE (ns) (MHz) -10(P) -10(P) -12(P) -12(P) 90.9 76.9 90.9 76.9 62.5 90.9 76.9 62.5 90.9 76.9 62.5 90.9 76.9 62.5
132, 132, 132, 132, 132,
Notes: Available 7000S devices only. available 7000S devices.
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Notes:
MAX+PLUS software manuals, contact Altera Customer Service your local distributor. also contact your local Altera sales office sales representative. Altera 1996 Data Book listing.
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