Altera introducing options high-density programmable logic devices (PL

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Altera introducing options high-density programmable logic devices (PL

Datasheet Thumbnail

Top Searches for this datasheet

ClockLock ClockBoost Circuitry High-Density PLDs
Altera introducing options high-density programmable logic devices (PLDs). ClockLock feature uses phase-locked loop (PLL) minimize clock delay skew within device, significantly increasing performance. ClockBoost feature increase clock frequencies much four times incoming clock rate, improving system performance. Combined, these enhancements provide significant breakthroughs system performance bandwidth. Figure1. Faster System Performance PLDs increase density, clock delay skew have greater impact performance. Historically, shield designers from effects clock skew, critical parameters such setup clock-to-output delays (tSU tCO) were padded. contrast, ClockLock circuitry uses synchronize clock lines, thereby minimizing clock delay skew. With easy-to-use
Figure Phase-Locked Loops (PLLs)
maintains phase delay between input clock internal oscillator. Dividing feedback signal provide clock multiplication.
Phase Comparator Voltage-Controlled Oscillator
ClockLock feature, Altera reduce clock delay skew programmable logic specifications, significantly improving performance. example, using ClockLock circuitry EPF10K100GL503-3DX device, designers likely worst-case respectively, increasing expected system performance more than 60%. This performance increase will help designers meet high-speed interface requirements future. Figure page Increased System Bandwidth Reduced Area ClockBoost circuitry enables clock multiplication Altera devices. Popularly used microprocessors, clock multiplier circuits allow external clock frequency "multiplied" inside device. With ClockBoost feature, designers have access both clock doubling option clock frequencies that tripled quadrupled some Altera devices. Figure page ClockBoost allows designers internal logic device four times faster than input clock frequency. This option useful digital signal processing (DSP) designs data compression algorithms, where complex data manipulation performed very high speeds. Through technique called time-domain multiplexing, ClockBoost feature allows designer enhance device area efficiency resource sharing within device. example, design that requires continued page
Primary Clock
Locked Clock
Delay
Frequency divider provides clock multiplication.
Frequency Divider
A-NV-Q396-01
Altera Corporation
News Views
August 1996
form
ion.
Contents
Features ClockLock ClockBoost Circuitry High-Density PLDs Altera Viewpoint: MegaCore Functions Complete Picture Customer Application: Altera Delivers Speed GigaNet AProtocol Engine Altera News Available: 1996 Data Book Advantages Hybrid Mixed-Voltage Systems Available: VHDL-Synthesizeable Functions Customer Training Courses Creating AMPP Megafunctions Target Applications Support Growing Strong Altera Spring Show Altera Dream Team Delivers Devices Tools Introducing ByteBlaster Download Cable Altera Improves FLEX Performance EPF10K30 Ships 240-Pin RQFP Package FLEX Speed Grade Device Availability EPF10K10 Packages Altera Introduces First 144-Pin TQFP Package Industrial-Temperature FLEX 8000 Devices
FLEX 8000 Prices Reduced EPM9560 Available 208-Pin RQFP Package EPM9560 Prices Reduced 7000S Availability EPM7192S Shipping Exchange Your 5000 Programming Adapter Free Product Transitions MAX+PLUS Version Available September Discontinued Devices
Technical Articles Building Complex Logic with FLEX EABs Using VHDL Designs Troubleshooting Problems with Questions Answers Every Issue Altera Publications Current Software Versions Altera Device Selection Guide Data Programming Support Software Utilities Programming Hardware Compatibility Request Altera Publications Access Altera Response Form
Submit questions ideas Altera Applications Department Attention: Martin 2610 Orchard Parkway Jose, 95134-2020 Tel: (408) 894-7000 Fax: (408) 954-0348 E-mail: n_v@altera.com
Altera, AHDL, AMPP, BitBlaster, ByteBlaster, Classic, ClockLock, ClockBoost, FastTrack, FLASHlogic, FLEX, FLEX 10K, FLEX8000, FLEX 8000A, FLEX DSP, 9000, 7000, 7000E, MAX7000S, 5000, MAX, MAX+PLUS, MAX+PLUSII, MegaCore, Altera Megafunction Partners Program, PLDasm, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: 3Soft registered trademark 3Soft Corporation. Verilog registered trademark Cadence Design Systems. Data registered trademark Data Corporation. Intel Paragon trademark Intel Corporation. AOC-12c Protocol Engine trademark Giganet Corporation. Windows, Windows 3.1.1, Windows registered trademarks Microsoft Corp. Synopsys registered trademark Synopsys, Inc. Viewlogic registered trademark Viewlogic Systems. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Forward-looking statements this newsletter made pursuant safe harbor provisions Private Securities Litigation Reform 1995. Investors cautioned that forwardlooking statements involve risks uncertainty, including without limitation risks dependence third-party wafer suppliers, intellectual property rights litigation, market acceptance demand Company`s products well general market conditions, competition pricing, development technology manufacturing capabilities. Please refer Altera`s Securities Exchange Commission filings, copies which available from Altera without charge, further information. Copyright 1996 Altera Corporation. rights reserved.
Printed recycled paper.
Altera Corporation
News Views
August 1996
ClockLock ClockBoost Circuitry High-Density PLDs continued from page 32-bit data path function running implemented with 16-bit data path function running internally MHz, achieving same functionality with nearly half logic resources requirements. Software Support Software support both ClockLock ClockBoost features planned MAX+PLUS version 7.0. enable ClockLock ClockBoost circuitry, designers will parameterized function (named CLKLOCK MAX+PLUS that permits specifications input frequency frequency multiplication factors. After design compilation, designer MAX+PLUS software functional timing simulation well timing analysis. support ClockLock ClockBoost circuitry-through Verilog VHDL models-will also available with MAX+PLUS version 7.0. Availability Initially, ClockLock ClockBoost features will available FLEX devices only. EPF10K100 will first device incorporate these options (planned release September 1996), followed additional FLEX devices. 7000S devices will introduced with ClockLock feature 1997.
Figure ClockLock Feature
ClockLock feature improves clock-to-output times because clock delay skew eliminated.
Output Delay
data1 CLKLOCK
Clock Delay Clock Delay
Skew
data2
Output Delay
Figure ClockBoost Feature
clock multiplier increases bandwidth data path without increasing board-level clock speed.
32-bit Data Path
16-bit
CLKLOCK
Data Path
Introducing ByteBlaster Download Cable
Designers require fastest performance during in-system programming newest Altera programming hardware, called ByteBlaster. ByteBlaster connects standard 25-pin parallel port downloads programming configuration data directly target device. ByteBlaster fully compatible with existing printed circuit boards that BitBlaster device programming. ByteBlaster programs MAX9000 7000 devices configures FLEX FLEX 8000 devices. also ByteBlaster with PLDshell Plus software program configure FLASHlogic devices. following table compares features ByteBlaster BitBlaster. more information ByteBlaster, refer ByteBlaster Download Cable Data Sheet.
ByteBlaster BitBlaster Comparison
Feature
Platforms supported In-system programming time (for EPM7128S) In-circuit reconfiguration time Data port seconds Fast
ByteBlaster
BitBlaster
workstation seconds Fast
25-pin parallel port RS-232 serial port
Altera Corporation
News Views
August 1996
Devices
&TOOLS
FLEX
FLEX Speed Grade Device Availability EPF10K10, EPF10K30, EPF10K100 devices available today speed grades. EPF10K50 EPF10K20 devices speed grades scheduled fourth quarter 1996. EPF10K40 EPF10K70 scheduled first quarter 1997. Contact your local Altera representative information pricing, further information FLEX family. following table summarizes device availability FLEX10K devices speed grade.
FLEX Device Speed Grade Availability
Device
EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100
Altera Improves FLEX Performance Altera improved performance FLEX devices. Devices speed grade available, devices speed grades contain performance improvements. FLEX10K device family leads industry density, with devices densities 100,000 gates. With performance enhancements, FLEX devices also offer speed leadership similar FLEX8000A devices.
Altera used following methodology demonstrate high-performance characteristics FLEX family: Selected nine circuits that represent typical programmable logic device (PLD) designs. Implemented circuits until device filled. Determined performance with MAX+PLUSII software.
Availability
October 1996 1996 1997
test results shown table "Performance Characteristics FLEX Devices" below.
EPF10K30 Ships 240-Pin RQFP Package Altera shipping EPF10K30 device 240-pin power quad flat pack (RQFP) packages. EPF10K30 embedded array-which contains 12,288 bits memory-can used implement on-chip complex logic functions without affecting resource utilization logic array speed.
Performance Characteristics FLEX Devices
Logic Benchmark EPF10K10
Data path Timer State Large state machine Arithmetic circuit 16-bit accumulator 16-bit counter Pre-scaled counter Memory Average performance
EPF10K10 Packages EPF10K10 will available 84-pin plastic J-lead chip carrier (PLCC) 144-pin thin quad flat pack (TQFP) packages later this year. pricing information, contact Altera Customer Marketing.
Performance Speed Grade Devices (MHz) EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
EPF10K100
Altera Corporation
News Views
August 1996
Devices Tools
FLEX 8000
Altera Introduces First 144-pin TQFP Package EPF8820A first Altera device offered 144-pin TQFP package. With 8,000 usable gates pins, EPF8820ATC144 support PCMCIA designs requiring higher density more pins than available with EPF8282A EPF8452A devices 100-pin TQFP packages. compact TQFP package ideal solution tight board designs that cannot accommodate 160-pin package. Initial quantities EPF8820A A-4, A-3, speed grades will available early October. Production volumes will available later this year. Industrial-Temperature FLEX 8000 Devices following industrial-temperature devices were recently added FLEX 8000 family. devices offered speed grade, providing 95-MHz, 16-bit counter performance.
Industrial-Temperature FLEX 8000 Devices
Device
EPF8282ATI100-3 EPF8452AQI160-3 EPF81188AQI208-3 EPF81500ARI240-3
9000
EPM9560 Available 208-pin RQFP Package EPM9560 device will available 208-pin RQFP packages third quarter 1996. 208-pin RQFP package replacement existing 208-pin ceramic quad flat pack (CQFP) package. EPM9560 devices 208-pin RQFP packages form, fit, functionally equivalent EPM9560 devices 208-pin CQFP packages.
Pricing EPM9560 devices 208-pin CQFP packages will same EPM9560 devices RQFP packages. ordering codes affected package substitution shown below.
9000 Ordering Code Changes
Existing Ordering Code
EPM9560WC208-20 EPM9560WC208-15 EPM9560WC208-20C EPM9560WC208-15C
Ordering Code
EPM9560RC208-20 EPM9560RC208-15 EPM9560RC208-20C EPM9560RC208-15C
Usable Gates
2,500 4,000 12,000 16,000
Package
100-pin TQFP 160-pin PQFP 208-pin PQFP 240-pin RQFP
EPM9560 Prices Reduced July Altera reduced cost selected speed grades EPM9560 device 10%. These price reductions reflect continuous improvement made possible increased sales volume.
FLEX 8000 Prices Reduced Maintaining leadership industry's most costeffective programmable logic family, Altera reduced price FLEX 8000 devices 55%. 100-unit pricing listed below.
Examples Reduced FLEX 8000 Pricing
Part Number
EPF8282ALC84-4 EPF8452ALC84-4 EPF8636ALC84-4 EPF8820AQC160-4 EPF81188AQC208-4 EPF81500ARC240-4
7000
7000S Availability Altera shipping production quantities EPM7192S device. Additional 7000S devices available engineering samples obtained from your local Altera sales representative. 7000S device availability shown below. Contact your local Altera sales representative release dates other 7000S devices.
7000S Device Availability
Device
EPM7256S EPM7192S EPM7128S EPM7064S
100-Unit Price
$17.50 $38.00 $58.00 $75.00 $89.00 $149.00
100-Unit Percent Price Decrease
$11.00 $17.00 $25.00 $37.00 $55.00 $79.00
Engineering Samples
Production Availability
1996 October 1996 1997
Note: Price U.S. dollars direct orders suggested resale.
metal-intensive architecture FLEX 8000 family utilizes 0.5-micron, triple-layer metal SRAM process provide high-performance low-cost required today's low-end ASIC designs.
EPM7192S Shipping Production quantities EPM7192S device 160-pin plastic quad flat pack (PQFP) packages
continued page
Altera Corporation
News Views
August 1996
Devices Tools EPM7192S Ships continued from page shipping. EPM7192S available both 10-ns 15-ns speed grades introductory 100-unit price $115.00 $82.00, respectively. EPM7192S, like 7000S devices, supports insystem programmability (ISP) through industrystandard JTAG test ports. Additionally, device open-drain output option pin- programming file-compatible with EPM7192 EPM7192E devices.
Product Transitions Altera migrating existing 5000 Classic devices from 0.8-micron process 0.65-micron process. evaluate qualify devices manufactured process, obtain evaluation packet (containing device samples, data sheets, process change notices, reliability data) from local Altera sales representative. Altera recommends verifying that your third-party programming hardware vendor modified programmers devices that have migrated 0.65-micron process. table below outlines migration schedule:
Product Migration Schedule
Description
5000 devices fabricated 0.65-micron process
5000 Classic
Exchange Your 5000 Programming Adapter Free Altera qualified 0.65-micron EPROM process 5000 devices migrating existing 0.8-micron 5000 devices 0.65-micron process. This change will facilitate long-term support MAX5000 family.
This migration will change 5000 ordering codes 5000 timing parameters shown 5000 Programmable Logic Device Family Data Sheet. However, programming adapters required program 0.65-micron devices. Altera will exchange existing EPM5032, EPM5064, EPM5130 programming adapters adapters free. These adapters backwards-compatible support existing revisions. table below lists existing adapters that exchanged adapters. Altera already completed exchange program EPM5128 EPM5192 programming adapters. Contact Altera's Customer Service Department your local Altera sales representative more information.
5000 Replacement Adapters
Existing Adapter
PLED5032 PLMD5032 PLEJ5032 PLM5032 PLES5032 PLEJ5064 PLMJ5064 PLEG5130 PLEJ5130 PLMJ5130 PLEQ5130 PLMQ5130
Reference
9407 9515 9606
Device
Date
EPM5032 1997 EPM5064 1997 EPM5128 Complete EPM5130 1997 EPM5192 October 1996
Note
Classic devices fabricated 0.65micron process 9510 9607
EP6xx EP9xx EP18xx
Complete September 1996 March 1997
Notes: This process transition will result changes data sheet parameters ordering codes. Devices containing must programmed with programming adapters. information obtain adapters, "Exchange Your 5000 Programming Adapter Free" this page.
MAX+PLUS
MAX+PLUS Version Available September MAX+PLUS version will available late September. addition support FLEX 10K, FLEX 8000, 9000, 7000S devices packages, this version will provide support Altera's ClockLock ClockBoost features, which currently available EPF10K100 devices.
MAX+PLUS version will also contain improved interfaces tools. Specifically, timing models used Synopsys performance prediction will improved generate more accurate results. addition, release will support Mentor Graphics QuickVHDL simulator. MAX+PLUS version maximize your design efficiency. pricing information details software maintenance agreements, contact your local Altera representative.
Adapter
PLMD5032A PLMD5032A PLMJ5032A PLMJ5032A PLMS5032A PLMJ5064A PLMJ5064A PLMG5130A PLMJ5130A PLMJ5130A PLMQ5130A PLMQ5130A
Altera Corporation
News Views
August 1996
Devices Tools
Discontinued Devices
recent months, Altera announced that various products will discontinued (see table below). Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera
Discontinued Device Ordering Codes
Device Family
FLEX 8000 7000 FLASHlogic 5000
sales representative. Selected ADVs PDNs also available Altera's world-wide site http://www.altera.com. Rochester Electronics, aftermarket supplier, offers support many discontinued Altera products. Contact Rochester Electronics (508)462-9332 more information.
Device
Military products (all 883B, DESC, military temperature grades) Military products (all 883B, DESC, military temperature grades) EPX780 (all packages, temperature grades, speed grades) EPX740 (all packages, temperature grades, speed grades) Military EPM5130W device Selected 5000 ordering codes EPM5016 (all packages, temperature grades, speed grades)
Last Order Date
10/31/96 10/31/96 6/28/96 3/31/97 10/31/96 9/30/96 3/31/97 6/28/96 10/31/96 3/31/97 6/28/96 9/30/96 3/31/97 10/31/96 3/31/97
Last Shipment Date
12/31/96 12/31/96 9/30/96 9/30/97 12/31/96 12/31/96 9/30/97 9/30/96 12/31/96 9/30/97 9/30/96 12/31/96 6/30/97 12/31/96 9/30/97
Reference
9513 9517 9513 9601 9516 9513 9609 9516 9516 9511 9513 9516 9518 9608 9608 9513 9517 9516
Classic
EP22V10, EP22V10E, EP310I, EP320I (all packages, temperature grades, speed grades) Military products (all 883B, DESC, military temperature grades) EP220, EP224, EP312, EP324 (all packages, temperature grades, speed grades) Selected EP6xx ordering codes Selected EP9xx ordering codes Selected EP18xx ordering codes
FunctionSpecific
EPS448, EPC1213 military (all 883B, DESC, military temperature grades) EPS448, EPS464 (all commercial industrial temperature grades; military devices have earlier last order last shipment dates)
Altera Publications
Altera publications available from Altera Literature Services, Altera Express, Altera world-wide site. Document part numbers shown italics. 1996 Data Book A-DB-0696-01 Provides comprehensive information about Altera's FLEX 10K, FLEX 8000, Configuration EPROM, 9000, 7000, FLASHlogic, 5000, Classic device families well MAX+PLUS development tools. 1996 Data Book also includes information device operation, product reliability, device timing models, package outlines. AMPP Catalog M-CAT-AMPP-01 Provides introduction Altera Megafunction Partners Program (AMPP),
Altera Corporation News Views August 1996
description each AMPP megafunction, listing corporation profiles contact information each AMPP partner. Gate Array-to-Programmable Logic Conversion User Guide A-UG-GARP-01 Describes Gate Array-toProgrammable Logic Conversion Kit, including supported technologies, design flow, Library Mapping Files, design guidelines, installation, MAX+PLUS design processing. FLEX Embedded Programmable Logic Family Data Sheet Supplement, version A-DSS-F10K-1.2 Provides updated timing parameters FLEX10K family.
Technical
ARTICLES
Building Complex Logic with FLEX EABs
Altera's FLEX devices first programmable logic devices (PLDs) contain embedded arrays, which allow designers quickly create, prototype, debug complex designs with many 100,000 gates. Unlike embedded functions gate array, FLEX10K embedded array fully programmable, giving designer complete control over functions programmed embedded array. FLEX embedded array composed series embedded array blocks (EABs), which used implement both memory complex logic functions. EABs also reconfigured on-the-fly, allowing designers modify portion design without disturbing operation rest device. This article provides examples implement complex logic functions FLEX EABs. However, many other functions implemented embedded array, including:
logic function. contains results functions rather than using algorithms calculate them. Example Trancendental Functions Waveform Generators used generate waveforms that repeat over time (e.g., sine waves). waveform generator implemented with counter that drives address input EAB, waveform output appears output EAB. Because bits wide, simultaneously generate waveforms. Multiple EABs cascaded generate additional waveforms. waveform irregular within period because created with LUT. This example describes generate sine wave using EAB. Transcendental functions-such sine, cosine, logarithms-are non-linear, they difficult compute using algorithms. more efficient implement transcendental functions looking results large LUTs, which implemented with EABs. When using implement transcendental function, input drives address input EAB, output appears data output. Each address location stores result input (e.g., result function implemented with input=10 stored address location 10). Rather than duplicating entries symmetric functions (e.g., cos(+n) cos(-n), sin(+n) -sin(-n)), transcendental functions sign determine whether output should inverted. compute sine function, example, stores values quadrant function. Based value input, logic element (LE) computes results other quadrants determining whether inputs outputs should inverted. Figure shows values quadrant sine function repeat rest function.
Multipliers Constant multipliers/vector scalars Digital filters Two-dimensional convolvers State machines Transcendental functions Waveform generators bit-to-10 encoders On-the-fly reconfigurable functions
more detailed information these applications, refer Product Information Bulletin (Implementing Logic with Embedded Array FLEX Devices). Implementing Logic Each flexible block with optional input output registers. assume following sizes with speed penalty: 1,024 2,048 bits. Logic functions implemented programming during configuration with read-only pattern, creating large look-up table (LUT). pattern reconfigured during device operation change
Altera Corporation
News Views
August 1996
Technical Articles Computing transcendental functions with produces high-resolution result, where resolution minimum change input change output. produces high-resolution results because implement functions with high numbers inputs, whereas cannot easily implement such complex functions. more entries that stored EAB, higher resolution. store 8-bit entries. Therefore, used calculate symmetric function effectively 1,024 8-bit entries because symmetric functions each entry times, once each quadrant function. example, computing sine wave with produces resolution 0.35°. increase precision resolution output transcendental function, multiple EABs used. increase precision, look eight most significant bits (MSBs) while another looks eight least significant bits (LSBs) result. increase resolution, EABs used emulate ROM, which provides 2,048 8-bit entries resolution 0.18°. After sine function been implemented, generate sine wave. counter drives input sine function, output digitized sine wave. This digital output driven digital-to-analog converter. sine wave used various functions. Example State Machines embedded array used implement highly complex state machines. Generally, more complex state machine becomes (i.e., more transitions has), more logic resources requires. number EABs required implement state machine function number states, inputs, outputs state machine-regardless complexity. Therefore, state machines with different number transitions same number states, inputs, outputs require same number EABs. address input combination bits representing inputs state machine current state. example, 16-state, 4-input, 4output state machine, signals representing inputs state machine drive ADDR[7.4], signals representing current state drive ADDR[3.0]. Each address input contains fields: outputs current state state bits indicating next state. Moore state machine design uses output registers EAB, whereas Mealy state inputs machine design uses register only inverted. address bits representing current state. Figure shows implementation 16state, 4-input, 4-output Moore state machine. also used implement sequencer, which state machine generates sequence signals. implement sequencer, counter drives address inputs EAB. defines operation sequencer storing appropriate outputs each count value. During operation, outputs outputs sequencer. Figure shows state machine implemented EAB. contents table control behavior state machine. example, state with state continued page
Figure Computing Sine Function
inputs outputs inverted.
outputs inverted.
only stores values quadrant; other quadrants produced inverting inputs and/or outputs.
Figure Implementing Moore State Machine
ADDR[3.0] Q[3.0]
Registered Outputs
Input
ADDR[7.4] Q[7.4]
Output
Altera Corporation
News Views
August 1996
Technical Articles
Using VHDL Designs
FLEX devices contain embedded array blocks (EABs) that configured large blocks RAM. these EABs VHDL design with functions from industry-standard library parameterized modules (LPM). MAX+PLUS Compiler version supports instantiation functions VHDL, which allows implement while preserving architecture-independence your design. functions parameterized, i.e., quickly easily change size and/or behavior RAM. functions have optional parameters that provide flexibility. following example shows instantiate memory function lpm_ram_dq VHDL design. This example shows instance block with synchronous inputs asynchronous outputs that 4bits wide words deep. When include statements highlighted blue, have declare function before using
LIBRARY ieee; ieee.std_logic_1164.ALL; LIBRARY lpm; lpm.lpm_components.ALL; ENTITY ramexa PORT inclock datain addr dout ramexa;
STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR DOWNTO STD_LOGIC_VECTOR DOWNTO STD_LOGIC_VECTOR DOWNTO
ARCHITECTURE ramexa BEGIN the_ram LPM_RAM_DQ GENERIC (LPM_WIDTH LPM_WIDTHAD LPMOUTDATA UNREGISTERED, LPM_ADDRESS_CONTROL REGISTERED, LPM_INDATA REGISTERED) PORT (DATA datain, inclock inclock, address addr, dout);
Troubleshooting Problems with
program 9000 7000S devices in-system with MAX+PLUS BitBlaster. workstation running MAX+PLUS sends data BitBlaster serial port; turn, BitBlaster sends data JTAG connector your printed circuit board (PCB). BitBlaster uses EPM7064 device perform data translation drive four JTAG pins required programming insystem (TCK, TMS, TDI, TDO). supplies power BitBlaster; power applied correctly, POWER status light will turn Perform following steps program devices with BitBlaster MAX+PLUS Choose Programmer (MAX+PLUS menu). Choose Hardware Setup (Options menu). following dialog appears:
Altera Corporation
News Views
August 1996
Technical Articles in-system programmability (ISP), following settings: BitBlaster required programming devices in-system with BitBlaster. Select appropriate port BitBlaster. Select baud rate that corresponds BitBlaster setting, choose Auto-Setup have MAX+PLUSII baud rate you. COM3 BitBlaster RS-232 port-or selecting COM2 when other hardware uses COM4-causes conflict. avoid conflicts, verify that other hardware using port that shares interrupts with BitBlaster. correct configuration using Auto-Setup, RS-232 port settings must correct BitBlaster must powered from your PCB. After have configured MAX+PLUS BitBlaster, begin programming. problems occur with BitBlaster (e.g., noise), MAX+PLUS issues error message. following table determine possible cause message solution.
Hardware Type Address RS-232 Port Baud Rate
Serial ports share interrupts: COM1 shares with COM3 COM2 shares with COM4. Therefore, have installed other hardware that uses COM1, selecting
Programming Error Messages Solutions
Error Message
Programming hardware busy
Possible Cause
BitBlaster receiving power. There RS-232 port conflict. baud rate selected MAX+PLUS does match BitBlaster setting. selected baud rate supported operating system.
Solution
Provide power BitBlaster through 10-pin header PCB. Select different port disconnect conflicting hardware. Ensure that baud rate MAX+PLUS matches BitBlaster dipswitch setting. Auto-Setup match baud rates. maximum baud rates supported are: Windows NT/95 Windows 3.11 Workstation 115,200 57,600 38,400
Unrecognized device socket empty
stuck high low.
Probe verify that signal levels acceptable.
TCK, TMS, pins have noise.
Probe TCK, TMS, valid signal levels noise. necessary, terminate TCK. Refer (High-Speed Board Designs) more information. Programmer, change device match device PCB. latest version MAX+PLUS obtain password program device. Probe verify that signal levels acceptable. Probe TCK, TMS, valid signal levels noise. necessary, terminate TCK. Refer (High-Speed Board Designs) more information. Ensure that held during programming.
Device version enabled
device specified MAX+PLUS Programmer does match device PCB. Your version MAX+PLUS does support chosen device, requires password program device.
Verify Error
stuck high low. TCK, TMS, pins have noise.
tied during programming.
Altera Corporation
News Views
August 1996
Technical Articles Building Complex Logic with FLEX EABs continued from page machine inputs equal state machine transitions state state with state machine inputs equal state machine transitions state These transitions indicated Figure well first fifth rows table below.
Figure State Machine Inputs
State machine input output values shown hexadecimal radix.
size state machine's required memory calculated from memory width memory depth. Memory width function number outputs number states; memory depth function number inputs number states. required memory space large into EAB, MAX+PLUS development software cascade multiple EABs create required memory space. Design Entry Altera's MAX+PLUS design software provides methods placing logic EAB. manually assign logic more EABs selecting piece logic turning Implement option. This method provides maximum control over design implementation. also direct MAX+PLUS automatically place logic into more EABs turning Automatic Implement option Global Project Logic Synthesis dialog (Assign menu). variety logic functions also implemented with Altera-provided macrofunctions. Conclusion FLEX devices first PLDs contain embedded arrays. FLEX embedded array, composed series EABs, enables designers implement complex logic functions single level logic. Using EABs implement logic functions results higher device utilization performance. flexibility makes adaptable variety specialized logic applications combinatorial functions.
values each state Figure shown following table.
State Machine Values
State
Inputs ADDR[7.4]
Current State ADDR[3.0]
Outputs Q[7.4]
Next State Q[3.0]
Available: 1996 Data Book
copy 1996 Data Book, contact your local Altera sales representative.
Altera Corporation
News Views
August 1996
Altera
VIEWPOINT
MegaCore Functions Complete Picture
Jack Ogawa Development Tools Marketing Manager density complexity programmable logic devices (PLDs) ASICs have outpaced improvements design process, widening "design gap." Designers require right tools efficiently create designs large devices. Specifically, design tools must address following needs:
Because lack commercially available megafunctions, some companies develop functions internally during course normal design activity, provide these functions other design engineers within same company. However, other companies have resources develop megafunctions inhouse. Altera addresses this need providing following functions:
Design flow-The design tools should integrated, requiring minimal overhead providing maximum flexibility. Compilation performance-Each design iteration should completed fast possible. Increased design abstraction-When using highdensity devices, designers often need move away from explicit, gate-oriented design highlevel descriptions. Design abstraction requires less verbose, more explicit description logic, which permits more gates designed over period time. Consequently, high-level hardware description languages (HDLs) such VHDL, Verilog HDL, Altera Hardware Description Language (AHDL) have become increasingly popular.
MegaCore functions-These Altera-provided functions internally developed, fully tested, supported MAX+PLUS well thirdparty tools. Altera Megafunction Partners Program (AMPP) functions-AMPP partners intellectual property (IP) vendors develop, market, support megafunctions. partners target select, fullytested functions Altera devices, such highlevel system functions, which used different architectures. AMPP functions supported MAX+PLUS third-party tools.
MegaCore Functions AMPP Functions MegaCore functions AMPP functions seemingly overlap because they address same market. However, Altera chooses develop megafunctions that complement Altera's core architectures; MegaCore functions focus specific areas only targeted Altera devices. contrast, AMPP functions cover broader range functional areas, retargeted variety architectures, provide migration path designer. MegaCore Functions
However, HDLs alone sufficient bridge design gap. large designs practical, another level abstraction design level required. Large building blocks, such megafunctions, provide this next level. Altera Provides Value Many functions reusable. Designers usually associate these reusable functions with digital design building blocks, such 74-series functions. Over time, however, these reuseable functions have grown complexity, beyond scope 74-series functions. With large, complex megafunctions-such peripheral component interconnect (PCI) interfaces, microprocessor peripherals, microprocessors-the design process faster more efficient.
Altera plans offer MegaCore functions ways: comprised related functions standalone functions. first available functions will
8237 controller 6402 UART 16450 UART 8251 UART continued page
Altera Corporation
News Views
August 1996
Customer
APPLICATION
Altera Delivers Speed GigaNet AProtocol Engine
Communications Intel Paragon Supercomputer Design Application: AOC-12c Protocol Engine Altera Products: EPF81188A, EPM7032, EPM7128E, EPM7160E, EPM7192E, EPM7256E, MAX+PLUS
GigaNet develops high-performance ATM-based protocol engines that interface supercomputers. OC-12c Protocol Engine designed Intel Paragon supercomputer allow customers communicate with Anetworks OC-12c, OC-48, OC-192 rates. Speed this design critical because interface needed OC-12c rates under worst-case conditions. designers also wanted flexibility scale design OC-192 rates through parallel implementations.
Industry: Product:
Choosing Programmable Logic Vendor GigaNet design team implemented much design programmable logic meet flexibility time-to-market demands. They chose specific devices based speed density requirements. needed register-intensive product calculating TCP/IP checksums 400MB second (MBPS), needed macrocell architecture incorporate wide state machines deep pipelines higher-level protocol algorithms," says David Follett, architect project. addition, having single programmable logic vendor essential because needed single toolset that well integrated with Viewlogic WorkView Plus board-level simulator," says Follett. Altera Provides Answer programmable logic vendors were considered during selection process, Altera only supplier that GigaNet's speed, density, tool requirements. final design incorporated Altera devices using clock frequencies from MHz. "The FLEX 8000 architecture ideal implementing fast checksum with multiple high-speed adders. Implementing Aalgorithm required speed particularly tricky large state machines, 7000 devices helped meet challenge," says Follett.
needed single toolset that well integrated with Viewlogic WorkView Plus board-level simulator." David Follett Project Architect
GigaNet OC-12c Protocol Engine
Altera Corporation
News Views
August 1996
Customer Application Benefits Tool Integration GigaNet designers expected Altera's MAX+PLUS software chip design some multi-chip functional simulation while using WorkView Plus verify larger blocks entire board. end, however, they used MAX+PLUS Simulator extensively functional timing simulation because well integrated with MAX+PLUSII design entry tools. "The integration tools best I've seen," says Follett. "The timing simulator provided very accurate information that allowed modify design obtain mandated speed." multi-chip simulation capability also allowed GigaNet team simulate functional block with nine chips verify both functionality timing parameters. timing information from MAX+PLUS then imported into WorkView Plus board-level simulation. Winning Solution FLEX 8000 7000 devices, together with MAX+PLUS software, provided winning solution GigaNet. "Altera only supplier that demand high density, blazing speed, well-integrated tools. MAX+PLUS enabled verify functionality, integrate many elements, validate aggressive speed requirements."
"The integration tools best I've seen," says Follett. "The timing simulator provided very accurate information that allowed modify design obtain mandated speed."
GigaNet AOC-12c Protocol Engine
AOC-12c Protocol Engine, transmit side processes data received from computer, segments into 53-byte Acells, sends network link. receiver then reassembles Acells received from network link, processes data, sends computer.
64-Bit, 50-MHz Computer Interface EPM7256E-12 EPM7032-6 Transmitter (Higher-Level Protocol Engine) EPF81188A-4 EPM7160E-10 Common Logic EPM7128E-10 Receiver (Higher-Level Protocol Engine) EPF81188A-4 EPM7128E-10
ASAR (Segmentation) EPM7192E-12
ALower-Level Protocols
ASAR (Reassembly) EPM7256E-12 EPM7192E-12 EPM7128E-10 EPM7032-6
SONET 0C-12c Link
Altera Corporation
News Views
August 1996
Questions
&ANSWERS
EPROMs 8-pin 20-pin PLCC packages, including EPC1.
Design received includes CD-ROM, don't have CD-ROM drive. install Design files? install reference designs Design CD-ROM, perform following steps:
would like assign constant Graphic Design File (.gdf). assign constant GDF?
function lpm_constant from library parameterized modules (LPM) make constant value available schematic. This function output, which constant that define. constant value defined parameter LPM_CVALUE; width constant value defined parameter LPM_WIDTH. also CONSTANT primitive specify constant value used GDF.
Insert CD-ROM into computer that does have CD-ROM drive. Insert blank diskette into drive Type following command prompt: c:\> copy <CD-ROM drive>: \pc\install.exe
control length carry chains used function such lpm_counter lpm_add_sub? example, have 32-bit adder that would like implement 16-bit carry chains. control length carry chains implemented functions function-byfunction basis performing following steps. Select function MAX+PLUS Text Editor, Graphic Editor, Hierarchy Display. Choose Logic Options (Assign menu). Choose Individual Logic Options. Individual Logic Options dialog box, select Auto Carry Chain drop-down menu box. Then, type value Max. Auto Length maximum carry chain length.
Remove first diskette insert second into drive Type following command prompt: c:\> copy <CD-ROM drive>: \pc\install.w02
then first diskette begin installation Design files.
Which FLEX device packages support 3.3-V pins with 5.0-V core? following packages support 3.3-V pins with 5.0-V core.
This adjustment will apply only selected function-not functions design.
FLEX devices pin-grid array (PGA) packages ball-grid array (BGA) packages 208-pin plastic power quad flat pack (PQFP RQFP, respectively) packages 144-pin TQFP packages
take advantage device-wide clear device-wide output disable options FLEX10K devices? FLEX devices, ability clear registers tri-state pins device. access these features, perform following steps: Select FLEX10K device family choosing Device command (Assign menu) choosing FLEX Device Family box. Choose Device Options open FLEX10K Individual Device Options dialog box.
FLEX devices 84-pin PLCC 240-pin RQFP packages support this feature.
Which Altera programming adapter should program EPC1 Configuration EPROM 8-pin 20-pin PLCC package? PLMJ1213 programming adapter with program Configuration
Altera Corporation
News Views
August 1996
Questions Answers also these features globally FLEX10K Global Project Device Options dialog (Assign menu) after selecting FLEX device family. device-wide clear option, turn Enable Chip-Wide Reset option. When this option turned MAX+PLUS adds called DEV_CLRn design. When this driven low, registers device cleared, device just powered MAX+PLUS print following message during compilation: Some registers powerup VCC. registers that power-up preset device-wide clear signal. device-wide output disable, turn Enable Chip-Wide Output Enable option FLEX Individual Device Options dialog box. MAX+PLUS will called DEV_OE design. When this driven low, pins device will tri-stated. This option electrically removes device from circuit, which useful debugging board without physically removing device. mapped lpm_ram_dq with parameters LPM_NUMWORDS LPM_WIDTH file name, iror signifies that both inputs outputs registered.
creating design FLEX device using Synopsys tools. ensure that when compile design with Synopsys Design Compiler, DFFE primitives correctly mapped DFFE primitives FLEX device? devices that contain DFFE primitives implemented silicon (FLEX10K, MAX9000, MAX7000 devices), code that synthesizes DFFE primitives. example: always (posedge clock) IF(enable) ELSE primitives will correctly shown following figure.
When would Altera genmem utility with hardware description language (HDL) simulator and/ Synopsys tools timing-driven synthesis? genmem utility produces file that behaviorially describes memory function (with extension Verilog .vhd VHDL). this file simulator functionally verify circuit. However, plan simulator, this file required. genmem utility also produces file with extension .lib, which contains timing information that Synopsys tools synthesize design with timing constraint. This file should added technology library Altera device using. However, using Synopsys tools timing driven synthesis accurate timing information-using report_timing command Synopsys tools-is necessary, then need .lib file technology library. When instantiate behavioral description memory that genmem creates, must same name that genmem assigns description. MAX+PLUS uses name memory function appropriate memory function. example, syn_ram_64x8_iror.v, Verilog module,
JTAG boundary-scan description language (BSDL) files available Altera devices?
JTAG BSDL files required describe JTAG circuitry within device. Altera provides BSDL files FLEX8000, MAX9000, MAX7000S, FLASHlogic devices. download selfextracting executable with JTAG BSDL files, called jtagbsdl.exe, from Altera site (ftp.altera.com) Altera BBS. BSDL files FLEX devices under development.
Altera Corporation
News Views
August 1996
Altera
Advantages Hybrid Mixed-Voltage Systems
Hybrid capability enables device inputs outputs support electrical requirements both 5.0-V 3.3-V devices. Because programmable logic devices often "glue" that ties various devices board together, high-performance programmable logic devices with hybrid capability provide ideal interface solution mixed-voltage systems. hybrid capability FLEX 10K, FLEX 8000, 9000, 7000, FLASHlogic devices makes these families excellent choice mixed-voltage interfacing. Figure Most 5.0-V FPGAs Cannot Drive 3.3-V Devices Because most 5.0-V field-programmable gate arrays (FPGAs) offer hybrid I/O, they produce undesirable results when driving 3.3-V devices. Some FPGAs have true CMOS outputs with high-level output voltage (VOH range 3.86 5.0V. However, maximum high-level input voltage (VIH) 3.3-V device Thus, outputs these FPGAs exceed maximum specification. Providing option outputs foolproof solution because reach mode, violating specification. most severe penalty violating specification latch-up, which destroy 3.3-V device. Additionally, excess current flow from 5.0-V power supply 3.3-V power supply through 5.0-V 3.3-V devices, potentially raising 3.3-V power higher level damaging other 3.3-V devices connected bus. Finally, driving input voltage higher than specified value adversely affect long-term reliability device. Figure2. solution when using FPGAs place 150- resistor between devices minimize current flow. While this patchwork solution help limit current, cannot ensure reliable operation because specification still met. Furthermore, placing extra resistors board inconvenient solution that require designer change board layout. 3.3-V FPGAs 5.0-V Tolerant
Figure Altera Two-Way Mixed-Voltage Interfacing
Altera Device
3.3-V Device
Logic
5.0-V Device
5.0-V 3.3-V signals drive input buffers.
3.3-V outputs drive 3.3-V 5.0-V devices.
Although some FPGA vendors promoting "pure" 3.3-V devices, customers designing mixed-voltage systems into problems with these devices because inputs 5.0-V tolerant. Regardless whether driving 5.0-V device CMOS NMOS output, maximum (5.0 respectively) exceed maximum device. Once again, specification violated, consequently, this
Altera Corporation
News Views
August 1996
Altera News configuration have same latchup, current flow, reliability issues previously discussed. Figure While Altera's current 3.3-V devices have similar limitations, hybrid capability Altera 5.0-V devices offers flexibility interface with inputs outputs both 3.3-V 5.0-V devices. Furthermore, future 3.3-V devices from Altera will offer 5.0-V tolerant inputs, making them suitable mixed-voltage systems. Altera Provides Mixed-Voltage Flexibility Altera provides broadest mixedvoltage product offering with FLEX10K, FLEX 8000, 9000, 7000, FLASHlogic device families. inputs these devices easily accommodate both 3.3-V 5.0-V signals, outputs these devices safely drive both 3.3-V 5.0-V devices without violating specification. Thus, this hybrid capability provides superior interface between 5.0-V 3.3-V devices.
Figure 5.0-V FPGAs with CMOS Output Cannot Drive 3.3-V Devices
FPGA
3.3-V Device
3.86
3.86 3.857
Figure 3.3-V FPGAs 5.0-V Tolerant
CMOS NMOS outputs exceeds maximum
NMOS Output
3.3-V FPGA
Maximum
CMOS Output
3.3-V FPGA
Maximum
MegaCore Functions Complete Picture continued from page
Conclusion Altera MegaCore functions, conjunction with AMPP functions, provide designers with viable "make buy" option large, complex digital systems. This option important designers want 100,000-gate PLDs, faced with increasingly stringent time-to-market demands. Altera committed providing designers complete solution highdensity programmable logic design expanding design capability beyond 100,000 gates.
6850 asynchronous communications interface adapter 8255 parallel controller
These functions will offered together Microperipheral MegaCore Library, priced $7,995. Maintenance agreements available, providing designer with access improvements library elements additional charge.
Altera Corporation
News Views
August 1996
Altera News
Available: VHDL-Synthesizable Functions
Altera provided synthesizeable VHDL models functions from library parameterized modules (LPM). With LPM, designer create architecture-independent designs without sacrificing silicon efficiency. VHDL models functions available through Electronic Design Interchange Format (EDIF) world-wide site http://www.edif.org. LPM: Powerful Tool industry-standard contains different functions-including adders, multipliers, memory functions-that easily placed logic design modified expand many dimensions. Designers duplicate functionality other design libraries that contain hundreds functions, which greatly simplifies design debugging tasks. allows designers create architectureindependent designs while still maintaining silicon efficiency. Designers specify architectureindependent functions schematics instantiate them hardware description language (HDL) files. software recognizes each function uses architecture-specific design techniques create most efficient design. Altera Increases Effectiveness Because generic synthesizeable description functions previously available, limited tools that supported natively. With VHDL models, tools silicon vendors that support process design containing functions. Designers tools synthesize, optimize, simulate designs implementing behavioral descriptions. VHDL description lpm_counter function shown below.
LIBRARY IEEE; IEEE.std_logic_1164.ALL; work.lpm_components.ALL; ENTITY count4 PORT data STD_LOGIC_VECTOR DOWNTO clock STD_LOGIC; clk_en STD_LOGIC; cnt_en STD_LOGIC; updown STD_LOGIC; sload STD_LOGIC; sset STD_LOGIC; sclr STD_LOGIC; aload STD_LOGIC; aset STD_LOGIC; aclr STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR DOWNTO count4; ARCHITECTURE count4 BEGIN LPM_COUNTER GENERIC (LPM_WIDTH PORT (data data, clock clock, clk_en clk_en, cnt_en cnt_en, updown updown, sload sload, sset sset, sclr sclr, aload aload, aset aset, aclr aclr, END;
Current Software Versions
latest versions Altera software products shown below:
MAX+PLUS version 7.0, available September 1996 (PC, SPARCstation, 9000 Series 700, IBMRISC System/6000 platforms) PLDshell Plus version only)
Altera Corporation
News Views
August 1996
Altera News
Customer Training Courses
Altera Customer Training Program enables designers maximize benefits Altera devices, including time-tomarket benefits lower system cost. lower cost increased silicon efficiency. Altera's training classes show efficiently silicon resources, which often permits additional logic placed into device, eliminating other devices their associated costs. Alternatively, design into smaller, less expensive device, providing reduced overall system cost. Altera offering customer training classes: FLEX class FLEX Synopsys class. FLEX Training This one-day course introduces FLEX family describes MAX+PLUS access FLEX device features. class provides indepth description FLEX architecture explains architecture optimize your design meet area performance requirements. excercises used demonstrate implement logic FLEX embedded array blocks (EABs).
Alternative design methods session
FLEX Synopsys Training This one-day course teaches Synopsys tools design efficiently with FLEX devices. class provides in-depth description FLEX architecture. shown optimization features Synopsys MAX+PLUS used improve area performance design. will latest features Synopsys tools MAX+PLUS exercises used demonstrate these concepts.
Prerequisites Prerequisites include completion PLT-INTRO course good working knowledge MAX+PLUSII. Working experience with Synopsys design environment required. Agenda FLEX Synopsys course covers following topics.
Prerequisites Prerequisites include completion PLT-INTRO course good working knowledge MAX+PLUSII. Agenda FLEX course covers following topics.
FLEX basics FLEX architecture Logic element Embedded array block (EAB) Interconnect structure (row column composition) Design guidelines session session compile using Synopsys tools session Compiling MAX+PLUS session DesignWare session Logic functions EABs session optimization session Pipelining session State machines
FLEX basics FLEX architecture Logic element Embedded array block (EAB) Interconnect structure (row column composition) Description library parameterized modules (LPM) megafunctions
Classes offered regularly multiple locations each region. training class schedule course catalog available Altera Express (800)5-ALTERA Altera world-wide site http://www.altera.com.
Altera Corporation
News Views
August 1996
Altera News
Creating AMPP Megafunctions
Megafunctions produced part Altera Megafunction Partners Program (AMPP) targeted specific Altera device architectures. targeting process typically involves setting compilation synthesis options achieve optimum density performance. megafunctions then refined until they fast small possible. Megafunction Development Flow development AMPP megafunctions summarized below: megafunction begins high-level design created VHDL, Verilog HDL, schematic capture with third-party design tool MAX+PLUS megafunction design modified updated take advantage features target Altera architecture (e.g., embedded array blocks (EABs) FLEX devices, carry cascade chains FLEX devices). Logic synthesis options applied that synthesis engine invokes certain rules algorithms achieve specific design objectives (e.g., high speed, high density, parallel serial implementation, pipelining). These options third-party synthesis tools MAX+PLUSII. AMPP partner performs iterative design processing using MAX+PLUS maximize performance minimize resource usage. Some functions provide range size speed options offered different versions suit target design requirements. Once optimal specifications met, AMPP partner generates post-synthesis Altera Hardware Description Language (AHDL) file MAX+PLUS encrypts file using software provided Altera. AMPP partners also provide megafunctions VHDL, Verilog HDL, AHDL. final megafunction tested, proven, documented, added AMPP product availability list. Available Formats AMPP partners provide megafunctions following formats: VHDL Verilog Altera Hardware Description Language (AHDL) Post-synthesis AHDL
Post-synthesis AHDL files, provided most AMPP partners, reduce possibility unexpected changes occurring during design process. more information available design file formats, contact AMPP partners directly. Megafunction Package Contents Each packaged megafunction includes some following information, depending vendor: Encrypted post-synthesis AHDL file (<function name>.tdf) design file VHDL, Verilog HDL, AHDL Symbol File (<function name>.sym) MAX+PLUS schematics List critical timing parameters Documentation Authorization key(s) addition, some AMPP partners supply simulation models verification suites that used third-party tools prior MAX+PLUSII design processing, with test vectors check design functionality. Each partner offers different level design verification support. Designers should contact AMPP partner directly more information. Encryption AMPP megafunctions typically shipped encrypted format protect partners' intellectual property. Megafunction decryption performed MAX+PLUSII software. MAX+PLUSII must authorized process particular megafunction before design processing; decryption supplied customers when they license megafunction from AMPP partner. Licensing Terms Each AMPP partner specifies megafunction licensing terms, such Authorization codes installation instructions Time-period during which access megafunction will granted Access source code megafunction more information AMPP AMPP megafunctions, contact Altera Customer Marketing.
Altera Corporation
News Views
August 1996
Altera News
Target Applications Support Growing Strong
Altera target applications program provides tools improving design cycles supporting customer time-to-market. These tools include megafunctions, reference designs, design kits, documentation. Currently, target applications program focuses three areas: digital signal processing (DSP), peripheral component interconnect (PCI), communications. support includes megafunctions from Altera Megafunction Partners Program (AMPP) Altera MegaCore functions. table below summarizes AMPP megafunctions. megafunctions that planned 1996 include color space converters (RGB-YUV YUV-RGB) round, saturate, accumulate functions.
AMPP Functions
Partner
Integrated Silicon Systems Ltd.
Communications Communications support includes AMPP megafunctions that provide significant value network designers. These functions listed following table.
Communications AMPP Functions
Partner
Microelectronics, Inc. 3Soft Corporation Object Oriented Hardware
Megafunction
Speedbridge M16C450 UART M16550A UART RF-G704 synchronous framer/deframer RF-G721 ADPCM transcoder RF-HDLC controller RF-BRIM basic rate interface GF-RSC Reed Solomon CODEC GF-LILAC linked list access controller
Logic Innovations, Inc.
Acell delineation Acell translation routing Acell generator/checker Aswitch UTOPIA interface
Megafunction
Programmable filter 1-dimensional symmetric filter 1-dimensional median filter 2-dimensional filter biquad filter Laplacian sharpening filter Laplacian edge detector
Up-to-date information target applications available Altera world-wide site http://www.altera.com.
Synova Incorporated
JPEG decoder JPEG encoder Fast Fourier transform function
Altera Spring Show
Altera presented papers spring show held Jose, California, April May2. Wong, Altera Applications Engineer presented Design Foundation Flexible Rapid Interface Development" Tools panel VHDL Design Approach Master/Target Interface" Semicustom Logic Implementations panel. Both presentations were well received.
AMPP partners, Logic Innovations Eureka Technology, have announced megafunctions supporting both target master/target interfaces. MegaCore function support 32-bit target/ master megafunction will available fourth quarter 1996.
Altera Corporation
News Views
August 1996
Altera News
Altera Dream Team Delivers
crowds around Altera's booth recent Design Automation Conference (DAC) Vegas showed growing popularity Dream Team solution programmable logic designs. Over 1,000 engineers managers viewed Altera's presentation participated software hardware demonstrations. Altera Dream Team five players:
Special Announcements During DAC, Altera invited AMPP ACCESS partners discuss issues surrounding megafunctions. Although discussion focused simulation file encryption protecting intellectual property, many other issues were discussed. result, group companies develop sell intellectual property have joined form industry's first association: RAPID (Reusable Application-Specific Intellectual Property Developers). intellectual property vendors also intend create advocacy organization preserve their companies' interests intellectual property industry advances. Altera began distributing AMPP Catalog DAC. catalog summarizes current AMPP functions currently available more than under development) provides corporate profile each AMPP partner. copy AMPP Catalog, contact Altera Literature Services; up-to-date AMPP information available Altera site http://www.altera.com. number AMPP megafunctions expected grow year-end. During DAC, Altera announced that VHDL versions functions from library parameterized modules (LPM) available public domain. Altera descriptions obtained Electronic Design Interchange Format (EDIF) world-wide site http://www.edif.org. With VHDL models, tools silicon architectures that support process design containing functions. more information, "Now Available: VHDLSynthesizeable Functions" page Also DAC, Synopsys announced FPGA Express, PC-based synthesis tool targeted programmable logic industry. Altera Synopsys have worked closely develop interfaces Synopsys Design Compiler FPGA Compiler. This process will continue FPGA Express.
FLEX10K device family -Provides anchor Dream Team. With 100,000 gates, EPF10K100 largest programmable logic device commercially available today. MAX+PLUS development system-Combines strengths Altera devices with tools megafunctions create total programmable logic solution ASIC design challenges. Altera Commitment Engineering Solutions (ACCESS) program-Provides partnership with over vendors focuses ensuring compatibility with Altera architectures. Altera Megafunction Partners Program (AMPP)- Ensures constant flow megafunctions optimized Altera devices. MegaCore functions-Provides megafunctions handcrafted Altera.
Dream Team provides complete solution, focused improving productivity reducing product development cycles. Teamwork Ensures Success Altera offered numerous demonstrations using Altera devices tools from Altera's partners. Altera third-party tool companies shared responsibility hands-on demonstrations throughout show. total design solution successful because hardware software work together seamlessly. example, demonstration showed synthesis using Synopsys tools combined with simulation with Cadence tools EPF10K50 device, taking design from concept silicon. Other demonstrations included Autologic Quicklogic, WorkView Office with MAX+PLUS addition, communications designers were shown digital signal processing functions into 50,000-gate EPF10K50 device.
Altera Corporation
News Views
August 1996
Altera News Winning success large part active participation Altera partners vendors. Altera committed providing only most advanced devices, also design tools megafunctions that help designers increase productivity reduce product development cycles.
Every
Altera Device Selection Guide
current information Altera FLEX 10K, FLEX 8000, 9000, 7000 devices listed here. Information other Altera products given Altera 1996 Data Book. Contact Altera your local sales office current product availability.
FLEX Devices
Typical Gates EPF10K10 EPF10K10 EPF10K20 EPF10K20 EPF10K30 EPF10K30 EPF10K40 EPF10K40 EPF10K50 EPF10K50 EPF10K50 EPF10K70 EPF10K70 EPF10K100 EPF10K100 10,000 10,000 20,000 20,000 30,000 30,000 40,000 40,000 50,000 50,000 50,000 70,000 70,000 100,000 100,000 Pin/Package Options Pins Temp. Speed Grade Flipflops 1,344 1,344 1,968 1,968 2,576 2,576 3,184 3,184 3,184 4,096 4,096 5,392 5,392 Logic Elements 1,152 1,152 1,728 1,728 2,304 2,304 2,880 2,880 2,880 3,744 3,744 4,992 4,992 Bits 6,144 6,144 12,288 12,288 12,288 12,288 16,384 16,384 20,480 20,480 20,480 18,432 18,432 24,576 24,576
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 503-Pin 240-Pin RQFP, 503-Pin 503-Pin 503-Pin
102, 102, 147, 147, 147, 189, 147, 189, 147, 147, 189, 274, 189, 274, 189, 274, 189, 189,
pins dedicated inputs.
continued page
Altera Corporation News Views August 1996
Every Issue Altera Device Selection Guide continued from page
FLEX 8000 Devices
Usable Gates EPF8282A EPF8282A EPF8282A EPF8282AV EPF8452A EPF8452A EPF8452A EPF8636A EPF8636A EPF8636A EPF8820A EPF8820A EPF8820A EPF81188A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A 2,500 2,500 2,500 2,500 4,000 4,000 4,000 6,000 6,000 6,000 8,000 8,000 8,000 12,000 12,000 12,000 16,000 16,000 16,000 Pin/Package Options Pins 110, 110, 110, 120, 120, 120, 148, 148, 148, 181, 181, 181, Temp. Speed Grade Flipflops 1,188 1,188 1,188 1,500 1,500 1,500 Logic Elements 1,008 1,008 1,008 1,296 1,296 1,296
84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin PQFP, 225-Pin 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin PQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP 240-Pin PQFP, 280-Pin PGA, 304-Pin RQFP
indicates 3.3-V voltage supply. Four pins dedicated inputs.
9000 Devices
Macrocells Pin/Package Options Pins Temp. Speed Grade
EPM9320 EPM9320 EPM9320 EPM9400 EPM9400 EPM9400 EPM9480 EPM9480 EPM9560 EPM9560
84-Pin PLCC, 208-Pin RQFP, 280-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin CQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP 208-Pin CQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP
132, 132, 132, 139, 139, 139, 146, 146, 153, 191, 153, 191,
Four pins dedicated inputs.
Altera Corporation
News Views
August 1996
Every Issue
7000 Devices
Macrocells Pin/Package Options Pins 132, 132, 132, 132, 132, Temp. Speed Grade -10(P) -10(P) -12(P) -12(P) (ns) fCNT (MHz) 178.6 90.9 76.9 90.9 76.9 62.5 90.9 76.9 90.9 76.9 90.9 76.9 62.5 76.9 90.9 76.9 62.5 90.9 76.9 62.5 90.9 76.9 62.5
EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032 EPM7032, EPM7032S EPM7032V EPM7032V EPM7032V EPM7064, EPM7064S EPM7064, EPM7064S EPM7064, EPM7064S EPM7064 EPM7064, EPM7064S EPM7096, EPM7096S EPM7096, EPM7096S EPM7096, EPM7096S EPM7096 EPM7096, EPM7096S EPM7128E, EPM7128S EPM7128E, EPM7128S EPM7128E EPM7128E, EPM7128S EPM7128E EPM7128SV EPM7128SV EPM7160E, EPM7160S EPM7160E, EPM7160S EPM7160E EPM7160E, EPM7160S EPM7160E EPM7192E, EPM7192S EPM7192E, EPM7192S EPM7192E EPM7192E, EPM7192S EPM7192E EPM7256E, EPM7256S EPM7256E, EPM7256S EPM7256E EPM7256E, EPM7256S EPM7256E
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 64-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP
indicates 3.3-V voltage supply. Four pins dedicated inputs.
Altera Corporation
News Views
August 1996
Every Issue
Data Programming Support
Data provides programming hardware support select Altera devices. Algorithms supplied Data I/O's Keep Current Express Bulletin Board Service (KCE-BBS). Programming support Configuration EPROM, 9000, 7000 devices shown below. estimated availability dates subject change. Data customers with current maintenance agreement obtain qualified algorithms electronically from KCE-BBS. following Configuration EPROM devices supported 2900 version 5.2, 3900 version 5.2, UniSite version (Hex Files only).
7000 Devices
EPC1213P-8 EPC1213L-20 EPC1064P-8 EPC1064L-20 EPC1064T-20 EPC1064VL EPC1064VT EPC1P-8 EPC1LC-20
following 9000, 7000, FLASHlogic devices supported 3900 version UniSite version 5.2. 9000 Devices
EPM9320LC84 EPM9320GC280 EPM9320RC208 EPM9400RC208 EPM9400RC240 EPM9480RC208 EPM9480RC240 EPM9560GC280 EPM9560RC240 EPM9560WC208 EPM9560RC304
EPM7032L-44 EPM7032Q-44 EPM7032T-44 EPM7032VL-44 EPM7032VT-44 EPM7064L-44 EPM7064L-68 EPM7064L-84 EPM7064Q-100 EPM7096L-68 (EPROM) EPM7096L-84 (EPROM) EPM7096Q-100 (EPROM) EPM7096L-68 (EEPROM) EPM7096L-84 (EEPROM) EPM7096Q-100 (EEPROM) EPM7128L-84 EPM7128Q-100 EPM7128Q-160 EPM7128EL-84 EPM7128EQ-100 EPM7128EQ-160 EPM7160L-84 EPM7160Q-160 EPM7160EL-84 EPM7160EQ-100 EPM7160EQ-160 EPM7192G-160 EPM7192Q-160 EPM7192EG-160 EPM7192EQ-160 EPM7256G-192 EPM7256W-208 EPM7256M-208 EPM7256EG-192 EPM7256EG-160 EPM7256ER-208
FLASHlogic Devices
EPX880
Software Utilities
Overview electronic utilities EP310 EP330 JEDEC File converter JEDPACK JEDEC File compactor JEDSUM JEDEC checksum generator LEF2AHDL converts A+PLUS files AHDL eau018.exe PLD2EQN PAL/GAL/PLA file converter eau000.exe eau003.exe eau005.exe eau007.exe eau017.exe
eau019.exe ABEL2MAX file converter eau020.exe PASM2TDF PALASM file converter eau022.exe PLA2PDS PALASM file converter Utilities available from Altera modem (408) 954-0104 Altera site ftp.altera.com.
Altera Corporation News Views August 1996
Every Issue
Programming Hardware Compatibility
following tables contain latest programming hardware information. should always software version shown "Current Software Versions" page ensure correct programming. PLM-prefix adapters used only with Master Programming Unit (MPU).
Programming with BitBlaster
Device
FLEX 8000 devices 7000S EPX880 FLASHlogic devices
Programming Adapters
Device Package Adapter
PLMJ1213 PLMT1064 PLMJ1213 PLMJ1213
EPC1064, EPC1064V, EPC1213 DIP, J-lead (all FLEX 8000 devices), Note TQFP EPC1 (all FLEX FLEX 8000 devices), Note EPM9320 J-lead
PLMG9000-280 J-lead (84-pin) PLMJ9320-84 RQFP (208-pin) PLMR9000-208 J-lead (84-pin) PLMJ9400-84 RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240
Package
packages packages packages packages
Hardware
PL-BITBLASTER PL-BITBLASTER
EPM9400
FLEX devices packages
EPM9480 PL-BITBLASTER PL-BITBLASTER, PL-FLDLC, PL-BITBLASTER, Note (1), EPM7032, EPM7032V EPM9560
RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240 RQFP (208-pin) RQFP (240-pin) RQFP (304-pin) J-lead PQFP TQFP J-lead (68-pin) J-lead (84-pin) PQFP J-lead (68-pin) J-lead (84-pin) PQFP PLMG9000-280 PLMR9000-208 PLMR9000-240 PLMR9000-304 PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100
Notes tables:
MAX+PLUS version higher provides programming support FLASHlogic devices BitBlaster. EPX880 only programmed with BitBlaster. FLASHlogic Download Cable (PL-FLDLC) with PLDshell Plus program configure FLASHlogic devices, except EPX880. hardware products these devices included with FLEX Download Cable. Refer Altera 1996 Data Book device adapter information. Altera offers adapter exchange program 0.8-micron EPM5032, EPM5064, EPM5130 programming adapters. "Exchange Your 5000 Programming Adapter Free" page this newsletter more information.
EPM7064
EPM7096
EPM7128, EPM7128E
J-lead (84-pin) PLMJ7000-84 PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 J-lead PLMJ7000-84 PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 PQFP MQFP, RQFP PQFP J-lead packages packages packages PLMG7192-160 PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMQ7192/7256-160 PLMJ780-84
EPM7160, EPM7160E
EPM7192, EPM7192E EPM7256E
EPX780 5000 devices Classic devices EPS448
Note Note Note
Altera Corporation
News Views
August 1996
Every Issue
Request Altera Publications
Altera publications available through Altera Express, 24-hour, 7-day-a-week, automated service. U.S. Canada, call (800) 5-ALTERA; international callers retrieve information calling (408) 894-7850 from phone. following figure. Documents also obtained from Altera Literature Services (408) 894-7144 Altera world-wide site http://www.altera.com.
Begin Here
Main Menu
Press
order document. must know document number.
Press
order catalog available documents.
Press
listen Altera Express introduction.
Press
transfer Altera Literature Services.
Press
order documents mail with Altera's Voice Hotline.
Press
repeat menu options.
Catalog Menu
Press
order other literature, document catalog.
Press
finished ordering.
Press
return previous menu.
Access Altera
Getting information services from Altera easier than ever. table below lists some ways reach Altera:
Altera Contact Information
Information Type
Literature
Access
Altera Express Altera Literature Services
U.S. Canada
(800) 5-ALTERA (408) 894-7144 lit_req@altera.com (800) SOS-EPLD (408) 954-8186 (800) 800-EPLD (408) 894-7000 (408) 954-0348 (408) 954-0104 sos@altera.com ftp.altera.com altera (408) 894-7104 http://www.altera.com
Other Locations
(408) 894-7850 (408) 894-7144 lit_req@altera.com (408) 894-7000 (408) 954-8186 (408) 894-7000 (408) 954-0348 (408) 954-0104 sos@altera.com ftp.altera.com altera (408) 894-7104 http://www.altera.com
Non-Technical Customer Service Technical Support
Telephone Hotline Telephone Hotline a.m. p.m. Pacific Time) Bulletin Board Service Electronic Mail Site CompuServe
General Product Information
Telephone World-Wide
Note:
also contact your local Altera sales office sales representative. Altera 1996 Data Book list sales offices representatives.
Altera Corporation
News Views
August 1996
Response Form
Your Name: Organization: Street Address: City, State, ZIP: Phone: E-Mail:
would like subscription News Views. would like have design featured News Views. Please correct address.
Tell What Think
Please take moment help improve News Views rating usefulness following sections. Your answers will help shape content future issues. Useful Devices Tools Altera Publications Questions Answers Technical "How Articles Information Altera's Partners Interface Support Customer Applications Software Utilities Current Software versions Altera News Very Useful
Please write your comments about News Views space below (use additional pages necessary). Which subjects getting enough coverage? What questions still have? What features would like see?
Please mail copy this page
Altera Literature Distribution Services Altera Corporation 2610 Orchard Parkway Jose, 95134-2020 Fax: (408) 894-7809 E-mail: n_v@altera.com
Altera Corporation News Views August 1996

Altera introducing options high-density programmable logic devices (PL

Top Searches for this datasheet

Other recent searches