Altera shipping EPF10K100 device, which only largest member FLEX famil

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Altera Ships 100,000-Gate
Altera shipping EPF10K100 device, which only largest member FLEX family, also largest device programmable logic industry. FLEX devices contain both logic array embedded array that used RAM, ROM, complex logic functions. With added capability embedded array, EPF10K100 offers 100,000 gates-a breakthrough programmable logic. EPF10K100 more than twice large other programmable logic device (PLD) shipping today. Figure compares speed density FLEX family AT&T ORCA Xilinx XC4000 families. EPF10K100 contains approximately million transistors; contrast, Pentium (P7) microprocessor from Intel contains million transistors. EPF10K100 ideal prototyping initial production device ASIC designs. According market analysts Dataquest, 1996 gate array design starts will require device densities less than 100,000 gates. result, FLEX family meets density demands most gate array designs. addition 100,000 gates, EPF10K100 contains embedded array blocks (EABs) that integrate specialized arithmetic, digital signal processing (DSP), large on-chip memory functions. With EPF10K100, design engineers create prototype 100,000-gate gate array designs with system speeds over MHz. FLEX Architecture FLEX architecture implements complex functions efficiently embedded gate arrays-the fastest-growing segment gate array market. Like standard gate arrays, embedded gate arrays implement general logic conventional "sea-ofgates" architecture. addition, embedded gate arrays have dedicated areas implementing large, specialized functions. Embedded gate arrays contain functions that embedded silicon, which provides reduced area increased speed compared standard gate arrays. However, embedded functions typically cannot customized, thus limiting design flexibility. contrast, FLEX devices programmable, providing with full control over logic while facilitating iterative design changes during debugging. Each FLEX device contains embedded array logic array. embedded array implement
Figure Comparison Speed Density
Altera FLEX
Speed
AT&T ORCA Xilinx XC4000
Density
Source: Altera Corporation continued page
A-NV-Q296-01 Altera Corporation
News Views
1996
Contents
Features Altera Ships 100,000-Gate Customer Application: FLEX 8000 Devices "Grab" Vitana's Fancy Altera News Altera Synopsys Optimize Benefits Altera's FLEX Solution Available: First AMPP Functions Devices Tools Updates EPF10K10 Ships EPF10K50 Update EPF10K30 Ships 208-Pin Package FLEX 8000 Packages More Industrial-Temperature FLEX 8000 Devices FLEX 8000 Price Projections Discontinued FLEX 8000 Ordering Codes EPM9400 Ships 9000 Price Projections EPM7128S Ships 7000S Availability Exchange Your 5000 Programming Adapter Free Discontinued Devices
Megafunctions Streamline High-Density Design Data Programming Support
Technical Articles Preserving Resource Assignments VHDL Designs Analyzing Registered Performance with Timing Analyzer Using JTAG Interface Multi-Device Programming FLEX Memory Support Synopsys Implementing Internal Buses MAX+PLUS Parameterized Function Support AHDL AHDL Design Concurrency 9000 Programming Times Every Issue Altera Publications Altera Device Selection Guide Questions Answers Current Software Versions Programming Hardware Compatibility Software Utilities Request Altera Publications Access Altera Response Form
Submit questions ideas Altera Applications Department Attention: Martin (Editor) 2610 Orchard Parkway Jose, 95134-2020 Tel: (408) 894-7000 Fax: (408) 954-0348 E-mail: martinw@altera.com
Altera, MAX, MAX+PLUS, FLEX, AMPP, Megafunction Partners Program, MAX+PLUS AHDL, PLDasm, BitBlaster, EPC1, FastTrack, FLEX 10K, FLEX 8000, FLEX 8000A, 9000, 7000, 7000E, 7000S, MegaCore, FLASHlogic, 5000, Classic, FLEX DSP, specific device designations trademarks and/or service marks Altera Corporation United States and/or other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Advancel trademark Advancel Corporation. AT&T trademark AT&T. Verilog registered trademark Cadence Design Systems. Data registered trademark Data Corporation. registered trademark Hewlett-Packard Corporation. Windows, Windows 3.1.1, Windows registered trademarks Microsoft Corp. Synopsys registered trademark Synopsys, Inc. Viewlogic registered trademark Viewlogic Systems. Xilinx, XC4000E, XC4025E trademarks Xilinx, Inc. VAutomation trademark VAutomation. ShapeGrabber, IndustryPack, Module Site trademarks Vitana Corp. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Forward-looking statements this newsletter made pursuant safe harbor provisions Private Securities Litigation Reform 1995. Investors cautioned that forward-looking statements involve risks uncertainty, including without limitation risks dependence third-party wafer suppliers, intellectual property rights litigation, market acceptance demand Company's products well general market conditions, competition pricing, development technology manufacturing capabilities. Please refer Altera's Securities Exchange Commission filings, copies which available from Altera without charge, further information. Copyright 1996 Altera Corporation. rights reserved.
Printed recycled paper.
Altera Corporation
News Views
1996
Altera Ships 100,000-Gate continued from page variety memory functions complex logic functions, such DSP, microcontroller, wide datapath manipulation, data transformation functions. logic array same function sea-ofgates gate array: implement general logic, such counters, adders, state machines, multiplexers. combination embedded logic arrays provides high performance high density embedded gate arrays, enabling implement entire system single device. EPF10K100 contains 4,992 logic elements grouped into logic array blocks (LABs), EABs 24,576 bits), user pins. Figure compares EPF10K100 with Altera's first PLD, EP300. Design Support EPF10K100 supported MAX+PLUS version 6.2, Altera's fully integrated design
Figure EPF10K100 EP300 Dies
environment programmable logic. addition providing interfaces industry's most popular tools, MAX+PLUS offers support schematic capture high-level hardware description languages (HDLs), such VHDL Verilog HDL, highdensity design libraries such library parameterized modules (LPM). Creating complex designs 100,000-gate level requires equally complex development tools. result, Altera taking high-level design step further with Altera MegaCore functions functions from Altera Megafunction Partners Program (AMPP). introducing MegaCore functions AMPP, Altera first programmable logic vendor supply reusable, synthesizable megafunctions.
MegaCore Functions
Altera MegaCore functions developed, tested, documented, licensed Altera MAX+PLUS migration products. Designers these pre-tested functions that fully optimized target Altera device architecture. first MegaCore functions will available second quarter 1996, will consist several different design files, including VHDL, Verilog HDL, Altera Hardware Description Language (AHDL). more information, refer "Megafunctions Streamline High-Density Design" page
ALTERA MEGAFUNCTION PARTNERS PROGRAM
AMPP Functions
AMPP focuses supporting vendors supply tested, simulated, synthesizable megafunctions that optimized Altera device architectures. Currently, AMPP includes partner companies specialize supporting gate array market, have historically produced gate array standardcell implementations their functions. AMPP partners offer synthesizable netlist files their products, providing technology architecture independence. latest information AMPP links sites AMPP partners, Altera's world-wide site http://www.altera.com. Availability EPF10K100 available 503-pin package. Contact your local Altera representative pricing information. more information FLEX devices, contact Altera Customer Marketing.
Altera Corporation
News Views
1996
Devices Tools Updates
FLEX
EPF10K10 Ships Altera currently shipping 10,000-gate EPF10K10 programmable logic device. This latest member FLEX family brings power Altera's revolutionary embedded array 10,000-gate density level. EPF10K10 logic elements (LEs) grouped into logic array blocks (LABs), embedded array blocks (EABs), yielding 6,144 bits memory. FLEX devices supported Altera's MAX+PLUS development system version higher, which available workstation platforms. Support EPF10K10 available entry-level PLS-ES MAX+PLUS system platforms. MAX+PLUS supports special features FLEX architecture library parameterized modules (LPM), which allows build common logic memory functions quickly efficiently. MAX+PLUS Simulator allows read contents EABs. MAX+PLUS provides seamless integration with tools from Cadence, Data I/O, Mentor Graphics, Synopsys, Viewlogic, other leading vendors. EPF10K10 currently offered 208-pin plastic quad flat pack (PQFP) package. Future packages will include 144-pin thin quad flat pack (TQFP) 84-pin plastic J-lead chip carrier (PLCC) packages. Contact your local Altera representative pricing. EPF10K50 Update price EPF10K50GC403-5 been reduced over 50%. This device originally priced $995 each 100-unit quantities. Additionally, 50,000gate EPF10K50 available 240-pin power quad flat pack (RQFP) package. EPF10K30 Ships 208-Pin Package 30,000-gate EPF10K30 shipping 208-pin power quad flat pack (RQFP) package. Contact your local Altera representative pricing. September. TQFP packages ideal space-sensitive low-profile applications such personal computer memory card international association (PCMCIA) designs. More Industrial-Temperature FLEX 8000 Devices Altera recently introduced EPF8452AQI160-3, EPF81188AQI208-3, EPF81500ARI240-3 devices, expanding portfolio industrial-temperature devices. With these product introductions, each FLEX 8000 device least industrialtemperature version. FLEX 8000 Price Projections When compared with devices comparable density, Altera FLEX 8000 devices have lowest prices programmable logic industry. Volume price projections 1996 shown below.
Device
EPF8282ALC84-4 EPF8452ALC84-4 EPF8636ALC84-4 EPF8820AQC160-4 EPF81188AQC208-4 EPF81500ARC240-4
Price Note
5.00 7.50 $13.00 $19.00 $29.00 $49.00
Quantity
25,000 25,000 25,000 25,000 10,000 10,000
Note: Price U.S. dollars direct orders.
Discontinued FLEX 8000 Ordering Codes Altera discontinuing non-"A" FLEX 8000 ordering codes. lower-cost equivalent FLEX 8000A device drop-in replacement. last order date discontinued FLEX 8000 device ordering codes 1996; last ship date August 1996. more information, refer Product Discontinuance Notice (PDN) 9603. Discontinued ordering codes listed following table.
Discontinued FLEX 8000 Ordering Codes (Part
Device
EPF81188GC232-2 EPF81188GC232-3 EPF81188GI232-2 EPF81188RC240-2 EPF81188GC240-3 EPF81188RI240-3 EPF81500GC280-2 EPF81500GC280-3 EPF81500RC304-2 EPF81500RC304-3 EPF8282LC84-2
Alternative
EPF81188AGC232-4 EPF81188AGC232-4 Consult factory EPF81188ARC240-4 EPF81188ARC240-4 EPF81188ARI240-4 EPF81500AGC280-4 EPF81500AGC280-4 EPF81500ARC304-4 EPF81500ARC304-4 EPF8282ALC84-4
FLEX 8000
FLEX 8000 Packages EPF8636A EPF8820A devices available 208-pin plastic quad flat pack (PQFP) packages. EPF8820A devices will available 144-pin, 1.0-mm thin (TQFP) package
Altera Corporation
News Views
1996
Discontinued FLEX 8000 Ordering Codes (Part
Device
EPF8282LC84-3 EPF8282LI84-3 EPF8282TC100-2 EPF8282TC100-3 EPF8282VLC84-3 EPF8282VLC84-4 EPF8282VTC100-3 EPF8282VTC100-4 EPF8452LC84-2 EPF8452LC84-3 EPF8452LI84-3 EPF8452QC160-2 EPF8452QC160-3 EPF8820GI192-3 EPF8820RC208-2 EPF8820RC208-3 EPF8820RI208-3
7000
EPM7128S Ships Altera shipping EPM7128S 100-pin package. EPM7128S first member 7000S device family, which supports in-system programmability (ISP). EPM7128S also JTAG boundary-scan test circuitry open-drain output option. EPM7128S pin- programming filecompatible with EPM7128 EPM7128E devices. EPM7128SQC100 available 7.5-ns, 10-ns, 15-ns speed grades. non-"S" EPM7128 originally fabricated 0.8-micron CMOS process 1992 moved 0.65micron process 1995. EPM7128S fabricated 0.5-micron process. figure below shows relative sizes these devices.
EPM7128 Process Migration
Alternative
EPF8282ALC84-4 EPF8282ALI84-4 EPF8282ATC100-4 EPF8282ATC100-4 EPF8282AVLC84-4 EPF8282AVLC84-4 EPF8282AVTC100-4 EPF8282AVTC100-4 EPF8452ALC84-4 EPF8452ALC84-4 EPF8452ALI84-4 EPF8452AQC160-4 EPF8452AQC160-4 Contact Altera EPF8820ARC208-4 EPF8820ARC208-4 EPF8820ARI208-4
9000
EPM9400 Ships Altera shipping EPM9400-the fourth member 9000 device family-in 208-pin 240-pin RQFP packages. EPM9400 fabricated 0.65micron process supports in-system programmability (ISP) JTAG boundary-scan testing. Additional 9000 devices will produced 0.65-micron process 1996. following table shows expected process change schedule.
Device
EPM9320 EPM9480 EPM9560
0.8-µ EPM7128 1995
0.65-µ EPM7128 1996
0.5-µ EPM7128S 1992
Expected Process Change Date
October 1996 July 1996 1996
Continuous improvement both process geometry device features allows Altera provide highest performance most cost-effective design solutions available. 7000S Availability Altera will introduce remainder 7000S device family throughout 1996. table below shows schedule 7000S availability. Check with your local Altera sales representative specific package speed grade availability.
Device
EPM7256S EPM7192S EPM7160S EPM7128S EPM7096S EPM7064S EPM7032S
9000 Price Projections 9000 device family moves more aggressive process technologies, Altera will provide lower prices. following table shows 9000 volume price projections 1996 1997.
Device
EPM9320LC84-20 EPM9400LC84-20 EPM9480RC208-20 EPM9560RC208-20
Quantity
25,000 25,000 10,000 10,000
1996 1997
$30.00 $39.00 $67.00 $79.00 $17.00 $26.00 $35.00 $39.00
Availability
1996 June 1996 1996 1996 1996 1996
Note: Prices U.S. dollars direct order.
Contact your local Altera sales representative package speed grade pricing shown table above.
Altera Corporation News Views 1996
continued page
continued from page
5000
Exchange Your 5000 Programming Adapter Free Altera qualified 0.65-micron EPROM process 5000 devices migrating existing 0.8-micron 5000 devices 0.65-micron. This change will facilitate long-term support 5000 family. This migration will change 5000 ordering codes 5000 timing parameters shown 5000 Programmable Logic Device Family Data Sheet. However, programming adapters required program 0.65-micron devices. Altera will exchange existing EPM5032, EPM5064, EPM5130 programming adapters adapters charge. These adapters backwardscompatible support existing revisions. table right lists existing adapters that
exchanged adapters. Altera already completed exchange program EPM5128 EPM5192 programming adapters. Contact Altera's Customer Service Department (800) SOS-EPLD your local Altera representative take advantage this offer.
Existing Adapter
PLED5032 PLMD5032 PLEJ5032 PLM5032 PLES5032 PLEJ5064 PLMJ5064 PLEG5130 PLEJ5130 PLMJ5130 PLEQ5130 PLMQ5130
Adapter
PLMD5032A PLMD5032A PLMJ5032A PLMJ5032A PLMS5032A PLMJ5064A PLMJ5064A PLMG5130A PLMJ5130A PLMJ5130A PLMQ5130A PLMQ5130A
Discontinued Devices
recent months, Altera announced that various products will discontinued (see table below). Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera sales representative. Some ADVs PDNs also
Device Family
FLEX 8000 7000 FLASHlogic 5000
available Altera's world-wide site http://www.altera.com. Rochester Electronics, after-market supplier, offers support many discontinued Altera products. Contact Rochester Electronics (508) 462-9332 more information.
Last Order Date
10/31/96 10/31/96 6/28/96 3/31/97 10/31/96 9/30/96 3/31/97 6/28/96 10/31/96 3/31/97 6/28/96 9/30/96 3/31/97 10/31/96 3/31/97
Device
Military products (all 883B, DESC, military temperature grades) Military products (all 883B, DESC, military temperature grades) EPX780 (all packages, temperature grades, speed grades) EPX740 (all packages, temperature grades, speed grades) Military EPM5130W device Selected 5000 devices EPM5016 (all packages, temperature grades, speed grades)
Last Shipment Date
12/31/96 12/31/96 9/30/96 9/30/97 12/31/96 12/31/96 9/30/97 9/30/96 12/31/96 9/30/97 9/30/96 12/31/96 6/30/97 12/31/96 9/30/97
Reference
9513 9517 9513 9601 9516 9513 9609 9516 9516 9511 9513 9516 9518 9608 9608 9513 9517 9516
Classic
EP22V10, EP22V10E, EP310I, EP320I (all packages, temperature grades, speed grades) Military products (all 883B, DESC, military temperature grades) EP220, EP224, EP312, EP324 (all packages, temperature grades, speed grades) Selected EP6xx devices Selected EP9xx devices Selected EP18xx devices
FunctionSpecific
EPS448, EPC1213 military (all 883B, DESC, military temperature grades) EPS448, EPS464 (all commercial industrial temperature grades; military devices have earlier last order last shipment dates)
Altera Corporation
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1996
Megafunctions Streamline High-Density Design
FLEX family, with unique embedded array architecture, offers both density performance meet increasingly demanding design requirements. With 100,000 gates, FLEX first programmable logic device (PLD) family that provide system-on-a-chip integration. However, this increase density poses challenges designers, must design efficiently quickly 100,000-gate level. Historically, designers used Boolean equations schematic capture develop lower-density designs. device densities rose above 10,000 gates, designers turned high-level hardware description languages (HDLs), such VHDL Verilog HDL, high-density design libraries, such library parameterized modules (LPM), improve their productivity. These design methods permit designer describe behavior circuit rather than implementation, significantly reducing time required create debug circuit. Synthesis tools then automatically optimize design silicon. continue providing industry's most powerful easy-to-use development tools, Altera taking high-level design step further. With Alteracreated megafunctions, called MegaCore functions, functions created through Altera Megafunction Partners Program (AMPP), Altera first programmable logic vendor supply reusable, synthesizable megafunctions. MegaCore functions pre-verified design files complex system-level functions such microprocessors, microcontrollers, engines, RAM. MegaCore functions reduce design task creating only custom logic surrounding these commonly used system-level functions, dramatically shortening design cycle leveraging existing intellectual property. MegaCores permit designers focus more time energy improving differentiating design final product, rather than redesigning common off-the-shelf functions from ground MegaCore functions developed, tested, documented, licensed Altera MAX+PLUS migration products. Designers these pre-tested megafunctions fully optimized target Altera device architecture, including FLEX 10K, FLEX 8000, 9000, 7000 devices. first MegaCore functions will available late third quarter 1996, include following functions:
8051 8-bit processor 6502 8-bit processor 16450 universal asynchronous receiver/transmitter (UART) 6402 UART 6850 asynchronous communications interface adapter (ACIA)
Altera MegaCore functions consist several different design files. post-synthesis AHDL design file used design implementation (i.e., fitting) target Altera device. addition, VHDL Verilog functional simulation models supplied design debugging with standard simulation tools. MegaCore functions optimized architectural features Altera devices, which ensures that userspecified performance area goals met. Megafunctions also available partners AMPP. date, Altera formed partnerships with companies. Like Altera, AMPP vendors develop megafunctions that optimized Altera devices. Altera trains AMPP vendors Altera device architectures provides them with MAX+PLUS software. Customers negotiate directly with AMPP vendors either license standard megafunction products have custom design service performed. listing current AMPP partner companies their product specialties appears "Now Available: First AMPP Megafunctions" page
Altera Corporation
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1996
Altera Synopsys Optimize Benefits
Altera participated most recent Synopsys Users Group conference, open technical forum that focused customer issues. Altera presented information Altera/Synopsys Design program synthesize designs targeted Altera FLEX devices, which offer 100,000 gates logic. This article highlights information that Altera presented conference. High-level logic designers faced with many decisions when creating design methodology that optimizes benefits programmable logic devices (PLDs). goal combine design synthesis tools that will work with widest range silicon, while minimizing total development time. Altera/Synopsys Design provides complete design solution, integrating Altera MAX+PLUS Compiler with Synopsys logic synthesis tools. With this process, high-density logic designs easily targeted Altera's broad range PLDs without changing design descriptions methodologies. This flexibility integration leads faster time-to-market. Combined with densities Altera devices, these tools give designers competitive advantage. Embedded Array Blocks Altera FLEX embedded array blocks (EABs) flexible: they implement either memory logic functions. Altera/Synopsys design flow allows designers effectively access each 2,048-bit both types functions. implement both synchronous asynchronous RAM, well FIFO functions dual-port RAM. Synopsys design tools allow easy memory functions, include complete functional simulation timing-driven synthesis models. Logic functions accessible through Synopsys hierarchical synthesis feature. contents EABs modified on-the-fly, allowing designers change portion design without disturbing operation rest device. FLEX family also links EABs with continuous interconnect structure provide predictable speeds regardless design-an advantage unavailable gate array designers. Carry Cascade Features FLEX architecture uses four-input look-up table (LUT) basic building block, offering fast, efficient implementation general logic. architecture also offers carry cascade chains implementing counters, adders, comparators, which significant logic resources. Implementing these functions FLEX FLEX 8000 device easy with Altera/Synopsys Design Kit, which contains DesignWare library that provides area optimization high performance. result optimal circuit speed smallest possible area. High-Speed Cells FLEX FLEX 8000 architecture ensures high in-system performance with fast input, setup, clock-to-output times high-speed registers located cells periphery device. These cell registers easily accessed Synopsys environment attaching property register. Partnerships Enhance Value close ties between Altera Synopsys provide seamless integration design solutions, tools, silicon. This relationship example Altera ensures that users Altera PLDs have widest range tools available. example, Altera Commitment Cooperative Engineering Solutions (ACCESS) program consists vendors have developed design entry, synthesis, verification, and/or device programming products that support Altera PLDs. Altera continually evaluating adding ACCESS partners. more information Altera/Synopsys interface, refer Altera Synopsys Software Interface Guide.
Altera Corporation
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1996
Altera's FLEX Solution
past, designers digital signal processing (DSP) systems were forced choose between flexibility processor high performance ASIC. Now, however, Altera offers FLEX solution that provides both flexibility real-time performance. Design Altera provides free design (see figure right), which includes customizable building blocks implementing functions FLEX FLEX 8000 devices. design contains support literature following reference designs:
Parallel finite impulse response (FIR) filters with parameterized features-8-, 16-, 24-, 32-, 64-tap functions with parameterized coefficient width, symmetry, pipelining. Serial filters-16- 64-tap functions that accommodate designs with larger widths. Arithmetic functions-Floating-point multiplier, adder/subtractor, integer divider functions. video convolver-Convolution filter with parameterized coefficient width pipelining.
Altera DSPx Altera presented papers Digital Signal Processing Applications Conference Exhibition (DSPx) held Santa Clara, from March through Caleb Crome, Altera Applications Engineer, Martin Langhammer, Kaytronics Field Applications Engineer, presented "Image Processing Acceleration Using Altera FLEX Programmable Logic" conference. Martin Langhammer also presented "Adaptive Filtering Architecture Distributed Arithmetic Applications Altera FLEX." Magazine showcased Altera's FLEX solution "New Product Presentations."
design improve productivity shorten designer's development cycle. example, designer created cable modem design that used modified filter reference design create YUV-toRGB converter function, fir_32tp reference design create 32-tap filtering function. Both designs were completed under minutes, saving valuable development time. information other design applications, refer Technical Brief (Using FLEX Devices Coprocessors). Design available from Altera Literature Services. Reference designs support literature also available from Altera's world-wide site http://www.altera.com.
Altera Corporation
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1996
Preserving Resource Assignments VHDL Designs
When designing Altera devices using Synopsys tools, pass device resource assignments from VHDL Design File (.vhd) MAX+PLUS EDIF netlist file. script that commands Synopsys Design Compiler compile VHDL Design File make adjustments resulting EDIF netlist. example, following dc_shell script passes cell assignments from VHDL Design File (.vhd), ministate.vhd sample file included with MAX+PLUS workstations) EDIF netlist file, ministate.edf.
read-format vhdl ministate.vhd compile write_name_nets_same_as_ports true set_attribute find(port, ps2) "CHIP_PIN_LC" -type string "ministate@4" set_attribute find(cell, state_reg[1]) "LOGIC_OPTION" -type string "io_cell_register=on" edifout_dc_script_flag="altera" edifout_write_attributes="true" {CHIP_PIN_LC LOGIC_OPTION} write -format edif -hierarchy output ministate.edf
resulting netlist file. Then, dc_shell script generates cell assignments adds them EDIF netlist file. attribute commands (highlighted blue) assign port implement register state_reg[1] cell register when EDIF netlist file compiled. synthesize project through MAX+PLUS Altera-provided setacf utility. Before compile EDIF netlist file MAX+PLUS project must assigned specific device. Otherwise, MAX+PLUS defaults AUTO device selection resource assignments preserved. assign project specific device MAX+PLUS Choose Device (Assign menu). Device dialog displayed. Select device family-e.g., FLEX 8000-from Device Family drop-down list box. Choose specific device-e.g., EPF8282LC84-in Devices box. Choose
dc_shell script reads compiles VHDL design, using design's port names names
When compile design, MAX+PLUS Compiler synthesizes design chosen device makes resource assignments specified EDIF netlist file.
Altera Publications
Altera publications available from Altera Literature Services, Altera Express, Altera world-wide site (see "How Access Altera" page this newsletter). Document part numbers shown italics.
FLEX Embedded Programmable Logic Device Family Errata Sheet A-ES-F10K-1.1 Provides updated configuration information EPF10K10, EPF10K50, EPF10K100 devices with data codes prior x9639 (i.e., devices manufactured prior 39th week 1996). (Implementing Multipliers FLEX Devices)
A-AN-053-01
(Design Tools 100,000-Gate Programmable Logic Devices) A-PIB-022-01 Discusses ASIC design tools with tools offered programmable logic vendors create large designs quickly while optimizing silicon features programmable logic devices (PLDs).
Describes implement large multipliers using several embedded array blocks (EABs) compares parallel multiplier time-domainmultiplexed multiplier implementations.
Altera Corporation
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1996
Analyzing Registered Performance with Timing Analyzer
MAX+PLUS Timing Analyzer permits analyze performance design after synthesized Compiler. Timing Analyzer trace signal paths project, well determine critical speed paths paths that limit performance design. Calculating Clock Performance Design Timing Analyzer's Registered Performance Display shows worst-case registered performance, i.e., maximum clock frequency every clock signal circuit. following figure. default settings Registered Performance Display evaluate whether design meeting performance goals. design does meet your goals, Registered Performance Display determine number paths that fail amount which they fail. design that from meeting performance goals requires different strategy than design that meets performance requirements paths. options Time Restrictions dialog (Options menu) list either paths that fail meet specified clock frequency specified number paths. following figure.
Analyzing Bottlenecks Design After Timing Analyzer finds longest delay paths, view information paths choosing List Paths. Message Processor displays propagation delays calculated between nodes, including internal setup time propagation delay through flipflop. choose Locate locate highlight each signal path. Then, trace path either source design file Floorplan Editor. more information Timing Analyzer, refer MAX+PLUS Help.
open Registered Performance Display choosing Registered Performance (Analysis menu) Timing Analyzer. Registered Performance Display measures maximum delay from output flipflops data clock enable inputs other flipflops, including:
Clock-to-output delay source flipflop Combinatorial interconnect delays between source destination flipflops Internal setup time destination flipflop
Altera Corporation
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1996
Using JTAG Interface Multi-Device Programming
features MAX+PLUS version higher permit program multiple 9000, 7000S, FLASHlogic devices in-system JTAG interface BitBlaster serial download cable. define JTAG chain necessary JTAG parameters non-Altera devices they bypassed during programming. Furthermore, programming multiple devices requires only single JTAG-compatible header interface. JTAG chain contain number IEEE standard 1149.1 JTAG-compliant devices-including Altera devices non-Altera devices. following figure shows sample JTAG chain.
Devices JTAG Chain
9000 Device
Multi-Device JTAG Chain Setup dialog box, which shown below.
Multi-Device JTAG Chain Setup Dialog
7000S Device
Other JTAGCompliant Device
Select device name first device JTAG chain from Device Name dropdown list box. necessary, modify selected device's attributes choosing JTAG Device Attributes button. Altera device chain programming, enter programming file Programming File Name select with Select Programming File button.
more information programming with BitBlaster, BitBlaster Serial Download Cable Data Sheet current Altera data book. Defining JTAG Chain JTAG chain must defined before programming correct JTAG data constructed. define JTAG chain: MAX+PLUS Programmer, choose MultiDevice JTAG Chain Setup (JTAG menu). Build list devices JTAG chain, along with appropriate programming files,
Choose button device JTAG chain. non-Altera device JTAG chain, enter name Device Name JTAG Device Attributes dialog (see following figure), specify values Instruction Register Length, Boundary Scan Length, (optional) JTAG Code boxes. Choose
JTAG Device Attributes Dialog
Altera Corporation
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1996
Repeat steps through each device chain.
"Multi-Device JTAG Chain" number programming files. Choose Program button program device(s).
necessary, select device name MultiDevice JTAG Chain dialog choose Down buttons Order match device's position list with physical position JTAG chain printed circuit board. necessary, choose Delete button delete devices from list. (Optional) Select device name MultiDevice JTAG Chain dialog choose Detect JTAG Chain Info verify that device count, JTAG code, total instruction length correct. Save JTAG chain information choosing Save button Multi-Device JTAG Chain dialog box. Enter name JTAG Chain File (.jcf) choose
MAX+PLUS Verificaton Options verification options MAX+PLUS Programmer allow reduce cycle time ISP. These options reduce both single-device multidevice JTAG chain programming times. Programming Options dialog (Options menu), following options turned default:
Blank-Check Before Programming-This option automatically checks that device blank before being programmed. Programmer issues message indicating whether device blank. Blank-checking required 9000, 7000S, FLASHlogic devices; therefore, this option safely turned when using ISP. Verify During Programming-This option automatically verifies device during programming checks whether each sufficiently programmed. Turning this option increase speed device programming. Verify After Programming-This option automatically verifies device after programming checks insufficiently erased bits. Turning this option increase speed device programming. Test After Programming-This option automatically performs post-programming functional testing devices programmed with current programming file. This option available multiple devices programmed ISP, however, available single-device ISP.
JTAG Chain File records name each device chain, well name associated programming file, any. Programming Multiple Devices JTAG Chain Follow steps below configure MAX+PLUS Programmer program multiple devices with BitBlaster: Connect BitBlaster workstation, PCB. Configure BitBlaster according directions BitBlaster Serial Download Cable Data Sheet. Choose Hardware Setup command (Options menu) select BitBlaster Hardware Type box. Choose Turn Multi-Device JTAG Chain command (JTAG menu) specify multi-device JTAG chain. Choose Restore command (JTAG menu) specify JCF. Programmer window displays
more information, Technical Brief (In-System Programming Times 9000 Devices).
Altera Corporation
News Views
1996
Customer
FLEX 8000 Devices "Grab" Vitana's Fancy
Contributed Andrew Nelson, hardware engineer with Vitana Corporation.
Vitana Corporation, based Ottawa, offers two- three-dimensional imaging products integrated solutions resource, industrial design, parts inspection, volume measurement, contour analysis, medical imaging industries. Vitana leader three-dimensional imaging experience laser-based imaging, digital signal processing (DSP), high-speed digital design. company's flagship product, ShapeGrabber, second-generation laser-scanning system that fits into standard design high-speed digital video circuitry control implement complex algorithms that make ShapeGrabber finest-quality imaging system available. Figure Challenge From onset, knew that ShapeGrabber would single card, packed with features. Although core functionality provided Texas Instruments floating-point device TMS320C44), determined that support device video peak detection
Figure ShapeGrabber Board Shot
sub-pixel interpolation, could meet goal providing real-time video three-dimensional imaging. Therefore, first challenge identify device that would allow build high-speed digital filters. addition real-time video processing, other major performance requirement high host/embedded transfer rates Mbytes second). that, decided peripheral component interconnect (PCI) master/slave interface high-speed local support data transfers between devices ShapeGrabber card. Finally, planned provide easy upgrades customers field, imperative that these devices reconfigurable reprogrammable insystem. Another benefit in-circuit reconfigurability (ICR) quick easy prototyping iterations. Solution Three types devices could have needs: gate arrays, off-the-shelf programmable filters, programmable logic devices (PLDs). Although gate arrays could less expensive large quantities, their long development times inflexibility made gate arrays ultimately unsuitable project. None programmable filters considered were flexible enough needs. particular, these filters could implement different types filters upgrades product modifications envisioned. some previous experience with programmable anti-fuse devices; however, need configure devices in-circuit field precluded these onetime-programmable devices. also considered using field-programmable gate arrays (FPGAs) with segmented routing, ultimately decided against them concern their poor routability need guarantee timing fitting with
planned provide easy upgrades customers field, imperative that these devices reconfigurable reprogrammable insystem." -Andrew Nelson, Vitana Corporation
Altera Corporation
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1996
Application
each design iteration through future upgrades. PLDs that needs, least from initial examination, were Altera FLEX 8000 devices. Implementation When creating designs FLEX 8000 devices, began grouping functions assigning descriptive names icons devices that would perform functions. didn't take long before devices lives their own. devices their functionality summarized below.
Device Name
Device
TwinPeaks
Device Used
detection validation external device, freeing more processing time. TwinPeaks design-which included filters-I chose EPF81188A device. peak locator 16-bit, 8-tap filter peak location validator 14-bit, 3-tap filter. Both filters video rates. TwinPeaks design also contained sub-pixel interpolator, which interpolates position peak 1/64 pixel. placed these functions device, they would have consumed device's functionality. using EPF81188A coprocessor, were able meet speed requirements. Figure shows TwinPeaks block diagram. Development Time first-generation ShapeGrabber, used anti-fuse-based devices. took about painful months build that version-painful both terms design cost because throw devices away after each iteration. However, using Altera's MAX+PLUS software, designed second-generation ShapeGrabber less than day, completed full simulation entire design following weeks. continued page
Function
Video peak EPF81188AQC208-3 detector subpixel interpolator EPF8452AQC160-3 EPF8452ALC84-3
GateKeeper
TwinPeaks
GateKeeper TMS320C44 GrabMaster Video control logic Diablo
GrabMaster
TMS320C44 local EPF8282ATC100-3 arbiter memory controller
four designs, TwinPeaks most challenging. designed TwinPeaks video preprocessor, with intention having device perform peak Diablo
Figure TwinPeaks Block Diagram Note
from Analog Digital Convertor Local
Frame Buffer Controller
Peak Detector (FIR Filter)
FLEX 8000 Device Validation Logic (FIR Filter Comparator) Sub-Pixel Interpolator
Microprocessor Interface
from GrabMaster from GrabMaster Pixel Clock
Video Line Counters Pixel Counter
Peak Buffer Controller
Peak Positions
Vitana Corporation 25-5470 Canotek Gloucester, Ontario K1J9H3 Tel. (613) 749-4445 (613 749-4087
Altera Corporation
Note: TwinPeaks design patented Vitana Corporation.
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1996
FLEX 8000 Devices "Grab" Vitana's Fancy continued from page create design, used MAX+PLUS version 6.0, which supports library parameterized modules (LPM). This solution permitted create custom building blocks that were limited conventional logic sizes. Because functions were optimized target device chose, able concentrate design without worrying about lower-level implementation details. MAX+PLUS version also better device fitting support, evidenced when software designs faster easier than previous version. FLEX 8000 devices support in-circuit reconfigurability (ICR), which vastly decreased amount time took protoype ShapeGrabber. could make design change, implement physically test minutes. Using Altera Hardware Description Language (AHDL), able make, simulate, fully test design changes day. With these rapid prototyping features, time-tomarket decreased significantly. In-Field Upgrades features planned this generation ShapeGrabber ability perform in-field
Figure ShapeGrabber Block Diagram
upgrades modifications meet special customer needs. accomplished this reconfiguring FLEX 8000 devices bus. wrote software driver that resides host platform converts FLEX 8000 programming file configuration data. driver also downloads configuration data appropriate FLEX 8000 device upon startup. that required upgrades modifications single programming file that sent customer electronically. Figure provides block diagram ShapeGrabber. Some modifications planning include changing filtering TwinPeaks design. example, instead peak detection, consider valley detection, performing low-pass high-pass filtering video signal. case, gives greater ability service customers field. Conclusion Having worked with number device architectures design packages, truly that using FLEX 8000 devices along with MAX+PLUS software were ideal choices creating product. ShapeGrabber meets goal being most advanced three-dimensional imaging product worldwide.
50-Pin Digital Video Connector
Video Input External Sync
TwinPeaks
Restore
Low-Pass Filter
12-Bit, 10-MHz Analog Digital Convertor
Video Peak Detector Memory Control Logic
Clock Generator
GenLock Controller
GrabMaster
Digital Output Digital Output Laser Enable
50-Pin Connectors
DSP,
Laser Mod. System
Power Supply
Digital Analog External
Video Control Logic
External Sync
Frame Buffer 256K VRAM 50-Pin Connector
Peak Buffer SRAM
IndustryPack Module Sites
TwinPeaks
Peripheral Local
SyncGen Controller
Interface
GateKeeper
128K SRAM 50-MHz TMS320C44 Device
Diablo
Local Arbiter DRAM Memory Controller
Mastering, DMA, Controller
PCI/DSP Interface Peripheral Controller
Module Sites (TIM)
JTAG Debugging Port
DRAM
JTAG-Capable Devices
Global
Altera Corporation
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1996
FLEX Memory Support Synopsys
Altera/Synopsys interface offers full memory support FLEX device family, including asynchronous synchronous ROM, cycleshared FIFO functions, cycle-shared dual-port RAM. Altera software utility genmem-which provided with Altera's Synopsys support MAX+PLUS II-to generate functional simulation models timing models designs with different sizes ROM. When install MAX+PLUS genmem placed /usr/maxplus2/bin directory. genmem utility, type following command UNIX prompt: genmem <memory type><memory size> [-vhdl] [-verilog][-viewlogic] variable <memory type> specifies valid memory type, including: asynram asynrom synram synrom csfifo csdpram Asynchronous Asynchronous Synchronous Synchronous Cycle-shared FIFO function Cycle-shared dual-port bits wide, Component Declaration template (asyn_rom_256x15.cmp), timing model (asyn_rom_256x15.lib). timing model contains pin-to-pin delay information that used Synopsys Design Compiler. Design Compiler access timing information, must asynchronous timing model existing library typing following commands UNIX prompt: read flex10k.db update_lib flex10K <RAM/ROM function name>.lib During compilation, Synopsys VHDL Compiler VHDL Compiler Verilog automatically translates design into Synopsys database format with extension .db. update database file from previous example (flex10k.db), following optional command: write_lib flex10K flex10k.db Designs that contain functions must include structure EDIF netlist file that generated from design. include structure EDIF netlist file, edifout_no_array "false" following lines .synopsys_dc.setup file Synopsys Design Compiler: compile_fix_multiple_port_nets true bus_naming_style "%s<%d>"; bus_dimension_separator_style "><" bus_inference_style "%s<%d>"; requires initialization file Hexadecimal (Intel-format) file (.hex). Synopsys intelhex utility, provided with Synopsys VHDL System Simulator (VSS) Software Tool, used translate Synopsys memory file into File. Refer Synopsys VHDL System Simulator Software Tool manual details about using intelhex utility. more information about Synopsys support memory functions Altera devices, refer Synopsys MAX+PLUS Software Interface Guide, available from Altera Literature Services Altera's world-wide site http://www.altera.com.
variable <memory size> specifies size memory model using word width format, where: word width Must between 32,768 words deep Must between bits wide
word width values must separated such 256x15. following options available: -vhdl -verilog -viewlogic generates VHDL output (default setting) generates Verilog output generates VHDL output Viewlogic
example, create asynchronous VHDL output, type: genmem asynrom 256x15 -vhdl genmem utility generates asynchronous model (asyn_rom_256x15.vhd) that words deep
Altera Corporation
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1996
Implementing Internal Buses MAX+PLUS
Beginning with version 6.0, MAX+PLUS provides internal synthesis support Altera devices. Although Altera devices support internal tristate buses, synthesis support allows designers internal tri-state structures their designs. MAX+PLUS then converts structures multiplexers. Figure shows schematic internal bus. Figure input each buffers from junction point internal named. example, junction named d3[5.0]. This naming necessary because single buffer schematic really represents primitive array buffers, each bus. MAX+PLUS synthesizes appropriate number buffers according size bus, which specified attached name. named, MAX+PLUS report following error: Width Mismatch pinstub <name> (<instance number.name>). Altera Hardware Description Language (AHDL) equivalent design Figure shown below.
INCLUDE "74174b"; SUBDESIGN tri_ex data_in[5.0], bus_en, sel_a sel_b, nclear, clock bus_data[5.0] VARIABLE bus_tri1[5.0] bus_tri2[5.0] bus_tri3[5.0] d1[5.0] d2[5.0] d3[5.0] d4[5.0] TRI; TRI; TRI; NODE; NODE; TRI_STATE_NODE; NODE;
BEGIN d1[] 74174b(nclear, clock, data_in[]); bus_tri1[].in d1[]; bus_tri1[].oe sel_a; d3[] bus_tri1[].out; d2[] 74174b(nclear, clock, bus_data[]); bus_tri2[].in d2[]; bus_tri2[].oe sel_b; d3[] bus_tri2[].out; d4[] 74174b(nclear, clock, d3[]); bus_tri3[].in d4[]; bus_tri3[].oe bus_en; bus_data[] bus_tri3[].out; END;
INPUT; INPUT; BIDIR;
node junction internal connection, d3[5.0], must defined TRI_STATE_NODE. This definition directs MAX+PLUS synthesize this junction.
Figure Internal Buses MAX+PLUS
bus_en sel_a 74174B data_in[5.0] nclear clock
D[6.1] CLRn Q[6.1]
d1[5.0]
bus_tri1 d3[5.0]
D[6.1] CLRn
74174B d4[5.0]
Q[6.1]
bus_data[5.0]
sel_b 74174B
D[6.1] CLRn Q[6.1]
bus_tri3
d2[5.0]
bus_tri2
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1996
following equations synthesized bus_data1:
bus_data1 TRI(d41, bus_en); DFFE( _EQ001 VCC, clock, nclear, VCC, VCC); _EQ001 (!d21 sel_b) (!d11 sel_a);
Figure Schematic Equivalent Equations bus_data1
bus_en
sel_a
bus_data1
sel_b clock nclear
CLRn
Figure shows graphical representation these equations they implemented logic, while Figure shows simplified representation equations (excluding gate). more information tri-state buses, refer MAX+PLUS Help.
Figure Simplified Schematic Equivalent Equations bus_data1
bus_en
sel_a
bus_data1
sel_b clock nclear
CLRn
Altera Device Selection Guide
current information Altera FLEX 10K, FLEX 8000, 9000, 7000 devices listed here. Information other Altera products given Altera 1995 Data Book. Contact Altera your local sales office current product availability.
FLEX Devices
Typical Gates EPF10K10 EPF10K10 EPF10K20 EPF10K20 EPF10K30 EPF10K30 EPF10K40 EPF10K40 EPF10K50 EPF10K50 EPF10K70 EPF10K70 EPF10K100 EPF10K100 10,000 10,000 20,000 20,000 30,000 30,000 40,000 40,000 50,000 50,000 70,000 70,000 100,000 100,000 Pin/Package Options Pins Temp. Speed Grade Flipflops 1,344 1,344 1,968 1,968 2,576 2,576 3,184 3,184 4,096 4,096 5,392 5,392 Logic Elements 1,152 1,152 1,728 1,728 2,304 2,304 2,880 2,880 3,744 3,744 4,992 4,992 Bits 6,144 6,144 12,288 12,288 12,288 12,288 16,384 16,384 20,480 20,480 18,432 18,432 24,576 24,576
84-Pin PLCC, 144-Pin TQFP, 208-Pin RQFP 84-Pin PLCC, 144-Pin TQFP, 208-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 319-Pin PGA, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 319-Pin PGA, 356-Pin 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin RQFP, 503-Pin 240-Pin RQFP, 503-Pin 503-Pin 503-Pin
107, 107, 147, 147, 147, 198, 147, 198, 147, 147, 189, 274, 189, 274, 189, 189,
pins dedicated inputs.
continued page
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1996
Altera Device Selection Guide continued from page
FLEX 8000 Devices
Usable Gates EPF8282A EPF8282A EPF8282A EPF8282AV EPF8282AV EPF8452A EPF8452A EPF8452A EPF8636A EPF8636A EPF8636A EPF8820A EPF8820A EPF8820A EPF81188A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A 2,500 2,500 2,500 2,500 2,500 4,000 4,000 4,000 6,000 6,000 6,000 8,000 8,000 8,000 12,000 12,000 12,000 16,000 16,000 16,000 Pin/Package Options Pins 110, 110, 110, 120, 120, 120, 148, 148, 148, 181, 181, 181, Temp. Speed Grade Flipflops 1,188 1,188 1,188 1,500 1,500 1,500 Logic Elements 1,008 1,008 1,008 1,296 1,296 1,296
84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 100-Pin TQFP, 160-Pin PGA/PQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 84-Pin PLCC, 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP, 225-Pin 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP, 225-Pin 144-Pin TQFP, 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP, 225-Pin 208-Pin PQFP, 232-Pin PGA, 240-Pin RQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin RQFP 208-Pin PQFP, 232-Pin PGA, 240-Pin RQFP 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP,
indicates 3.3-V voltage supply. Four pins dedicated inputs.
9000 Devices
Macrocells Pin/Package Options Pins Temp. Speed Grade
EPM9320 EPM9320 EPM9320 EPM9400 EPM9400 EPM9400 EPM9480 EPM9480 EPM9560 EPM9560
84-Pin PLCC, 208-Pin RQFP, 280-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin CQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP 208-Pin CQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP
132, 132, 132, 139, 139, 139, 146, 146, 153, 191, 153, 191,
Four pins dedicated inputs.
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1996
7000 Devices
Macrocells Pin/Package Options Pins 132, 132, 132, 132, 132, Temp. Speed Grade -10(P) -10(P) -12(P) -12(P) (ns) fCNT (MHz) 178.6 90.9 76.9 90.9 76.9 62.5 90.9 76.9 90.9 76.9 90.9 76.9 62.5 76.9 90.9 76.9 62.5 90.9 76.9 62.5 90.9 76.9 62.5
EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032, EPM7032S EPM7032 EPM7032, EPM7032S EPM7032V EPM7032V EPM7032V EPM7064, EPM7064S EPM7064, EPM7064S EPM7064, EPM7064S EPM7064 EPM7064, EPM7064S EPM7096, EPM7096S EPM7096, EPM7096S EPM7096, EPM7096S EPM7096 EPM7096, EPM7096S EPM7128E, EPM7128S EPM7128E, EPM7128S EPM7128E EPM7128E, EPM7128S EPM7128E EPM7128SV EPM7128SV EPM7160E, EPM7160S EPM7160E, EPM7160S EPM7160E EPM7160E, EPM7160S EPM7160E EPM7192E, EPM7192S EPM7192E, EPM7192S EPM7192E EPM7192E, EPM7192S EPM7192E EPM7256E, EPM7256S EPM7256E, EPM7256S EPM7256E EPM7256E, EPM7256S EPM7256E
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 44-Pin PLCC/TQFP, 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 64-Pin PLCC, 100-Pin PQFP 68-Pin PLCC, 84-Pin PLCC, 100-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin PQFP, 160-Pin PQFP 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP/PGA 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP 160-Pin PQFP, 192-Pin PGA, 208-Pin RQFP
indicates 3.3-V voltage supply. Four pins dedicated inputs.
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1996
device bitstream counts. Summing single-device counts used estimation lower bound multi-device count.
Device
EPF8282A EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A
Single-Device Count Note
40,960 63,112 93,304 123,496 183,880 253,112, Note
Notes: counts subject change without notice. bits when using EPC1213 Configuration EPROMs.
just received latest MAX+PLUS upgrade. want install upgrade, middle project. What should Altera recommends using same version MAX+PLUS throughout project cycle. However, decide upgrade newer version, should archive your project that reload previous version necessary. directions archiving project, search "Archiving Project" MAX+PLUS Help.
creating large FLEX 8000 design read.me file MAX+PLUS says that Altera recommends minimum Mbytes memory (RAM virtual memory) FLEX 8000 projects. find much memory have increase that amount? determine much memory have increase available memory, refer "Maximizing Available Memory Windows Windows Workgroups 3.11" page MAX+PLUS Getting Started manual.
using EPF10K50 403-pin package. Does Altera sell sockets this device?
Altera does sell sockets this device, recommends third-party socket manufacturers listed below:
Socket Type
Test Burn-in Sockets 3M/Textool Yamaichi Low-profile, McKenzie printed circuit board sockets
Does MAX+PLUS support open-drain pins?
Vendor
Part Number
1-382320-7 2-0403-08450-390-019-002 NP-178-64401-Ks14828 Family
MAX+PLUS version higher supports open-drain pins FLEX devices OPNDRN primitive. Open-drain pins 7000S devices supported MAX+PLUS version higher. input OPNDRN primitive low, output will low. input high, output will high-impedance logic level. OPNDRN primitive used design targeted Altera devices other than FLEX 7000S, OPNDRN primitive converted primitive. turn Automatic Open-Drain Pins option Global Project Logic Synthesis dialog (Assign menu) FLEX 7000S design, MAX+PLUS Compiler converts following structures OPNDRN primitive:
Max/Preci-Dip Series Family
creating custom configuration EPF81188 printed circuit board. What exact count configuration bitstream that MAX+PLUS generates this device? following table lists exact counts single-device configuration bitstreams generated MAX+PLUS FLEX 8000 devices. Because overhead from combining multiple bitstreams, count multiple-FLEX 8000 device configuration bitstream single-
primitive whose output enable input signal, whose primary input primitive primitive whose output enable input complement primary input
When OPNDRN buffer, must observe following rules:
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1996
OPNDRN drive only BIDIR BIDIRC OPNDRN feeds logic, must also feed BIDIR BIDIRC OPNDRN feeds BIDIR BIDIRC pin, cannot feed other outputs design files created with MAX+PLUS MAX+PLUS workstations?
When MAX+PLUS compile EDIF file generated Synopsys FPGA Compiler, following error: Can't find design file 'LUT'. What doing wrong? Before generate EDIF netlist file with Synopsys tools, must execute replace_fpga command. Synopsys FPGA Compiler maps logic cell structure, while MAX+PLUS looks gate-level netlist EDIF file. replace_fpga command instructs Synopsys tools replace look-up table (LUT) cell structure with gate-level netlist EDIF file.
Yes, vice versa. With MAX+PLUS extended feature your workstation (PLSMEXTWS), your files-including Graphic Design Files (.gdf)-can used both workstation With base MAX+PLUS workstation product (PLS-WS), transfer AHDL design files programming files between platforms.
installed MAX+PLUS workstation. When software, following message:
past have used MAX+PLUS have recently starting using MAX+PLUS workstation. does MAX+PLUS handle UNIX environment's case sensitivity? UNIX workstation environment, MAX+PLUS uses lowercase filenames Altera-provided megafunctions macrofunctions, well their corresponding Symbol File (.sym) Include File (.inc) names. should lowercase characters references these functions textbased design files. Altera also recommends using lowercase names your megafunctions, macrofunctions, Symbol Files, Include Files. However, Altera provides variable that your maxplus2.ini file lessen impact UNIX environment's case-sensitivity during compilation: FILE_CASE_SEARCH_NODE=<setting> where <setting> following: LOWER MAX+PLUS searches exact filename case. exact case found, searches lowercase version name. This default setting MAX+PLUS version higher. MAX+PLUS searches exact filename case. exact case found, searches lowercase version name; that found, searches name case. MAX+PLUS searches exact filename case. exact case found, searches name case. This option lower speed performance MAX+PLUS
maxplus2 installed sunos /usr/ maxplus2/bin
What should
MAX2_HOME variable properly. error message indicates that MAX2_HOME pointing /usr/maxplus2/bin-instead /usr/ maxplus2 directory where installed MAX+PLUS reset this variable, place following line your .cshrc file:
setenv MAX2_HOME <path MAX+PLUS
Then, source .cshrc file.
would like upgrade from SunOS 4.1.5. Does MAX+PLUS support Solaris 2.5?
SMART
Yes. MAX+PLUS versions higher support Solaris 2.5. also MAX+PLUS version higher Solarisbased Ultra Ultra workstations. Because MAX+PLUS takes advantage 64-bit mode UltraSPARC chip used Ultra expect significantly higher performance when running MAX+PLUS Ultra Ultra workstations.
have Case Statement Altera Hardware Description Language (AHDL) design that several bits labeled "Don't Care." example:
CASE WHEN B"XXX10000" sig_out[] temp[];
Altera does recommend creating multiple files whose names differ only case same directory.
(continued page
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Parameterized Function Support AHDL
industry-standard library parameterized modules (LPM) provides architecture-independent functions that simplify design process. supported Altera other vendors such Viewlogic, Mentor Graphics, Cadence, VeriBest. includes logic blocks that range from simple functions (e.g., gates registers) more complex functions (e.g., adders multiplexers). addition simplifying design entry, designing with other parameterized functions ensures efficient device utilization. support parameterized functions, Altera added features MAX+PLUS Altera Hardware Description Language (AHDL). Explicit Iterative Assignments past, AHDL supported iteration implicit statement. example, following statement implies four separate assignments:
bus_one[] bus_two[3.0];
Conditional Logic Generation When building your parameterized functions, Generate Statement AHDL file select function that optimized device family your project. Altera-provided parameterized functions contain similar statements ensure that each function uses device efficiently possible. following example.
DEVICE_FAMILY "FLEX 10K" GENERATE my_adder10k GENERATE; efficient FLEX implementation
Rule Checking functions offer designers fast, efficient, flexible design entry method. With this flexibility, designers require easy verification design's logical legal parameter values. Assert Statement used automatic parameter checking during compilation effective ensure that functions other parameterized functions used intended. sample Assert Statement shown below.
ASSERT (width REPORT "LPM Width less than detected" SEVERITY ERROR;
With MAX+PLUS version higher, AHDL also supports explicit iterative logic assignments using Generate Statement. following example illustrates make explicit assignments parameterized function my_adder.
PARAMETERS width= SUBDESIGN my_adder a[width.1], b[width.1], sum[width.1], cout VARIABLE carr_ch[width+1.1]
structure Assert Statement shown below. ASSERT( condition listed inside parentheses. arithmetic expression used. However, separate Assert Statement must used each condition checked. REPORT user-created message placed within quotation marks. assertion condition true, this message displayed MAX+PLUS Message Processor Report File (.rpt). SEVERITY Possible values are: INFO, WARNING, ERROR. severity type displayed immediately before REPORT message Message Processor. value SEVERITY ERROR, compilation stops when Assert Statement true. more information AHDL, refer MAX+PLUS Help MAX+PLUS AHDL manual.
Altera Corporation News Views 1996
INPUT; OUTPUT;
NODE;
BEGIN carr_ch[1] cin; width GENERATE sum[i] a[i] b[i] carr_ch[i]; carr_ch[i+1] a[i] b[i] a[i] carr_ch[i] b[i] carr_ch[i]; GENERATE; cout carr_ch[width+1]; END;
AHDL Design Concurrency
most programming languages, command sequence affects functionality system. contrast, placement symbols schematic devices printed circuit board (PCB) does change logical functionality system. Like schematics PCBs, statements Altera Hardware Description Language (AHDL) evaluated concurrently. This article highlights effect concurrency design, using following AHDL Text Design File (.tdf) example.
SUBDESIGN example reset, load c[2.0] BEGIN load THEN reset THEN END;
preceeding example, when load reset assignments: (statement (statement These assignments combined value (1102). When load first Then Statement (statement adds assignment (0012) assignments, causing have value (1112). When reset second Then Statement (statement assigns (0002). Because this assignment bits assignment affect c[]. MAX+PLUS considers these possibilities synthesizes appropriate logic. These results summarized table below.
load reset
INPUT; OUTPUT;
Result
Comment
c[2.0] Assignments made statements c[2.0] Assignments made statements c[2.0] Assignments made statements c[2.0] Assignments made statements
Statement Statement
Statement
Statement
ensure desired results during compilation, Altera recommends placing assignments signal single conditional structure. example, obtain following result, only single Then Statement needed.
load
design above, c[2.0] following values:
load
reset
Result
c[2.0] c[2.0] c[2.0]
reset
Result
c[2.0] c[2.0] c[2.0] c[2.0]
AHDL that implements these values shown below.
SUBDESIGN example reset, load c[2.0] BEGIN load THEN ELSIF reset THEN ELSE END;
These values surprising some designers because AHDL design does provide same results sequential programming language (such C++). Instead, when AHDL synthesized MAX+PLUS statements evaluated concurrently (for conditional statements, such Case Then Statements, only first true statement evaluated concurrently). Equations that assign multiple values same AHDL node variable logically connected (ORed node variable active high, ANDed active low). Therefore, when MAX+PLUS evaluates four statements design above during compilation, order statements irrelevant.
INPUT; OUTPUT;
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1996
9000 Programming Times
When structure manufacturing flow include in-system programmability (ISP), device programming times very important. Altera 9000 devices programmed in-system through Joint Test Action Group (JTAG) interface matter seconds. time required program verify 9000 device JTAG interface function programming pulse width, verification pulse width, test input clock frequency (TCK). 9000 programming times calculated with following equation: tPROG (pPULSE tWIDTH) (TCKCYCLES 1/fTCK) where: tPROG pPULSE tWIDTH TCKCYCLES Total programming time Number programming pulses required Programming pulse width Number clock cycles
Programming Verification Times 9000 Devices
vPULSE tWIDTH
Number verification pulses Verification pulse width
table below provides values these parameters each 9000 device.
Device vPULSE
6018 6012 6006 6000
tWIDTH (µs)
TCKCYCLES
2,800,000 2,500,000 2,200,000 1,900,000
tVERIFY (seconds)
Note
0.37 0.34 0.31 0.28
EPM9560 EPM9480 EPM9400 EPM9320
Note: Programming times assume MHz.
figure below shows combined programming verification times each 9000 device function JTAG test input clock frequency.
table below provides values these parameters each 9000 device.
Device pPULSE
tWIDTH (ms)
TCKCYCLES
760,000 700,000 640,000 580,000
tPROG (seconds)
Note
Time
EPM9560 EPM9480 EPM9400 EPM9320
EPM9560 EPM9480 EPM9400 EPM9320
Note: Programming times assume MHz.
Frequency
9000 verification times calculated with following equation: tVERIFY (vPULSE tWIDTH) (TCKCYCLES 1/ftck) where: tVERIFY Total verification time
programming options MAX+PLUS Programmer adjust verfication times 9000 devices. more information these options, refer either "Using JTAG Interface Multi-Device Programming" page MAX+PLUS Help.
Look 1996 Data Book July
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Available: First AMPP Functions
ALTERA MEGAFUNCTION PARTNERS PROGRAM
Altera Megafunction Partners Program (AMPP) partnership between Altera third-party megafunction developers. Designers megafunctions shorten design cycles speed time-to-market. first megafunctions developed under AMPP V6502 from VAutomation 32-bit reconfigurable finite impulse response (FIR) filter from Integrated Silicon Systems, Ltd. (ISS). VAutomation re-worked architecture V6502 gate usage high performance. 32-bit filter from processes 12-bit data KHz.
AMPP Partners
Partner
3Soft Advancel CAST Digital Design Development Eureka Technology Excellent Design Infinite Solutions Integrated Silicon Systems Logic Innovations Object Oriented Hardware AMicroperipherals, 8-bit controllers XMIDI digital music PowerPC, interfaces Microperipherals, graphics, compression Optimized core products Set-top technologies, ATM, SONET, Broad library functions
coefficients filter stored FLEX embedded array block (EAB), enabling taps reconfigured on-the-fly adapt filter changing system requirements. following table summarizes current AMPP partners, their product specialties, contact information. latest megafunction listings availability information, Altera's world-wide site http://www.altera.com. catalog AMPP megafunctions will available early June 1996.
Specialty
Microperipherals
Initial Product
8051, PCMCIA 8254, 68450 XMIDI controller PowerPC suite Greencore 32-bit filter ATM,
Telephone
(408) 451-5700 (408) 453-0600 (914) 354-4945 (32) 270-27-97 (408) 888-0439 (81) 45-474-9410 (408) 986-1686 (44) 232-664664 (619) 455-7200
E-Mail
sales@3soft.com info@advancel.com info@cast-inc.com 73261.530@compuserve.com info@eurekatech.com ampp@exd.co.jp info@InfiniteSolutions.com info@iss-dsp.com info@logici.com
Reed Solomon (44) 1171-538-4114 info@ooh.com CODEC, Linked List Access Controller (LILAC) 6805 Controller V6502 (818) 991-1509 (408) 438-5330 (407) 728-8889 (603) 882-2282 (408) 452-1600 cores@srti.com info@sei.com info@sismicro.com ampp@synova.com sales@VAutomation.com sales@vchips.com
Sierra Research Technology Silicon Engineering Microelectronics Synova VAutomation
Processors, Ethernet, AGraphics controllers, CPUs Embedded Application blocks R3000, compression CPUs, controllers
Synchronizing FIFO (303) 776-1667
Virtual Chips (formerly interfaces RAVIcad)
Current Software Versions
latest versions Altera software products shown below:
MAX+PLUS version (PC, SPARCstation, 9000 Series 700, RISC System/6000 platforms) PLDshell Plus version only)
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1996
Data Programming Support
Data provides programming hardware support select Altera devices. Algorithms supplied Data I/O's Keep Current Express Bulletin Board Service (KCE-BBS). Programming support Configuration EPROM, 9000, 7000 devices shown following tables. checkmark indicates that KCE-BBS support available now. date represents Altera's best estimate when support will available from Data I/O. estimated availability dates subject change. KCE-BBS directs Data customers with current maintenance agreement obtain qualified algorithms electronically from KCE-BBS.
Configuration EPROM Support
Device
EPC1213P-8 EPC1213L-20 EPC1064P-8 EPC1064L-20 EPC1064T-20 EPC1064VL EPC1064VT
2900 Version
File Only File Only File Only File Only File Only File Only File Only
3900 Version
File Only File Only File Only File Only File Only File Only File Only
UniSite Version
File Only File Only File Only File Only File Only File Only File Only
EPM7096L-68 (EEPROM) EPM7096L-84 (EEPROM) EPM7096Q-100 (EEPROM) EPM7128L-84 EPM7128Q-100 EPM7128Q-160 EPM7128EL-84 EPM7128EQ-100 EPM7128EQ-160 EPM7160L-84 EPM7160Q-160 EPM7160EL-84 EPM7160EQ-100 EPM7160EQ-160 EPM7192G-160 EPM7192Q-160 EPM7192EG-160 EPM7192EQ-160 EPM7256G-192 EPM7256W-208 EPM7256M-208 EPM7256EG-192 EPM7256EG-160 EPM7256ER-208
9000 Support
Device
EPM9320LC84 EPM9320GC280 EPM9320RC208 EPM9400 EPM9480 EPM9560GC280 EPM9560RC240 EPM9560WC208 EPM9560RC304
following 7000 devices supported 3900 version UniSite version 5.1.
3900 Version
UniSite Version
EPM7032L-44 EPM7032Q-44 EPM7032T-44 EPM7032VL-44 EPM7032VT-44 EPM7064L-44 EPM7064L-68 EPM7064L-84 EPM7064Q-100 EPM7096L-68 (EPROM) EPM7096L-84 (EPROM) EPM7096Q-100 (EPROM)
Note Note
1996
Note Note
1996
Note: Data does currently support programming this device. Contact Altera Applications more information availability.
Questions Answers continued from page When compile this design, seems logic cells does device want use. have suggestions?
When define "don't care," additional logic required handle
possible states that bit, which excessive logic resources. Changing "don't care" bits often reduce amount logic required this portion your design, sometimes 75%. Analyze your design replacing your "don't care" bits with will give results require. this change improves logic utilization increases your chance fitting your design selected device.
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1996
Programming Hardware Compatibility
table below contains latest programming adapter information. should always software version shown "Current Software Versions" page ensure correct programing. "PLM" prefix adapters used only with MPU.
Programming Hardware
Device
FLEX devices FLEX 8000 devices
Notes table:
Package
packages packages
Hardware
PL-BITBLASTER PL-BITBLASTER PLMJ1213 PLMT1064 PLMJ1213 PLMJ1213
EPC1064, EPC1064V, EPC1213 DIP, J-lead (all FLEX 8000 devices), Note TQFP EPC1 (all FLEX FLEX 8000 devices), Note EPM9320 J-lead
PLMG9000-280 J-lead (84-pin) PLMJ9320-84 RQFP (208-pin) PLMR9000-208 RQFP (208-pin) PLMR9000-208 RQFP (240-pin) PLMR9000-240 RQFP (208-pin) RQFP (240-pin) RQFP (304-pin) J-lead PQFP TQFP J-lead (68-pin) J-lead (84-pin) PQFP J-lead (68-pin) J-lead (84-pin) PQFP PLMG9000-280 PLMR9000-208 PLMR9000-240 PLMR9000-304 PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100
EPM9480, EPM9400 EPM9560
hardware products these devices included with FLEX Download Cable. MAX+PLUS version higher provides programming support FLASHlogic devices BitBlaster. EPX880 only programmed with BitBlaster. FLASHlogic Download Cable (PLFLDLC) with PLDshell Plus program configure FLASHlogic devices, except EPX880. Refer Altera 1995 Data Book device adapter information. Altera offers adapter exchange program 0.8-micron EPM5032, EPM5064, EPM5130 programming adapters. "Exchange Your 5000 Programming Adapter Free" page this newsletter more information.
Software Utilities
eau000.exe Overview electronic application utilities eau003.exe EP310 EP330 JEDEC File converter eau005.exe JEDPACK JEDEC File compactor eau007.exe JEDSUM JEDEC checksum generator eau017.exe LEF2AHDL converts A+PLUS files AHDL eau018.exe PLD2EQN PAL/GAL/PLA file converter eau019.exe ABEL2MAX file converter eau020.exe PASM2TDF PALASM file converter eau022.exe PLA2PDS PALASM file converter ttf2rbf file converter utility been integrated into MAX+PLUS software version higher. Utilities available from Altera modem (408) 954-0104 Altera site ftp.altera.com.
EPM7032, EPM7032V
EPM7064
EPM7096
EPM7128, EPM7128E
J-lead (84-pin) PLMJ7000-84 PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 packages PL-BITBLASTER
EPM7128S EPM7160, EPM7160E
J-lead PLMJ7000-84 PQFP (100-pin) PLMQ7000-100 PQFP (160-pin) PLMQ7128/7160-160 PQFP MQFP, RQFP PQFP J-lead packages packages packages packages packages PLMG7192-160 PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMQ7192/7256-160 PLMJ780-84 PL-BITBLASTER, Note PL-FLDLC, PL-BITBLASTER, Notes (2),
EPM7192, EPM7192E EPM7256E
EPX780 EPX880 FLASHlogic devices 5000 devices Classic devices EPS448
Note Note Note
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1996
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Access
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U.S. Canada
(800) 5-ALTERA (408) 894-7144 (800) SOS-EPLD (408) 954-8186 (800) 800-EPLD (408) 894-7000 (408) 954-0348 (408) 954-0104 sos@altera.com ftp.altera.com altera (408) 894-7104 http://www.altera.com
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Altera shipping EPF10K100 device, which only largest member FLEX famil

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