1Mbit (128K x8), Asynchronous SRAM FEATURES SUMMARY SUPPLY VOLTAG
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M68AF127BL
1Mbit (128K x8), Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 5.5V
Figure Packages
128K bits SRAM with OUTPUT ENABLE EQUAL CYCLE ACCESS TIMES: 55ns STANDBY CURRENT DATA RETENTION: TRI-STATE COMMON ACTIVE STANDBY POWER
SO32 (MC)
PDIP32
2002
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M68AF127BL
TABLE CONTENTS SUMMARY DESCRIPTION Figure Logic Diagram Figure Block Diagram Figure Connections Figure Connections Figure Block Diagram MAXIMUM RATING. Table Absolute Maximum Ratings PARAMETERS. Table Operating Measurement Conditions Figure Measurement Waveform Figure Measurement Load Circuit Table Capacitance. Table Characteristics. OPERATION Table Operating Modes Read Mode Figure Address Controlled, Read Mode Waveforms Figure Chip Enable Output Enable Controlled, Read Mode Waveforms. Table Read Standby Mode Characteristics Write Mode Figure Write Enable Controlled, Write Waveforms Figure Chip Enable Controlled, Write Waveforms Table Write Mode Characteristics Figure Controlled, Data Retention Waveforms Figure Controlled, Data Retention Waveforms Table Data Retention Characteristics PACKAGE MECHANICAL SO32 lead Plastic Small Outline, Package Outline SO32 lead Plastic Small Outline, Package Mechanical Data. PDIP32 Plastic DIP, mils width, Package Outline PDIP32 Plastic DIP, mils width, Package Mechanical Data PART NUMBERING Table Ordering Information Scheme REVISION HISTORY. Table Document Revision History
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M68AF127BL
SUMMARY DESCRIPTION M68AF127BL 1Mbit (1,048,576 bit) CMOS SRAM, organized 131,072 words bits. device features fully static operation requiring external clocks timing strobes, with equal address access cycle times. requires single 5.5V supply.
This device automatic power-down feature, reducing power consumption over when deselected. M68AF127BL available SO32 (32-lead Small Outline) PDIP32 (32-pin Plastic Dual-InLine) packages.
Figure Logic Diagram
Table Signal Names
A0-A16 DQ0-DQ7 Address Inputs Data Input/Output Chip Enable Chip Enable Output Enable Write Enable Supply Voltage Ground
A0-A16
DQ0-DQ7
M68AF127BL
AI05472
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M68AF127BL
Figure Connections Figure Connections
M68AF127BL
AI05473
M68AF127BL
AI07003
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M68AF127BL
Figure Block Diagram
DECODER MEMORY ARRAY
CIRCUITS COLUMN DECODER
AI05471
MAXIMUM RATING Stressing device above rating listed "Absolute Maximum Ratings" table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification Table Absolute Maximum Ratings
Symbol
implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Parameter Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input Output Voltage Power Dissipation
Value -0.5 -0.5 +0.5
Unit
TSTG
Note: output time, exceed second duration. maximum operating 6.0V only.
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M68AF127BL
PARAMETERS This section summarizes operating measurement conditions, well characteristics device. parameters following Characteristic tables derived from tests performed under Measure-
ment Conditions listed relevant tables. Designers should check that operating conditions their projects match measurement conditions when using quoted parameters.
Table Operating Measurement Conditions
Parameter Supply Voltage Range Ambient Operating Temperature Range Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages Output Transition Timing Ref. Voltages 85°C 100pF 3.0k 3.1k 1ns/V VCC/2 0.3VCC; 0.7VCC M68AF127BL 5.5V 70°C
Figure Measurement Waveform
Figure Measurement Load Circuit
Timing Reference Voltage VCC/2 DEVICE UNDER TEST Output Transition Timing Reference Voltage 0.7VCC 0.3VCC
AI04831
includes capacitance
AI05814
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M68AF127BL
Table Capacitance
Symbol COUT Parameter (1,2) Input Capacitance pins (except Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested. 25°C, 1MHz, 3.0V.
Table Characteristics
Symbol ICC1 (1,2) ICC2
Note:
Parameter Supply Current
Test Condition 5.5V, 1/tAVAV, IOUT 5.5V, 1MHz, IOUT VOUT 5.5V, 0.2V, 0.2V,
Unit
Operating Supply Current Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Voltage Output High Voltage Output Voltage
-0.3
-1mA 2.1mA
Average current, cycling tAVAV minimum. VIL, VIH, VIL. 0.2V -0.2V, 0.2V -0.2V. Output disabled.
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M68AF127BL
OPERATION M68AF127BL Chip Enable power down feature which invokes automatic standby mode whenever Chip Enable de-asserted High), Chip Select asserted Low). Output Enable signal provides high-speed, tri-state Table Operating Modes
Operation Read Read Write Deselect Deselect
Note: VIL.
control, allowing fast read/write cycles achieved with common data bus. Operational modes determined device control inputs summarized Operating Modes table (Table
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z Hi-Z
Power Active (ICC) Active (ICC) Active (ICC) Standby (ISB) Standby (ISB)
Read Mode M68AF127BL Read mode whenever Write Enable High with Output Enable Low, Chip Enable (E1) asserted Chip Select (E2) de-asserted. This provides access data from eight 1,048,576 locations static memory array, specified address inputs. Valid data will available eight output pins
within tAVQV after last stable address, providing Low. Chip Enable Output Enable access times met, data access will measured from limiting parameter (tELQV tGLQV) rather than address. Data indeterminate tELQX tGLQX, data lines will always valid tAVQV.
Figure Address Controlled, Read Mode Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05474
Note: Low, High, Low, High.
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M68AF127BL
Figure Chip Enable Output Enable Controlled, Read Mode Waveforms.
tAVAV A0-A16 tAVQV tELQV VALID tAXQX tEHQZ
tELQX tGLQV tGLQX DQ0-DQ7 VALID
AI05476
tGHQZ
Note: Write Enable High.
Figure Chip Enable Controlled, Standby Mode Waveforms
AI05477
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M68AF127BL
Table Read Standby Mode Characteristics
M68AF127BL Symbol tAVAV tAVQV tAXQX tEHQZ (2,3) tELQV tELQX tGHQZ (2,3) tGLQV tGLQX Read Cycle Time Address Valid Output Valid Data hold from address change Chip Enable High Output Hi-Z Chip Enable Output Valid Chip Enable Output Transition Output Enable High Output Hi-Z Output Enable Output Valid Output Enable Output Transition Chip Enable UB/LB High Power Down Chip Enable UB/LB Power Parameter Unit
Note: Test conditions assume transition timing reference level 0.3VCC 0.7VCC. given temperature voltage condition, tGHQZ less than tGLQX tEHQZ less than tELQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels. Tested initially after design process changes that affect these parameters.
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M68AF127BL
Write Mode M68AF127BL Write mode whenever pins High. Either Chip Enable input (E1) Write Enable input must de-asserted during Address transitions subsequent write cycles. Write begins with concurrence being active with low. Therefore, address setup time referenced Write Enable Chip Enable tAVWL tAVEH, respectively, determined latter occurring edge.
Write cycle terminated earlier rising edge Output enabled Low, High Low), then will return outputs high impedance within tWLQZ falling edge. Care must taken avoid contention this type operation. Data input must valid tDVWH before rising edge Write Enable, tDVEH before rising edge whichever occurs first, remain valid tWHDX tEHDX.
Figure Write Enable Controlled, Write Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL tELWH tWHAX
tWLWH tAVWL tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI05478
tWHQX
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M68AF127BL
Figure Chip Enable Controlled, Write Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL tELEH tEHAX
tAVWL tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05479
tWLEH
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M68AF127BL
Table Write Mode Characteristics
M68AF127BL Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid Chip Enable High Address valid Chip Enable Address Valid Write Enable High Address Valid Write Enable Input Valid Chip Enable High Input Valid Write Enable High Chip Enable High Address Transition Chip enable High Input Transition Chip Enable Chip Enable High Chip Enable Write Enable High Write Enable High Address Transition Write Enable High Input Transition Write Enable High Output Transition Write Enable Chip Enable High Write Enable Output Hi-Z Write Enable Write Enable High Parameter Unit
Note: given temperature voltage condition, tWLQZ less than tWHQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels.
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M68AF127BL
Figure Controlled, Data Retention Waveforms
DATA RETENTION MODE 5.5V 4.5V
2.0V tCDR 0.2V
AI07204
Figure Controlled, Data Retention Waveforms
DATA RETENTION MODE 5.5V 4.5V
2.0V tCDR 0.2V
AI07205
Table Data Retention Characteristics
Symbol ICCDR Parameter Supply Current (Data Retention) Test Condition 1.5V, -0.2V 0.2V, tAVAV -0.2V 0.2V, Unit
Chip Deselected Data tCDR (1,2) Retention Time
Operation Recovery Time Supply Voltage (Data Retention)
Note: other Inputs -0.2V 0.2V. Tested initially after design process that affect these parameters. tAVAV Read cycle time. input exceed +0.2V.
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M68AF127BL
PACKAGE MECHANICAL Figure SO32 lead Plastic Small Outline, Package Outline
SO-C
Note: Drawing scale.
Table SO32 lead Plastic Small Outline, Package Mechanical Data
millimeters Symbol 1.27 20.14 11.18 13.87 0.58 1.19 0.10 2.57 0.15 2.82 0.30 0.10 20.75 11.43 14.38 0.99 1.60 0.050 0.793 0.440 0.546 0.023 0.047 0.36 0.51 3.00 0.004 0.101 0.006 0.111 0.012 0.004 0.817 0.450 0.566 0.039 0.063 0.014 0.020 0.118 inches
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M68AF127BL
Figure PDIP32 Plastic DIP, mils width, Package Outline
PDIP-C
Note: Drawing scale.
Table PDIP32 Plastic DIP, mils width, Package Mechanical Data
millimeters Symbol 15.24 2.54 3.81 0.41 1.14 0.23 41.78 15.24 13.46 3.05 1.65 0.53 1.65 0.38 42.29 15.88 13.97 3.56 2.21 0.600 0.100 0.38 0.150 0.016 0.045 0.009 1.645 0.600 0.530 0.120 0.065 0.021 0.065 0.015 1.665 0.625 0.550 0.140 0.087 4.83 0.015 0.190 inches
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M68AF127BL
PART NUMBERING Table Ordering Information Scheme
Example: Device Type Mode Asynchronous Operating Voltage 4.5V 5.5V Array Organization 1Mbit (128K Option Chip Enable Option leakage Speed Class 55ns 70ns Package SO32 PDIP32 Operative Temperature Shipping Tape Reel Packing M68AF127
list available options (e.g., Speed, Package) further information aspect this device, please contact STMicroelectronics Sales Office nearest you.
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M68AF127BL
REVISION HISTORY Table Document Revision History
Date August 2001 18-Oct-2001 29-Nov-2001 06-Mar-2002 17-May-2002 31-May-2002 Version First Issue SO32 Package Mechanical Data added (Figure Table Note removed from Ordering Information Scheme Document status changed Data Sheet Document globally revised PDIP32 Package added (Figure Table Chip Enable Data Retention clarified (Figure Table Revision Details
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M68AF127BL
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners. 2002 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
19/19
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