operate MAX+PLUS Compiler, Timing Analyzer, Simulator from command pro
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MAX+PLUS Command-Line Mode
operate MAX+PLUS Compiler, Timing Analyzer, Simulator from command prompt under UNIX, Microsoft Windows Microsoft Windows
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MAX+PLUS Getting Started
MAX+PLUS from command prompt, type: maxplus2 <batch option(s)> <I/O option(s)> <project name> Multiple batch options used single project; multiple projects processed with same command line. <project name> indicates options that project. <batch options> follows: Batch Option: -help -version -compile -ta_delay -ta_setup -ta_reg -simulate -ignore_errors Action: displays information about command line options displays MAX+PLUS version number runs Compiler runs Timing Analyzer Delay Matrix mode runs Timing Analyzer Setup/Hold Matrix mode runs Timing Analyzer Registered Performance mode runs Simulator ignores errors from Compiler, Simulator, Timing Analyzer, continues processing other projects specified same command line, even processing previous project failed
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Appendix MAX+PLUS Command-Line Mode
<I/O options> shown below. each option, <filename> defaults <project name> specify empty quotation marks (""). Option: -tao "<filename>" Action: saves Timing Analyzer output <filename>.tao; this option used, <project name>.tao generated automatically uses <filename>.scf source simulation vectors; this option used, file specified with SIMULATION_INPUT_FILE variable <project name>.acf used automatically uses <filename>.vec source simulation vectors uses <filename>.cmd file source simulation commands saves Simulator output <filename>.tbl records Simulator history <filename>.hst
-scf "<filename>"
-vec "<filename>" -cmd "<filename>" -tbl "<filename>" -hst "<filename>"
redirect MAX+PLUS warning error messages ASCII file. UNIX, instead noclobber variable set.)
following example compiles upcntr project; compiles chiptrip project; runs timing analysis chiptrip Registered Performance mode; simulates chiptrip using test.scf source vectors:
maxplus2 upcntr -ta_reg -scf "test.scf" chiptrip
following example compiles chiptrip project, overwriting existing message.out file:
maxplus2 chiptrip message.out
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MAX+PLUS Getting Started
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Altera Support Services
support team dedicated resolving your technical issues quickly. Altera responds your questions promptly efficiently telephone, fax, e-mail. Applications Engineers located Altera headquarters Jose, California, locations around world. Altera Applications, Literature, Marketing Departments offer following services:
Product information Technical support Technical publications Training courses
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MAX+PLUS Getting Started
Contacting Altera Support Services
Table describes support services.
Table B-1. Altera Support Services (Part
Support Service Product Information Contact Information Note Tel: (408) 544-7104 E-mail: news@altera.com WWW: http://www.altera.com BBS: 544-6421 Note site: ftp@altera.com contact your local Altera distributor sales office Technical Support U.S. Canada Only: Hotline: (800) 800-EPLD (408) 544-7000 Worldwide: Tel: (408) 544-7000 Fax: (408) 544-6401 WWW: http://www.altera.com BBS: 544-6421 Note site: ftp@altera.com E-mail: sos@altera.com Contact your local Altera distributor sales office design evaluations on-site support Direct technical support Altera devices software available from Altera Applications Department between hours 6:00 a.m. 6:00 p.m. Pacific Time, Monday through Friday. Applications Engineers Altera Field Applications Engineers located around world evaluate customer designs, recommend efficient design methods devices that will best meet your needs, estimate device performance, demonstrate MAX+PLUS software, provide onsite training. world-wide (WWW) site provides access Atlas technical support database, product information technical publications. site transfer files from Altera Applications Department technical support review. site also provide software utilities technical publications. Notes: e-mail, world-wide (WWW) site, bulletin board service (BBS), File Transfer Protocol (FTP) site available hours day. requires Bell Standard 212, CCITT standard, compatible modem 14,400 bps, using data bits, stop bit, parity. Description Up-to-date information Altera products available from Altera Marketing Department between hours 8:00 a.m. 5:00 p.m. Pacific Time, Monday through Friday.
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Appendix Altera Support Services
Table B-1. Altera Support Services (Part
Support Service Technical Publications Contact Information Note Tel: (888) 3-ALTERA E-mail: lit_req@altera.com WWW: http://www.altera.com BBS: 544-6421 Note site: ftp@altera.com Description Altera produces variety technical literature help select design with programmable logic, including application notes data sheets. Altera also provides News Views, quarterly newsletter that includes latest information Altera products, technical articles written Altera Applications Engineers, question answer section that addresses many commonly asked questions. registered users Altera products receive News Views.
Training Courses
Altera provides variety training courses teach innovative efficient design techniques. With these contact your local Altera sales courses, discover time-saving features MAX+PLUS development office system, explore design features device families, simply learn about Altera products. Altera Training Administrator: Tel: 544-7000
Notes: e-mail, world-wide (WWW) site, bulletin board service (BBS), File Transfer Protocol (FTP) site available hours day. requires Bell Standard 212, CCITT standard, compatible modem 14,400 bps, using data bits, stop bit, parity.
MAX+PLUS Help up-to-date information Altera contact information.
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MAX+PLUS Getting Started
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Additional Workstation Configuration Information
This section describes change additional workstation configuration items that control appearance MAX+PLUS windows, serial port configuration, screen height width, printer ports, fonts.
Customizing MAX+PLUS Colors Using mwcolormanager Utility Environment Variables Fonts. Printers
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MAX+PLUS Getting Started
Customizing MAX+PLUS Colors
customize colors various elements MAX+PLUS window editing ASCII-format win.ini file, which copied into home directory>/windows directory first time MAX+PLUS settings this file determine colors basic window elements when Windows selected. more information about changing user interface, page 288. contrast, Color Palette command (Options menu) MAX+PLUS determines colors specific objects displayed individual MAX+PLUS application windows. [colors] section win.ini defines color various elements MAX+PLUS window. Three values range define amount red, green, blue (RGB) that determine color each element. following table shows [colors] section sample win.ini file brief description each window element. Component Value: Background=192 AppWorkspace=255 Window=255 Description:
Desktop background MAX+PLUS workspace MAX+PLUS application workspace WindowText=0 Window text Menu=255 Window background MenuText=0 Menu text ActiveTitle=0 Active window title InactiveTitle=255 Inactive window title TitleText=255 Title text active window ActiveBorder=192 Active window border InactiveBorder=192 Inactive window border WindowFrame=0 Window frame ScrollBar=192 Scroll background ButtonFace=192 Button front surface ButtonShadow=128 Shadow (i.e., darker edges) unpressed button
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Appendix Additional Workstation Configuration Information
Component Value: ButtonText=0 GrayText=128 Hilight=0 HilightText=255 InactiveTitleText=0 ButtonHilight=255
Description: Text face button Text color when menu command unavailable Background behind highlighted text Highlighted text Text title inactive window Lighter edges unpressed button
following table shows values standard colors normally available color monitor. edit colors [colors] section your win.ini file using these values change color various window components. availability other colors depends capabilities your display system. Color: White Light Gray Dark Gray Black Dark Green Dark Green Blue Dark Blue Yellow Dark Yellow Magenta Dark Magenta Cyan Dark Cyan Red: Green: Blue:
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MAX+PLUS Getting Started
appearance colors MAX+PLUS satisfactory, editing win.ini file does help problem, should select Windows either setting MWLOOK environment variable described page 290, with Change Look system menu.
Using mwcolormanager Utility
Altera provides mwcolormanager utility correct color flickering problems that might occur when change MAX+PLUS from another application window. another application changes system colors after have started MAX+PLUS colors MAX+PLUS window elements change when return MAX+PLUS correct color flickering problems when changing applications, insert following line first command your .xinitrc file: mwcolormanager [-display <display>][-extra <nn>]9 -display <display> option allows specify different display than default listed DISPLAY variable your .cshrc shell users) .profile (Bourne Korn shell users) file. -extra <nn> option allows specify number colors addition colors that allocated default. Because MAX+PLUS only uses colors, should this option.
Environment Variables
MAX+PLUS uses environment variables configure various options locate files. MAX+PLUS initializes them when installed, wish change them optimize your system performance. using shell, environment variables located your .cshrc file, have following format: setenv <environment variable> <value>
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Appendix Additional Workstation Configuration Information
using Bourne Korn Shell, environment variables located your .profile file, have following format: <environment variable>=<value>
MAX2_HOME
MAX2_HOME variable specifies name MAX+PLUS home directory. default /usr/maxplus2. should this variable only system displays error message indicating that MAX+PLUS files cannot found when start program.
MAX2_PLATFORM
MAX2_PLATFORM variable specifies name platform used MAX+PLUS should this variable only following error message displayed when start program: Unable determine type system using. following table lists supported MAX+PLUS platform names corresponding variable values: Platform Name: SPARCstation running SunOS 4.1.3+ SPARCstation running Solaris 2.5+ 9000 Series 700/800 RISC System/6000 Variable Value: sunos solaris rs6000
MWCOM1, MWCOM2, MWCOM3 MWCOM4
These variables control mapping serial ports MAX+PLUS which MAX+PLUS accesses names COM1 through COM4, corresponding UNIX serial ports. Table shows default variable values.
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MAX+PLUS Getting Started
Table C-1. Serial Ports
Platform Name RISC System/6000 SPARCstation running SunOS 4.1.3 SPARCstation running Solaris 9000 Series 700/800 MWCOM1 /dev/tty0 /dev/ttya dev/term/0 /dev/ttyd00 MWCOM2 /dev/tty1 /dev/ttyb dev/term/1 /dev/ttyd01 MWCOM3 /dev/tty1 /dev/ttyc dev/term/2 /dev/ttyd02 MWCOM4 /dev/tty1 /dev/ttyd dev/term/3 /dev/ttyd03
change default mapping reassign port UNIX serial ports. example, MWCOM1=/dev/ttyc binds ttyc serial port COM1, replacing default port ttya.
MWFONT_CACHE_DIR
MWFONT_CACHE_DIR variable specifies name MAX+PLUS font cache directory. default directory home directory>/ windows.
MWLOOK
MWLOOK variable controls initial MAX+PLUS software workstation. MWLOOK take following values: Value: motif windows Effect: OSF/Motif look feel Microsoft Windows look feel
default value MWLOOK windows.
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Appendix Additional Workstation Configuration Information
MWRGB_DB
MWRGB_DB variable specifies full pathname file rgb.txt, which maps color names 24-bit color values server. MWRGB_DB used, program looks rgb.txt following directories, order: /usr/openwin/lib /lib /usr/X/lib /usr/lib/X11
MWSCREEN_HEIGHT MWSCREEN_WIDTH
MWSCREEN_HEIGHT MWSCREEN_WIDTH variables control literal size objects screen. They actual screen height width your display, millimeters. default values those server.
MWSYSTEM_FONT
MWSYSTEM_FONT variable specifies default system font used MAX+PLUS this variable used, default font Helvetica. change system font, this variable existing font name. more information, page 292.
MWUNIX_SHARED_MEMORY
MWUNIX_SHARED_MEMORY variable determines whether MAX+PLUS UNIX shared memory when shares data with another program. MWUNIX_SHARED_MEMORY true, MAX+PLUS UNIX shared memory, which improve speed performance. false (the default value), MAX+PLUS uses shared memory server when shares data with another program. This shared memory allows data exchanges between programs that different machines, which displayed same server.
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MAX+PLUS Getting Started
MWWM
MWWM variable determines which window manager used system. MWWM take following values: Value: OLWM Effect: uses Motif window manager uses OpenLook window manager uses standard window manager
MAX+PLUS automatically detects whether using Motif OpenLook. This variable should used only using standard window manager, TWM.
Fonts
MAX+PLUS installs fonts necessary normal operation. default, these fonts located home directory>/maxplus2/fonts directory.
Adding Fonts
fonts your system performing following steps: Copy fonts into font directory (/usr/lib/x11/fonts default) restart server. Copy fonts into /usr/maxplus2/fonts directory. Make font directory file (font.dir) running mkfontdir utility (bldfamily utility SunOS). Type xset /usr/maxplus2/fonts prepend font.dir file front existing font path.
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Appendix Additional Workstation Configuration Information
Type xset rehash reinitialize font cache server. Depending your operating system, perform following: Solaris, HP-UX, with Common Desktop Environment (CDE) (autostart enabled), through following steps: line DTSOURCEPROFILE=true .dtprofile file your home directory. Edit .login file your home directory read follows (the following example shell users): if(!$?DT) then <all text from your original .login file> else xset /usr/maxplus2/fonts xset rehash endif SunOS Solaris (without Common Desktop Environment), following line .xinitrc your home directory directory your font path each time server started:
xset /usr/maxplus2/fonts system default version .xinitrc file, called Xinitrc, available /usr/openwin/lib/ directory.
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MAX+PLUS Getting Started
Font Aliases
[FontSubstitutes] section win.ini file home directory>/windows directory provides aliases font names. These aliases used bind MAX+PLUS font names font names available under server. following example shows default font substitution list: [FontSubstitutes] Helv=helvetica Sans Serif=ms sans serif Rmn=times Serif=times Times Roman=times Arial=helvetica
Printers
MAX+PLUS uses Postscript printer driver support Postscript printers under UNIX.
Installing Printer
following examples show edit various sections win.ini file install printer. [windows] device=Apple LaserWriter NT,PSCRIPT,LPT1 device variable [windows] section defines default printer using following syntax: device=<output device name>,<device driver>,<port connection> MAX+PLUS uses PSCRIPT keyword <device driver> specify Postscript printer driver.
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Appendix Additional Workstation Configuration Information
[ports] lpt1:=lp "%s" lpt2:=lp -dps1700 "%s" lpt3:= [ports] section lists communication printer ports available MAX+PLUS Windows LPTn: variables equated UNIX commands. this example, LPT1 LPT2 equated print command MAX+PLUS prints output intermediate Postscript file, which then substituted term "%s". term -dps1700 example refers UNIX printer named ps1700 that should defined UNIX printcap file. [PrinterPorts] Apple LaserWriter NT=PSCRIPT,LPT1:,15,90 Postscript Printer QMS=PSCRIPT,LPT2:,15,90 [PrinterPorts] section lists active inactive output devices that accessed printer drivers, specifies ports which output devices connected, specifies time-out values. example, Apple LaserWriter printer connected PSCRIPT queue, connected LPT1. MAX+PLUS ignores time-out values.
Printer Fonts
[PSFontSubstitutes] section win.ini file specify aliases actual printer fonts match fonts MAX+PLUS following example shows default font substitute list: [PSFontSubstitutes] Helv=Helvetica helvetica=Helvetica Sans Serif=Helvetica Rmn=Times Roman Serif=Times Roman Times Roman=Times Roman Arial=Helvetica courier=Courier
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MAX+PLUS Getting Started
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Glossary
This glossary defines selected terms used MAX+PLUS documentation. Choose Glossary (Help menu) view full MAX+PLUS glossary on-line.
Glossary
Glossary
Assignment Configuration File. active-high node node that activated when assigned value AHDL Verilog VHDL) (e.g., ena, clk). active-low node node that activated when assigned value zero AHDL Verilog VHDL) (e.g., clrn, prn, oen). AHDL design files, active-low node should assigned default value with Defaults Statement. Altera Design File.
AHDL Altera Hardware Description Language. Altera Design File (.adf) ASCII-format file (with extension .adf) Boolean equation entry, used with A+PLUS software. ADFs netlist format Boolean equations describe design. MAX+PLUS Compiler automatically translates into Compiler Netlist File (.cnf) during project compilation. also generated when State Machine File (.smf) compiled. Altera Hardware Description Language (AHDL) high-level, modular language that completely integrated into MAX+PLUS system. create AHDL Text Design Files (.tdf) with
Glossary
Glossary
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MAX+PLUS Getting Started
MAX+PLUS Text Editor standard text editor, then compile, simulate, program your projects within MAX+PLUS AHDL supports Boolean equation, state machine, conditional, decode logic. AHDL also allows create parameterized functions, includes full support functions Library Parameterized Modules (LPM). Text Design Export files (.tdx) Text Design Output Files (.tdo) generated MAX+PLUS Compiler also written AHDL syntax. Altera Megafunction Partner Program (AMPP) program that offers support third-party vendors create distribute megafunctions with MAX+PLUS must enter password Megacore/AMPP Licenses dialog (accessed through Authorization Code command Options menu) enable particular megafunction implementation design file. Additionally, some vendors provide option view edit megafunction design file. information current AMPP vendors, available megafunctions, passwords, contact Altera Marketing. ancillary file file that associated with MAX+PLUS project, design file project hierarchy tree. Most ancillary files also contain design logic. User-editable ancillary files with same filename project appear Hierarchy Display window. following list:
Editable Ancillary Files: Assignment Configuration File (.acf) Assignment Configuration Output File (.aco) Command File (.cmd) EDIF Command File (.edc) File (.fit) FLEX Chain File (.fcf) Hexadecimal (Intel-format) File (.hex) History File (.hst) Include File (.inc) File (.jam) JTAG Chain File (.jcf) Library Mapping File (.lmf) File (.log) Memory Initialization File (.mif) Memory Initialization Output File (.mio) Message Text File (.mtf) Programmer File (.plf) Report File (.rpt) Serial Vector Format File (.svf) Simulator Channel File (.scf) Standard Delay Format (SDF) Output File (.sdo) Symbol File (.sym) Table File (.tbl) Tabular Text File (.ttf) Text Design Export File (.tdx) Text Design Output File (.tdo) Timing Analyzer Output File (.tao) Vector File (.vec) VHDL Memory Model Output File (.vmo) Non-Editable Ancillary Files: Compiler Netlist File (.cnf) Hierarchy Interconnect File (.hif) JEDEC File (.jed) Node Database File (.ndb) Programmer Object File (.pof) Binary File (.rbf) Serial Bitstream File (.sbf) Simulator Initialization File (.sif) Simulator Netlist File (.snf) SRAM Object File (.sof)
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Glossary
area marquee Graphic Symbol Editors, rectangular boundary surrounding area selection, which created dragging Button with Selection tool. Hierarchy Display, rectangular border that visible drag mouse select area. marquee visible only while dragging mouse. area selection defined rectangular region that includes more adjacent objects. Graphic Symbol Editors, this area contained within rectangular border called area marquee. Waveform Editor, Floorplan Editor, Hierarchy Display, objects within area selection highlighted. Area selection process selecting multiple contiguous objects dragging Button with Selection tool. Waveform Editor, such consist adjacent nodes groups, whole waveforms, intervals more waveforms. Floorplan Editor, such consist adjacent pins, nodes, logic cells, assignment bins. Hierarchy Display, file icons selected. Graphic Symbol Editors, symbols, arcs, circles, diagonal lines, text blocks must completely within area marquee selected. When orthogonal line crosses marquee, only portion within marquee selected. array group. ASCII American Standard Code Information Interchange. Text editing software used MAX+PLUS text file, e.g., Text Design File (.tdf), Library
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Mapping File (.lmf), Vector File (.vec), must conform this textual data coding system. assignment AHDL VHDL, assignment refers transfer value symbolic name group, usually through Boolean equation. value right side equation assigned symbolic name group left. assignment (resource) resource assignment. Assignment Configuration File (.acf) ASCII file (with extension .acf) that stores information about probe, pin, location, chip, clique, logic option, timing, connected pin, local routing, device assignments, well configuration settings Compiler, Simulator, Timing Analyzer entire project. stores information entered with menu commands MAX+PLUS applications, well pin, location, chip assignments entered Floorplan Editor window. also edit manually Text Editor window.
Glossary
Glossary
back-annotation process copying device resource assignments made Compiler, which stored File (.fit), into Assignment Configuration File (.acf) project. back-annotation process preserves current future compilations. background process application command that unattended perform another task which generate messages Message Processor window. following
MAX+PLUS Getting Started
MAX+PLUS applications commands background processes:
Compiler Programmer Simulator Timing Analyzer Reader Waveform Editor Import Vector File command (File menu) MAX+PLUS Project Archive command (File menu)
Boolean logic Logic that obeys theorems Boolean algebra (George Boole, Laws 1854). Boolean portion design portion which implemented AND-OR matrix device. branches extensions hierarchy tree that represent different levels hierarchy. branch consists design filename, file icon, ancillary file icons. intersections branches indicated branch buttons. Connection arrows lead from higher-level branches lower-level branches. breakpoint user-defined conditions that will interrupt simulation when fulfilled. buried node combinatorial registered signal that does drive output pin. buried register register Altera device that does drive output pin. buried register located logic cell that output pin. buried register used implement internal logic. thick line Graphic Editor file that represents multiple nodes. carries multiple signals between components design, represent from nodes (i.e., bits). AHDL Waveform Editor files, group synonymous with bus. VHDL, guarded signal that have drivers, i.e., signal sources, turned off. VHDL, called array, limited symbolic names. example array type STD_LOGIC_VECTOR. Section 3.2.1:
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balloon text Pop-up text Floorplan Editor that provides information item under mouse pointer, such pin, cell, logic cell, embedded cell, assignment bin. Information displayed following formats: <node name> <cell number> <pin name> <pin number> (<pin function> (<dedicated name>)) where <pin name> <cell name> replaced text <none> item assigned particular resource. multiple functions assigned resource, first names listed, followed text etc. there additional names. last compilation floorplan, text (unrouted) appears after node name items that successfully. batch mode simulation mode which Simulator commands executed from Command File (.cmd) rather than from on-screen options menu commands. binary base number system (radix). Binary digits
Glossary
Array Types IEEE Standard VHDL Language Reference Manual more information. Only one- twodimensional arrays scalar elements supported. Verilog HDL, array nets, limited symbolic names. section 3.3: Vectors IEEE Standard Hardware Description Language Based Verilog Hardware Description Language manual more information. group) name name group) nodes. single-range dual-range name consists name characters, followed ranges numbers arithmetic expressions brackets. (Dual-range names supported Waveform Editor files.) start number range separated periods. Each number sequence represents individual node bit). Example: a[4.1] consists nodes Example: b[2.1][1.0] consists nodes b2_1, b2_0, b1_1, b1_0. sequential name, consisting commaseparated list names, entered AHDL Text Design Files (.tdf) Graphic Design Files (.gdf). TDFs only, this list names must enclosed parentheses. Sequential names include singleand dual-range names. Example: a[3.0],dout[6.4],z3 first name series names single-range, dual-range, sequential name most significant (MSB)
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bus; last name least significant (LSB). arbitrary name, consisting name characters, entered Waveform Design File (.wdf), Simulator Channel File (.scf), Vector File (.vec). arbitrary name does indicate many members included bus. pinstub location boundary mega- macrofunction symbol, represented Symbol File (.sym), that represents multiple inputs outputs function. (thick line) drawn Graphic Editor file must connect pinstub with same number bits recognized connection function.
Glossary
ByteBlaster Parallel download cable that allows users program configure devices in-system. ByteBlaster provides programming support 7000S 9000 devices, configuration support FLEX 6000, FLEX 8000, FLEX devices. Multi-device JTAG chain programming configuration also available FLEX 10K, 7000S, 9000 devices. Multi-device FLEX chain configuration available FLEX 6000, FLEX 8000, FLEX devices. ByteBlaster connected parallel printer port fully populated DB25-to-DB25 cable. 10-pin female plug connects 10-pin male header circuit.
Glossary
MAX+PLUS Getting Started
chip group logic functions defined single, named unit. chip assigned actual device either user Compiler. make chip assignments logic functions design files. Items that assigned same chip placed same device during compilation. term device always refers actual programmable logic device, whereas term chip always refers group logic functions. When Compiler processes project, each chip name assigned corresponding programming file particular device. Classic Altera device family based original EPROM-based EPLD architecture. MAX+PLUS provides support following Classic devices: EP600I, EP610, EP610I, EP900I, EP910, EP910I, EP1800I, EP1810 devices. Clear input signal that resets register. synchronous Clear signal resets each rising falling Clock edge. asynchronous Clear signal resets regardless Clock signal. clique group logic functions defined single, named unit. Compiler attempts keep clique members together when fits project. clique assignment allows group logic speed-critical path, thus improving performance. possible, clique members assigned same LAB. clique members will into single LAB, they placed
same FLEX 10K, FLEX 8000, FLEX 6000, 9000 devices only) same device. Clock signal that triggers registers. flipflop state machine, Clock edge-sensitive signal. output flipflop change only Clock edge. example, flipflop, input value stored placed output Clock edge. some cases, MAX+PLUS lists Latch Enable input latch Clock, e.g., Delay Matrix timing analysis. Clock Enable level-sensitive signal enabled flipflop, i.e., flipflop with suffix, including DFFE, TFFE, SRFFE, JKFFE. When Clock Enable low, Clock transitions Clock input flipflop ignored. column vertical line LABs connected column FastTrack Interconnect path FLEX 10K, FLEX 8000, FLEX 6000, 9000 device. RS-232 port RS-232 serial communication port UNIX workstation. BitBlaster, which used configure program devices insystem, must connect port. combinatorial feedback Feedback from logic cell that goes back into logic array. direct function inputs logic cell, does retain values from earlier inputs. combinatorial output Output from logic cell that direct function inputs, without regard Clock; i.e., does retain values resulting from earlier inputs.
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Glossary
Command File (.cmd) ASCII text file (with extension .cmd) that contains commands batch-mode simulation. comment Graphic Symbol Editors, comment free-floating block text used document design. associated with object. comment stands alone anywhere within Graphic Editor files. comment also stands alone within symbol border Symbol Editor file. Comments ignored Compiler, used document various sections file. Waveform Editor, comment line text used annotate waveforms waveform drawing area associated with waveform. comment anchored time time scale where first character entered. label appears Name field indicate comment line; when comment added between existing nodes, appears blank space, which inserted between waveforms. Comments ignored Compiler. MAX+PLUS text files except VHDL Design Files (.vhd), Verilog Design Files (.v), Assignment Configuration Files (.acf), e.g., Report Files (.rpt), Vector Files (.vec), Text Design Files (.tdf), comment string characters enclosed percent symbols (%). insert comments wherever white space allowed text files. VHDL Design Files ACFs, comments begin with dashes continue End-of-Line. AHDL TDFs also support VHDL-style comments. VHDL-style comment TDF, must separate dashes from
preceding symbolic name with least space. Verilog Design Files, comments begin with slashes (//) continue End-of-Line. Verilog Design Files ACFs also support comments consisting string characters enclosed between characters. Compiler Netlist File (.cnf) binary file (with extension .cnf) that contains data from design file. created Compiler Netlist Extractor module MAX+PLUS Compiler. Configuration EPROM family serial EPROMs, which designed configure FLEX 6000, FLEX 8000, FLEX devices. This device family includes EPC1, EPC1213, EPC1064, EPC1064V, EPC1441 devices. connection entered intersection signal lines (nodes buses) Graphic Editor file. connection indicates that signals logically connected. construct unit text design language such AHDL, VHDL, Verilog HDL, EDIF. continuity checking test open circuits between device pins programming adapter sockets. This test verifies that device properly seated socket adapter. cutoff node node that excluded from timing analysis. signal associated with node from timing analysis tagging with Timing Analysis Cutoff command.
Glossary
Glossary
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MAX+PLUS Getting Started
database flattened representation design files MAX+PLUS project hierarchy. database used internally Compiler modules during compilation. decimal base number system (radix). Decimal digits through AHDL,VHDL, Verilog special notation needed indicate decimal digits. default Simulator Channel File (.scf) Simulator Channel File (.scf) that contain nodes groups that Simulator Netlist File (.snf) project. created automatically with Enter Nodes from command (Node menu) Waveform Editor. default timing tagging Timing Analyzer provides following default node tagging timing analysis: Analysis Mode: Default Tagging: Delay Matrix input pins sources; output pins destinations. input pins sources; data Clock inputs registers, Latch Enable inputs latches, data, address, Write Enable inputs asynchronous destinations. outputs registers sources; data Clock Enable inputs registers destinations.
delimiter text string, character, keyword used define beginning statement construct text file. example, delimiters AHDL group ranges comment delimiter many MAX+PLUS text files. design file file that contains logic MAX+PLUS project compiled Compiler. following files design files:
Altera Design File (.adf) EDIF Input File (.edf) Graphic Design File (.gdf) OrCAD Schematic File (.sch) State Machine File (.smf) Text Design File (.tdf) Verilog Design File (.v) VHDL Design File (.vhd) Waveform Design File (.wdf) Xilinx Netlist Format File (.xnf)
Setup/Hold Matrix
asterisk indicates design files that exist top-level files hierarchical projects. Other design files must only design file project must exist bottom level hierarchical project. destination node node that tagged (designated) destination signal purpose timing analysis. destination node tagged with Timing Analysis Destination command (Utilities menu), node that input logic function pin. device device refers Altera programmable logic device, including Classic, 5000, 7000, 9000,
Registered Performance
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Glossary
FLEX 6000, FLEX 8000, FLEX device families. Altera also offers Configuration EPROM devices which used configure FLEX 6000, FLEX 8000, FLEX devices. device assignment device assignment assigns user-specified block logic functions, called chip, specific Altera device. device family group Altera programmable logic devices with same fundamental architecture. Altera families include Classic, 5000, 7000, 9000, FLEX 6000, FLEX 8000, FLEX 10K, device families. device option option that controls device. Altera devices offer following device options: Option: Auto-Restart Configuration Frame Error Disable Start-Up Time-Out Enable Chip-Wide Output Enable Enable Chip-Wide Reset Enable DCLK Output User Mode Enable INIT_DONE Output Enable JTAG Support Device Family: FLEX 6000, FLEX 8000, FLEX FLEX 8000 FLEX 6000 FLEX FLEX 6000 FLEX FLEX 8000
Option: Enable LOCK Output JTAG User Code Low-Voltage Release Clears Before Tri-States Security
Device Family: FLEX FLEX FLEX 6000, FLEX 8000, FLEX Classic, 5000, 7000, 9000 Classic, 5000, 7000, 9000 (Logic Cell Turbo applied logic cells 7000 9000 device.) FLEX 6000 FLEX 7000S 9000 FLEX 6000, FLEX 8000, FLEX
Turbo
Low-Voltage Configuration EPROM User Code User-Supplied Start-Up Clock
Glossary
Glossary
dual feedback combination feedback register combinatorial feedback same logic cell. dynamic models Models that represent actual combinatorial logic timing Simulator Netlist Files (.snf). Dynamic models generated logic timing when Optimize Timing command (Processing menu) turned Instead processing combinatorial logic, Simulator Timing Analyzer refers representative dynamic model.
FLEX 6000 FLEX 7000S, FLEX 6000, FLEX 8000
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MAX+PLUS Getting Started
Dynamic models allow simulation faster; however, Compiler requires additional time generate SNF.
(.edo) created EDIF Netlist Writer module. EDIF Input File (.edf) EDIF version netlist file generated standard EDIF netlist writer. EDIF Input Files (with extension .edf) compiled MAX+PLUS Compiler. MAX+PLUS supports EDIF Input Files that contain functions from Library Parameterized Modules (LPM). EDIF Output File (.edo) EDIF version netlist file (with extension .edo) generated EDIF Netlist Writer module Compiler. This file exported industry-standard UNIX workstation environment simulation. EEPROM Electrically Erasable Programmable Read-Only Memory. form reprogrammable semiconductor memory which contents (program) erased subjecting device appropriate electrical signals. Embedded Array Block (EAB) physically grouped embedded cells that implement memory (RAM ROM) combinatorial logic FLEX device. consists embedded cell array, with data, address, control signal inputs data outputs that optionally registered. single implement memory block 1,024 2,048 bits. Each embedded cell within implements bits memory. memory blocks these sizes, outputs, respectively. Multiple EABs combined create larger memory blocks.
Embedded Array Block. embedded cell.
EDIF Electronic Design Interchange Format. industry-standard format transmission design data. generate EDIF netlist file from schematic design from VHDL Verilog design that been processed with appropriate industry-standard synthesis tool then import file into MAX+PLUS EDIF Input File (.edf). MAX+PLUS supports EDIF Input Files that contain functions from Library Parameterized Modules (LPM). MAX+PLUS Compiler also generate more EDIF Output Files (.edo) either EDIF format that contain functional timing information simulation with standard EDIF simulator. MAX+PLUS EDIF Netlist Reader EDIF Netlist Writer modules have been awarded Electronic Industries (EIA) EDIF version Self-Verification Seal Approval. This award indicates that MAX+PLUS EDIF support successfully completed testing process ensure compliance with EDIF Netlist View standard. EDIF Command File (.edc) ASCII text file (with extension .edc) used customize format EDIF Output Files
Altera Corporation
Glossary
interconnect paths dedicated input bus. embedded cell (EC) memory element that exists embedded array FLEX device, which implement memory (RAM ROM) combinatorial logic. Embedded Array Block (EAB) consists group embedded cells that implement memory block 1,024 2,048 bits. Each embedded cell within implements bits memory. Depending depth memory, embedded cells have outputs. memory blocks 1,024 2,048 bits, outputs, respectively. Embedded cells have format EC<number>_<row letter>, where <number> ranges from <row letter> consists letter EAB. EPLD Erasable Programmable Logic Device, i.e., Altera device that member Classic, 5000, 7000, 9000 device families. EPROM Erasable Programmable ReadOnly Memory. form reprogrammable semiconductor memory which contents (program) erased subjecting device ultraviolet light proper wavelength. evaluated function mathematical function that evaluates arithmetic expression returns value based more arguments. AHDL Define Statement used create evaluated
functions. following example shows definition evaluated function MAX:
DEFINE MAX(a,b)
expander product term single product term with inverted output that feeds back into Logic Array Block (LAB) 5000, 7000, 9000 device. uncommitted expander product term that shared with other logic cells same called shareable expander; product term that been shared this manner called shared expander. 7000 9000 devices only, expander product term that from adjacent logic cell same called parallel expander. extension filename extension.
Glossary
Glossary
family-specific mega- macrofunction Altera-provided mega- macrofunction that contains logic optimized architecture specific device family. functionality family-specific megaor macrofunction always same, regardless device family which designed. However, actual primitives nodes used within mega- macrofunction file vary from family family take advantage different device architectures, thus providing higher performance and/or more efficient implementation.
Altera Corporation
MAX+PLUS Getting Started
fan-in fan-out Fan-in refers input signals that feed input equations logic cell. Fan-out refers output signals that output equations logic cell. FastTrack Interconnect Dedicated connection paths that span entire width height FLEX 6000, FLEX 8000, 9000, FLEX device. These connection paths allow signals travel between Logic Array Blocks (LABs) device. FLEX Chain File. file icon icon that appears MAX+PLUS application window represents file current hierarchy tree. Double-clicking Button icon opens file that represents. Hierarchy Display, file icon shows which MAX+PLUS editor open file. filename extension displayed bottom file icon show file type; filename displayed left file icon. Compiler, file icons show input output files current project. filename name design file, ancillary file, other file, without extension. single filename contain name characters, plus 3-character filename extension. full pathname plus filename extension contain characters. Because Windows Windows Workgroups 3.11 support only 8-character
filenames, MAX+PLUS maps longer filenames Windows operating systems 8-character filenames default. These filename mappings stored maxplus2.idx file each directory that contains long filenames. However, override this behavior built-in support long filenames available Windows Windows setting USE_WINNT_LONG_FILENAMES variable [system] section your maxplus2.ini file Hierarchy Display window, filename, along with file icon filename extension, represents file current hierarchy tree. filename extension one, two, threeletter extension filename that follows period (.). Hierarchy Display window, filename extension, along with filename file icon, represents file current hierarchy current project. File (.fit) ASCII file (with extension .fit) generated Compiler that documents pin, logic cell, cell, embedded cell, chip, device assignments made during last compilation. Assignments recorded Assignment Configuration File (.acf) syntax. File used back-annotation functional testing Simulator Programmer. preserve assignments permanently, File assignments back-annotated into with Back-Annotate Project command (Assign menu).
Altera Corporation
Glossary
also display read-only version File information from most recent project compilation Floorplan Editor. FLEX Chain File (.fcf) ASCII file (with extension .fcf) that stores programming file names configuring multiple FLEX 6000, FLEX 8000, FLEX devices Passive Serial configuration scheme. saves information entered with MultiDevice FLEX Chain Setup command (FLEX menu). FLEX 6000 Altera device family based Flexible Logic Element MatriX architecture. This SRAM-based family offers high-performance, registerintensive, high-gate-count devices. FLEX 6000 device family includes EPF6016 device. FLEX 8000 Altera device family based Flexible Logic Element MatriX architecture. This SRAM-based family offers high-performance, registerintensive, high-gate-count devices. FLEX 8000 device family includes EPF8282V, EPF8282A, EPF8282AV, EPF8452A, EPF8636A, EPF8820A, EPF81188A, EPF81500A devices. Altera recommends using FLEX 8000A devices rather than FLEX 8000 devices designs. FLEX Altera device family based Flexible Logic Element MatriX architecture. This SRAM-based family offers high-performance, registerintensive, high-gate-count devices with embedded arrays. FLEX device family includes EPF10K100, EPF10K70,
EPF10K50, EPF10K40, EPF10K30, EPF10K20, EPF10K10 devices. FLEX devices, which include EPF10K50V, EPF10K130V, EPF10K250A devices, enhanced versions FLEX devices, function-, pin-, programming-filecompatible with FLEX devices. FLEX 10KA devices differ from FLEX devices that they 3.3-V versions FLEX devices. EPF10K100GC503-3DX device includes built-in ClockLock ClockBoost phase-locked loop circuitry. flipflop register edge-triggered, clocked storage unit that stores single data. low-to-high transition Clock signal changes output flipflop, based value data input(s). This value maintained until next low-to-high transition Clock, until flipflop preset cleared. Depending architecture device family, register programmed level-sensitive flowthrough latch edge-triggered D,T, flipflop. Verilog HDL, also used describe abstraction data storage device that MAX+PLUS Compiler uses infer registers. fMAX (maximum Clock frequency) maximum Clock frequency that achieved without violating internal setup hold time requirements. fMAX also timing assignment that specifies minimum acceptable Clock frequency. MAX+PLUS
Glossary
Glossary
Altera Corporation
MAX+PLUS Getting Started
specify required fMAX entire project and/or input (INPUT INPUTC), bidirectional (BIDIR BIDIRC input function), register. Function Prototype Specifies ports (pinstubs) primitive, megafunction, macrofunction AHDL. Function Prototype consists name function, list inputs outputs. mega- macrofunctions, Function Prototype also contain parameters that used specify characteristics function. Function Prototypes specified Function Prototype Statement. They often stored Include Files (.inc). Include Files that contain Function Prototypes Alteraprovided mega- macrofunctions located \maxplus2\max2lib\ mega_lpm \maxplus2\max2inc directories created during installation, respectively. UNIX workstation, maxplus2 directory subdirectory /usr directory.) implement instance mega- macrofunction AHDL, logic must defined design file Function Prototype must declared. (Function Prototypes optional primitives.) then create instance function with Instance Declaration in-line reference. When Module Instantiation Verilog HDL, MAX+PLUS Compiler uses port name ordering information AHDL Include Files that contain Function Prototypes implement instance logic function.
Graphic Design File.
glitch spike signal value pulse that occurs when logic level changes more times over short period. When Simulator timing linked simulation mode, define length glitch monitor project pulses shorter than defined value. Glitch detection available functional simulation mode. global signal pin- logic-driven signal that passes through global routing device before performing specified function. Clock, Preset, Clear, Output Enable signals global signals. Logic-driven global signals available only FLEX 6000 devices. global signal various ways:
During design entry with GLOBAL primitive. dedicated input drive global signal directly feeding output directly GLOBAL primitive. also output logic function global signal feeding output directly GLOBAL primitive. logicdriven global signal consumes dedicated global input pin. With Automatic Global option Global Project Logic Synthesis dialog (Assign menu). Compiler chooses pin-driven signal that feeds most flipflops global Clock, Preset, Clear, signal that feeds most buffers chosen global Output Enable.
Altera Corporation
Glossary
With Global Signal logic option Individual Logic Options dialog box, which open from Logic Options dialog (Assign menu). When this option turned input single-output logic function, equivalent using GLOBAL primitive. Turning this logic option prevents input from being used global signal.
specified with single-range group name, dual-range group name, sequential group name format. VHDL, group called array, limited symbolic names. Examples array types STD_LOGIC_VECTOR BIT_VECTOR. Section 3.2.1: Array Types IEEE Standard VHDL Language Reference Manual more information. Only oneand two- dimensional arrays scalar elements supported. Verilog HDL, group called array, limited symbolic names. Examples array types memories (which arrays register elements words) arrays gate instances registers. elements, instances, registers array specified with range. Section 3.3: Vectors, Section 3.8: Memories, Section Gate Switch Level Modeling IEEE Standard Hardware Description Language Based Verilog Hardware Description Language manual more information. Waveform Editor Simulator, group collection nodes that treated unit. these applications, group name specified with arbitrary group name single-range group name format. group name name.
low-level input voltage. default inactive node value. AHDL Text Design File (.tdf), used predefined constant keyword. VHDL Design File (.vhd), represented '0'. Verilog Design File (.v), represented Graphic Editor file, primitive symbol. represented logic level Simulator Waveform Editor. Graphic Design File (.gdf) schematic design file (with extension .gdf) created with MAX+PLUS Graphic Editor. OrCAD Schematic File (.sch) automatically translated into treated MAX+PLUS Graphic Editor Compiler. Gray code counting scheme which only time changes value between consecutive count values. contrast, binary count sequence does preclude more than changing consecutive count values. When only changes, noise susceptibility reduced circuit. group array AHDL, group collection symbolic names that treated unit. group name
Altera Corporation
Glossary
Glossary
hard logic function logic function design file that removed during standard logic synthesis therefore assigned physical resource such specific device, pin, logic cell, cell.
MAX+PLUS Getting Started
Graphic Design Files (.gdf) Text Design Files (.tdf), hard logic primitives/ ports include INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, BIDIRC, LCELL, MCELL, DFF, DFFE, TFF, TFFE,JKFF, JKFFE, SRFF, SRFFE, LATCH. However, INPUT INPUTC primitives that affect project outputs considered hard logic functions. When SOFT, TRI, OPNDRN primitives removed during logic synthesis, they also hard logic primitives. megafunction macrofunction that contains hard logic primitive considered hard logic function. Waveform Design Files (.wdf), hard logic functions input nodes output buried nodes with registered combinatorial node types. hexadecimal base number system (radix). Hexadecimal digits through through Hexadecimal numbers indicated with following notation:
Language
AHDL
Hexadecimal (Intel-Format) File (.hex) ASCII text file (with extension .hex) Intel hexadecimal format. MAX+PLUS Compiler Simulator Files inputs specify initial contents memory (e.g., ROM). MAX+PLUS Compiler automatically creates output Files containing configuration data Active Parallel (APU) configuration scheme FLEX 8000 devices, Passive Serial (PS) configuration scheme FLEX 6000 FLEX devices. After compilation, also create Files that support other configuration schemes FLEX 6000, FLEX 8000, FLEX devices. your project uses memory File specify initial contents, should name file with name that same project name chip name within project. Because Compiler automatically generates Files outputs FLEX 6000, FLEX 8000, FLEX devices, these output files overwrite your initial memory content files. hierarchical node symbol name unique name node symbol that based location hierarchy design files number AHDL,VHDL, Verilog instance name logic function which connected. Every node symbol project hierarchical name; also assign node name probe name node.
Notation
X"<series digits H"<series digits 16#<series digits 'h<series digits
VHDL Verilog
Examples: H"123AECF" (AHDL) 16#FF# (VHDL) 'h837FF (Verilog HDL)
Altera Corporation
Glossary
Hierarchy Interconnect File (.hif) ASCII file (with extension .hif) created Netlist Extractor module. This file specifies hierarchical interconnections between design files project. History File (.hst) ASCII file (with extension .hst) created MAX+PLUS Simulator. This time period records commands, buttons, onscreen options that used during simulation session, well their output. hold time flipflop, hold time minimum time period which signal must retained input that feeds data input Clock Enable after active transition input that feeds Clock input. latch, hold time minimum time period which signal must retained input that feeds input after active transition input that feeds Latch Enable input. asynchronous block, hold time minimum time period which signal must retained input that feeds data address inputs after active transition input that feeds Write Enable input. Internal hold times flipflops, latches, asynchronous RAM, which user-controllable, similarly constrain internally generated signals.
9000 device. cells permit short setup time. pre-version releases MAX+PLUS cells were known peripheral registers. feedback Feedback from output Altera device. allows output also used input pin. type direction signal travel node, pin, state machine. Graphic Symbol Editors, pins pinstubs have types input, output, bidirectional. AHDL, type port input, output, buried (i.e., buried output), machine input, machine output. Waveform Editor, type node input, output, buried (i.e., buried output). Input output types represent actual outputs; buried type always represents logic that does feed pin. in-circuit reconfigurability.
Glossary
Glossary
in-circuit reconfigurability (ICR) capability SRAM-based devices, such FLEX 6000, FLEX 8000, FLEX devices, load configuration data system power-up during normal system operation after they have been mounted printed circuit board. In-circuit reconfiguration performed unlimited number times with data from local PROM such Altera Configuration EPROM, with data downloaded external controller such MAX+PLUS
cell cell register (also known element) that exists periphery FLEX 10K, FLEX 8000,
Altera Corporation
MAX+PLUS Getting Started
Programmer. Programmer also provides capability configure more FLEX devices JTAG chain more FLEX 6000, FLEX 8000, FLEX devices FLEX chain. in-system programmability (ISP) capability EEPROM-based devices, such 9000 7000S devices, programmed after they have been mounted printed circuit board. MAX+PLUS Programmer supports in-system programming BitBlaster serial download cable ByteBlaster parallel download cable. Programmer also provides capability program multiple devices JTAG chain. Include File (.inc) ASCII text file (with extension .inc) that imported into Text Design File (.tdf) AHDL Include Statement. Include File replaces Include Statement that calls Include Files contain Function Prototype, Define, Parameters, Constant Statements. Include Files that contain Function Prototypes Altera-provided mega- macrofunctions located \maxplus2\max2lib\mega_lpm \maxplus2\max2inc directories created during installation, respectively. UNIX workstation, maxplus2 directory subdirectory /usr directory.) When Module Instantiation Verilog HDL, MAX+PLUS Compiler uses port name ordering information AHDL Include Files that contain Function Prototypes implement instance logic function. insertion point location which text graphics inserted.
dialog Text Editor window, insertion point appears flashing vertical bar. Graphic Symbol Editor, appears flashing square. Waveform Editor, insertion point waveform drawing area appears short horizontal line that extends right Time cursor. node/group information area, name blank space that selected interpreted insertion point. When type text, appears left insertion point, which moves right type. When enter paste symbols waveforms, upper left corner item(s) appears insertion point. instance logic function design file. Graphic Editor, instance represented symbol (net) number lower left corner; Waveform Editor, name node. AHDL, instances declared forms: Instance Declaration that declares variable type <primitive>, <megafunction>, <macrofunction>, in-line logic function reference. VHDL, instances logic functions declared with Component Instantiation Statement; registers also implemented with Register Inferences. Verilog HDL, instances declared with Module Instantiations Gate Instantiations. Hierarchy Display, instance mega- macrofunction represented function name, followed colon number. AHDL Variable Declaration VHDL Component Instantiation Statement, instance represented instance name followed colon function name.
Altera Corporation
Glossary
Verilog Module Gate Instantiation, instance represented module gate name, followed instance name. interactive mode simulation mode which choose on-screen options buttons, execute menu commands, with keyboard mouse. in-system programmability.
MAX+PLUS Programmer JEDEC File created with MAX+PLUS MAX+PLUS (DOS), A+PLUS, PLDshell Plus program Altera devices listed above. Programmer also optionally save programming data plus functional test vectors JEDEC File format. JTAG boundary-scan testing Testing that isolates internal circuitry from circuitry. This testing made possible Joint Test Action Group (JTAG) Boundary-Scan Test (BST) architecture that available FLEX devices; FLEX 8000 devices except EPF8452A EPF81188A; FLEX 6000 devices; 9000 devices; 7000S devices except EPM7064S. Serial data shifted into boundary-scan cells device; observed data shifted externally compared expected results. Boundary-scan testing offers efficient board testing, providing electronic substitute traditional test fixture. full partial JTAG architecture FLEX 10K, 9000, 7000S devices also supports in-system multidevice JTAG chain device programming configuration. JTAG chain multi-device JTAG chain. JTAG Chain File (.jcf) ASCII file (with extension .jcf) that stores device name, device order, optional programming file name information programming configuring more devices JTAG chain. saves information entered with Compiler Create File
File (.jam) ASCII file (with extension .jam) device programming test language that stores programming data programming, verifying, blank-checking more in-system programmable devices JTAG chain. files embedded processor-type programming environments. 7000S 9000 devices programmed with files. JTAG chain contain other device that complies with IEEE 1149.1 JTAG specification, including FLEX 10K, FLEX 6000, some FLEX 8000 devices. generate files with Create File command (File menu) Programmer Compiler. JTAG Chain File.
Glossary
Glossary
JEDEC File (.jed) ASCII file (with extension .jed) that contains programming information. JEDEC Files provide industry-standard format transferring information between data preparation system logic device programmer. MAX+PLUS Compiler automatically generates JEDEC Files Classic devices EPM5032 device during compilation.
Altera Corporation
MAX+PLUS Getting Started
command (File menu) Multi-Device JTAG Chain Setup command (JTAG menu).
keyword Words that reserved implementing syntax files used inputs MAX+PLUS including AHDL Text Design Files (.tdf), Assignment Configuration Files (.acf), Command Files (.cmd), EDIF Command Files (.edc), Library Mapping Files (.lmf), VHDL Design Files (.vhd), Verilog Design Files (.v) Vector Files (.vec). example, keyword cannot used unquoted symbolic name AHDL file.
Library Mapping File (.lmf) ASCII text file (with extension .lmf) used cells EDIF Input Files (.edf) symbols OrCAD Schematic Files (.sch) corresponding MAX+PLUS primitives, megafunctions, macrofunctions. Library Parameterized Modules (LPM) technology-independent library logic functions that parameterized achieve scalability adaptability. Altera implemented parameterized modules (also called from version 2.1.0 that offer architectureindependent design entry MAX+PLUS II-supported devices. MAX+PLUS Compiler includes built-in compilation support functions used schematic, AHDL, VHDL, Verilog HDL, EDIF input files. Library Mapping File.
Logic Array Block.
latch level-sensitive clocked storage unit that stores single data. highto-low transition Latch Enable signal fixes contents latch value data input until next low-to-high transition Latch Enable. Latch Enable level-sensitive signal that controls latch. When high, input flows through output; when low, output holds last value. logic cell.
Load input signal that loads data into register. synchronous Load signal loads data each rising falling Clock edge. asynchronous Load signal loads data regardless Clock signal. local routing resource assignment available FLEX 6000 devices that assigns fan-out node placed logic cell same node adjacent node. Local routing also available between node that placed logic cell periphery device output that feeds. Local routing assignments ensure that signals connected with shared local interconnect, which fastest interconnect available. Therefore, maximize your performance connecting logic speed-critical path with local routing.
least significant (LSB) binary number that contributes smallest quantity value that number, i.e., last member group name. example, group named a[31.0] a[0] a0).
Altera Corporation
Glossary
location generic term that refers assignable physical resource interior Altera device. assign logic function following locations:
5000 7000 devices, Programmable Interconnect Array (PIA) dedicated input bus. FLEX 6000, FLEX 8000, 9000, FLEX devices, FastTrack Interconnect paths dedicated input bus. logic cell (LC) generic term basic building block Altera device. Classic, 5000, 7000, 9000 devices, logic cell (also called macrocell) consists parts: combinatorial logic configurable register. combinatorial logic allows wide variety logic functions. FLEX 6000, FLEX 8000, FLEX devices, logic cell (also called logic element) consists look-up table (LUT), i.e., function generator that quickly computes function four variables, programmable register support sequential functions. register programmed flowthrough latch; flipflop; bypassed entirely pure combinatorial logic. register feed other logic cells feed back logic cell itself. Some logic cells feed output bidirectional pins device. assign logic function specific logic cell. also assign logic function logic array block (LAB), row, column ensure that function implemented logic cell particular LAB, row, column. FLEX 10K, FLEX 8000, FLEX 6000, 9000 devices, logic cells have format LC<number>_<LAB name>, where <number> ranges from <LAB name> consists letter
individual logic cell individual cell individual embedded cell logic array block (LAB), embedded array block (EAB), row, column
When assign logic function general location such LAB, EAB, row, column, Compiler choose best logic cell embedded cell within LAB, row, column implement logic. File (.log) ASCII text file (with extension .log) created MAX+PLUS Simulator. File records commands, buttons, onscreen options that used during interactive simulation session. logic function Design Entity primitive, megafunction, macrofunction, state machine, which represented either name symbol design file. Logic Array Block (LAB) physically grouped logic resources Altera device. consists logic cell array and, some device families, expander product term array. signal that available logic cell available entire LAB. Classic devices, logic shares global Clock signal. global dedicated input bus. EP1810 device, synonymous with quadrant.)
Altera Corporation
Glossary
Glossary
MAX+PLUS Getting Started
column number LAB. Classic, 5000, 7000 devices, logic cells have numbers format LC<number>, where <number> consist both digits letters. FLEX 10K, FLEX 8000, 9000 devices have specialized logic cells, called cells, periphery device. logic cell Turbo Turbo Bit. logic element logic cell. logic level input output logic levels nodes groups defined with following characters: Character: Logic Level:
variety logic options available. Logic option assignments applied individual logic functions; group logic option assignments, called logic synthesis style, applied individual logic functions. default logic synthesis style also applied project whole. logic cell Turbo logic option also turned device-by-device basis. Logic options also assigned parameters megafunction macrofunction. Some logic options available with standard synthesis; logic options available with multi-level synthesis. logic option ignored does apply current device family.
Logic (GND) Logic high (VCC) Care (not permitted initialization) High impedance input pin); e.g., used part bidirectional when part driving Used groups interpreted binary, decimal, hexadecimal, octal values according current radix. most significant first; least significant last. logic option option that controls logic synthesis process more logic functions.
logic synthesis style combination logic synthesis option settings that saved under single name. logic synthesis style individually tailored different device families, that logic synthesis option settings vary according architecture target device family. global project logic synthesis style your project fully defined, i.e., style specified with Global Project Logic Synthesis command (Assign menu) uses setting logic option, MAX+PLUS Compiler will setting that logic option from predefined, Altera-provided settings
Altera Corporation
Glossary
Normal style. view settings predefined style, open Define Synthesis Style dialog box, select style Style box, choose Default button. logical operator operator that performs logic operation nodes, groups, numbers. AHDL logical operators (!), (&), NAND (!&), (#), (!#), ($), XNOR (!$). VHDL logical operators AND, NAND, NOR, XOR, NOT. Verilog logical operators (&&) (||). Library Parameterized Modules. least significant bit.
created during installation. AHDL Include Files (.inc) these macrofunctions located \maxplus2\max2inc directory; VHDL Component Declarations macrofunctions supported VHDL provided maxplus2 package altera library, which located subdirectory \maxplus2\vhdlnn directory, where UNIX workstation, maxplus2 directory subdirectory /usr directory. view file that contains logic macrofunction, select macrofunction symbol Graphic Editor macrofunction name Text Editor choose Hierarchy Down (File menu). 5000 Altera device family based first generation Multiple Array MatriX architecture. This EPROM-based device family includes EPM5032, EPM5064, EPM5128, EPM5128A, EPM5130, EPM5192 devices. 7000, 7000E, 7000S Altera device family based second generation Multiple Array MatriX architecture that includes 7000, 7000E, 7000S devices. These EEPROM-based devices include EPM7032, EPM7032V, EPM7064, EPM7064S, EPM7096, EPM7128E, EPM7128S, EPM7160E, EPM7192E, EPM7192S, EPM7256E, EMP7256S devices. 7000S 7000E devices enhanced versions 7000 devices function-, pin-, programmingfile-compatible with 7000 devices. 7000E 7000S devices differ from 7000 devices that they offer pin- logic-driven Output Enable signals, fast input setup times
Glossary
Glossary
macrocell logic cell. macrofunction high-level building block that used together with gate flipflop primitives and/or megafunctions MAX+PLUS design files. general, Altera recommends using megafunctions preference equivalent macrofunctions projects. Megafunctions easier scale different sizes offer more efficient logic synthesis device implementation. Altera provides library over oldstyle macrofunctions \maxplus2\ max2lib directory subdirectories
Altera Corporation
MAX+PLUS Getting Started
logic cells, multiple global Clocks with optional inversion. 7000S devices also offer additional capability insystem programming JTAG boundaryscan test circuitry. Altera strongly recommends using 7000S 7000E devices rather than equivalent 7000 devices designs. 9000 Altera device family based third generation Multiple Array MatriX architecture. These EEPROM-based devices include EPM9560, EPM9560A, EPM9480, EPM9400, EPM9320, EPM9320A devices. 9000A devices enhanced versions 9000 devices, function-, pin-, programming-file-compatible with 9000 devices. 9000A devices differ from 9000 devices that they offer additional bits user code. 9000 devices with speed grade suffix contain fixed programming algorithms, therefore programmed with Serial Vector Format Files. MAX+PLUS (DOS) DOS-based Multiple Array MatriX Programmable Logic User System. MAX+PLUS computer programs hardware support products designing implementing custom logic circuits with Altera Classic 5000 devices. Graphic Design Files (.gdf) created MAX+PLUS automatically converted processed with MAX+PLUS Compiler; AHDL Text Design Files (.tdf) compiled directly. MAX+PLUS Programmer program Classic 5000
devices with JEDEC Files (.jed) Programmer Object Files (.pof) created MAX+PLUS. MAX+PLUS longer offered Altera. designs should created with MAX+PLUS MAX+PLUS Message File (.mmf) binary file (with extension .mmf) created MAX+PLUS that contains messages issued MAX+PLUS application command that runs background process, e.g., Compiler Programmer. This file used display messages Message Processor locate messages design ancillary files. maxplus2.idx file text file, created automatically when save file, that maps filenames with more than eight characters 8-character filenames. MAX+PLUS creates maxplus2.idx file each directory where save file that contains filenames with more than eight characters. file automatically updated each time save file with long filename. maxplus2.ini file text file, created during installation, that contains parameters that affect MAX+PLUS applications operate. This file continuously records options that session, that they automatically next session. MegaCore OpenCore megafunctions MegaCore OpenCore megafunctions pre-verified design files complex system-level functions that purchased from Altera. These pre-tested megafunctions optimized
Altera Corporation
Glossary
FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 device architectures. Altera MegaCore megafunctions consist several different design files. post-synthesis AHDL design file used design implementation (i.e., fitting) target Altera device. addition, VHDL Verilog functional simulation models supplied design debugging with standard simulation tools. OpenCore megafunctions MegaCore functions that evaluate before purchasing full support. purchase full support, generate programming files EDIF, VHDL, Verilog output files postcompilation simulation with other tools. Altera provides library megafunctions, including OpenCore megafunctions, \maxplus2\max2lib\mega_lpm directory. UNIX workstation, maxplus2 directory subdirectory /usr directory). VHDL Component Declarations megafunctions supported VHDL provided megacore package altera library, which located the\maxplus2\vhdlnn directory, where your authorization code MegaCore megafunction includes permission view source design file, view file selecting megafunction symbol Graphic Editor megafunction name Text Editor choosing Hierarchy Down (File menu). megafunction complex high-level building block that used together with gate flipflop primitives and/or
old-style macrofunctions MAX+PLUS design files. Altera provides library megafunctions, including functions from Library Parameterized Modules (LPM) version 2.1.0, \maxplus2\max2lib\ mega_lpm directory created during installation. AHDL Include Files (.inc) these megafunctions also located \maxplus2\max2lib\mega_lpm directory. VHDL Component Declarations functions other megafunctions provided lpm_components package library, megacore package altera library, respectively. Both these libraries located subdirectories \maxplus2\vhdlnn directory, where UNIX workstation, Glossary maxplus2 directory subdirectory /usr directory.) Glossary view file that contains logic megafunction, select megafunction symbol Graphic Editor megafunction name Text Editor choose Hierarchy Down (File menu). memory memory word memory individual memory address memory (i.e., ROM) block. memory word group memory bits block. example, content5_[4.0] memory word defines byte memory which individual memory bits content5_4, content5_3, content5_2, content5_1, content5_0. Memory Initialization File (.mif) ASCII file (with extension .mif) that specifies
Altera Corporation
MAX+PLUS Getting Started
initial content memory block (RAM ROM), i.e., initial values each address. This file used during project compilation and/or simulation. Memory Initialization Output File (.mio) ASCII file (with extension .mio) that generated when Compiler creates Text Design Export File (.tdo) project. File that implements always File each memory segment. File specifies memory addresses values used initialize segment, similar information Memory Initialization File (.mif). rename File with File that been saved Text Design File (.tdf). memory segment segment physical implementation memory (i.e., ROM) device. memory segment contains sequence memory bits corresponding address range. FLEX devices, memory segment consists that portion bit-slice memory which implemented single embedded cell. Each embedded cell implements bits memory. Multiple memory segments needed create single memory block. Message Text File (.mtf) ASCII file (with extension .mtf) that contains text messages shown Message Processor window. Memory Initialization File.
most significant (MSB) binary number that contributes greatest quantity value that number, first member group name. example, named a[31.0] a[31]. most significant bit. Message Text File.
multi-device FLEX chain series devices through which configuration data passed from device device using sequential Passive Serial configuration scheme. MAX+PLUS Programmer configure multiple FLEX 6000, FLEX 8000, FLEX devices multi-device FLEX chain. multi-device JTAG chain series devices through which programming and/ configuration data passed from device device Joint Test Action Group (JTAG) Boundary-Scan Test (BST) circuitry. MAX+PLUS Programmer program configure multiple 7000S, 9000, FLEX devices multi-device JTAG chain. JTAG chain contain combination Altera non-Altera devices that comply with IEEE 1149.1 JTAG specification, including some FLEX 8000 devices. MAX+PLUS also generate Files (.jam) Serial Vector Format Files (.svf) that support programming more 7000S 9000 devices JTAG chain. files used Automated Test Equipment (ATE)-type programming environments; Files
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MAX+PLUS Message File.
Glossary
embedded processor-type programming environments. multi-level synthesis Logic synthesis that takes advantage available logic options, including options listed Define Synthesis Style Advanced Options dialog boxes (Assign menu). This type logic synthesis handle projects with extremely complex logic, without requiring user intervention achieve fit. Multi-level synthesis selected with Global Project Logic Synthesis dialog (Assign menu). This type synthesis available only 5000, 7000, 9000, FLEX 6000, FLEX 8000, FLEX device families; only type synthesis available FLEX 6000, FLEX 8000, FLEX projects.
Item: single-range group (bus) name
Name Character Exception:
name characters characters slash (/), dash (-), underscore legal MAX+PLUS breakpoint, chip, clique, file, group (bus), node, parameter, pin, pinstub, probe, logic synthesis style, quoted unquoted symbolic names, with exceptions listed below. Case significant only Verilog files. Item: filename Name Character Exception: slash permitted. Case significant UNIX workstations.
slash permitted; identifier cannot with digit. name followed range numbers arithmetic expressions brackets. start range separated periods. example, group a[3.1] consists nodes Graphic Editor files only, sequential names also include series single-range names. example, a[8.0],d[6.4]. dual-range Same single-range group (bus) group names, with name ranges numbers arithmetic expressions brackets. example, a[6.3][4.0]. sequential name consists group (bus) series comma-separated name node names enclosed parentheses. example, group consists nodes Graphic Editor files, parentheses used. dash permitted. unquoted Names cannot consist symbolic name (AHDL) entirely digits. AHDL keywords cannot used. Verilog slash dash identifiers permitted. Names cannot begin with digit. Case significant. Verilog keywords cannot used.
Glossary
Glossary
Altera Corporation
MAX+PLUS Getting Started
Item:
Name Character Exception:
VHDL names slash dash permitted. name must start with letter, cannot with underscore (_), cannot contain underscores row. VHDL keywords cannot used. names Names that contain slash (/), dash (-), vertical (|), colon (:), and/or period characters must enclosed double quotation marks ("). number symbol number. network group interconnected node and/or lines, including nodes buses that connected name only. node node represents wire carrying signal that travels between different logical components design file. Verilog HDL, nodes called Graphic Editor files, nodes represented lines; text files, they symbolic names; Waveform Editor files, they waveforms. Node Database File (.ndb) file that contains database project node names, which supports resource probe assignment edits with Assign menu commands Floorplan Editor. Compiler Netlist Extractor Database Builder modules Compiler generate Node Database File project during project processing.
turn Preserve Node Name Synonyms command (Processing menu) before compilation, this file will contain possible forms project node names.
accidentally delete this file, must recompile project before most Assign menu commands Floorplan Editor functions. addition, only pins visible Floorplan Editor Node Database File created with Project Save Check command (File menu): full compilation required make buried nodes visible Floorplan Editor. node name name given signal design file. node name contain following name characters: slash (/), dash (-), underscore (_). Hierarchical node names contain characters, including vertical (|), colon (:), period (.). Case significant. Some restrictions apply names VHDL Design Files (.vhd), Verilog Design Files (.v), unquoted port symbolic names AHDL Text Design Files (.tdf). node type type logic that drives node group Waveform Design File (.wdf) Vector File (.vec). Four logic types defined: Type: INPUT Meaning: Node group driven input pin.
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Glossary
Type: COMB
Meaning: Node group combinatorial logic, e.g., gate. Node group register (implemented with logic cell device). Node state machine.
first object selected clicking Button remove objects selection pressing Shift while clicking them with Button Graphic Editor, object-by-object selection used select graphics and/or text blocks; Waveform Editor, select nodes groups; Floorplan Editor, select pins, nodes, logic cells, assignment bins; Hierarchy Display, select file icons. Graphic Editor, multiple objects rectangular area selected added existing selection pressing Shift while dragging Button octal base number system (radix). Octal digits though Octal numbers indicated with following notation:
Language
AHDL
MACH
Normal logic synthesis style Alteraprovided style that directs Logic Synthesizer optimize your project minimum silicon resource usage. Normal style attempts device resources efficiently possible, without adding excessive timing delays. display settings this style, select style Define Synthesis Style dialog box, which available through Logic Options Global Project Logic Synthesis dialog boxes (Assign menu). global project logic synthesis style your project fully defined, i.e., style specified with Global Project Logic Synthesis command (Assign menu) uses setting logic option, MAX+PLUS Compiler will setting that logic option from predefined, Altera-provided settings Normal style. view settings predefined style, open Define Synthesis Style dialog box, select style Style box, choose Default button.
Glossary
Glossary
Notation
O"<series digits Q"<series digits 8#<series digits
VHDL Verilog
'o<series digits
Examples: Q"4671223" (AHDL) 8#4671223# (VHDL) 'o4671223 (Verilog HDL) one-hot encoding type binary coding which only value example, four legal values 0001, 0010, 0100, 1000 together
object-by-object selection process selecting multiple non-contiguous objects.
Altera Corporation
MAX+PLUS Getting Started
comprise code sample because each these four values single manually implement one-hot encoding. addition, Global Project Logic Synthesis command (Assign menu) includes One-Hot State Machine Encoding option allow Compiler automatically implement one-hot encoding entire project. Altera strongly recommends using One-Hot State Machine Encoding option rather than manual one-hot encoding. This option available both multi-level standard synthesis. ignored does apply current device family. OrCAD Library File (.lib) binary file (with extension .lib) containing information that describes symbols displayed OrCAD Schematic Files (.sch). MAX+PLUS Graphic Editor uses OrCAD-generated OrCAD Library File import OrCAD Schematic File. OrCAD Library File each OrCAD Schematic File should contain libraries OrCAD symbols used schematic. This OrCAD Library File must also copied same directory OrCAD Schematic File. OrCAD Schematic File (.sch) schematic design file (with extension .sch) created with OrCAD Draft schematic editor. open edit OrCAD Schematic File MAX+PLUS save both Graphic Design File (.gdf) OrCAD Schematic File (.sch). OrCAD Schematic File also compiled directly MAX+PLUS Compiler.
oscillation unstable logic level signal. When Simulator timing linked simulation mode, specify time period that constitutes oscillation monitor project signals that stabilize within defined period. When Simulator functional simulation mode, monitor project nil-period oscillation only. Output Enable high logic level Output Enable signal enables output. 7000 devices (not including 7000E devices), signal from active-low global Output Enable must inverted connected activehigh Output Enable input primitive. other device families, either active-high active-low polarity used. 9000 devices, Fitter automatically inserts additional LCELL primitives provide correct polarity non-global Output Enable Output Enable signal driven logic cell.
parameter parameterized parameter attribute megafunction macrofunction that determines logic created used implement function, i.e., characteristic that determines size, behavior, silicon implementation function. parameter information used determine actual primitives other subdesigns needed implement logic function. parameterized function function whose behavior controlled more parameters. Some logic functions,
Altera Corporation
Glossary
such functions Library Parameterized Modules (LPM), inherently parameterized require parameter values assigned. Parameters assigned individual instance megafunction MAX+PLUS control size implementation. Some parameters also applied old-style macrofunctions determine their style implementation. MAX+PLUS also allows assign global, project-wide default values parameters. parameterized module logic function that uses parameters achieve scalability, adaptability, efficient silicon implementation. MAX+PLUS supports variety parameterized modules (also called including functions belonging Library Parameterized Modules (LPM). functions provide architectureindependent design entry MAX+PLUS II-supported devices. MAX+PLUS Compiler includes built-in compilation support functions used schematic, AHDL, VHDL, Verilog HDL, EDIF input files. actual input Altera device. Graphic Editor files, represented INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, BIDIRC symbol. Text Design File (.tdf), represented INPUT, OUTPUT, BIDIR port. VHDL Design File (.vhd), represented OUT, INOUT port. Verilog Design File (.v), represented input, output, inout port. Waveform Design File (.wdf),
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represented node with input, output, bidirectional type input, registered, combinatorial node type. assign logic function specific number. also assign logic function column ensure that function implemented particular column. number number used assign input output signal design file, which corresponds number actual device. Both letters digits used specify numbers PGA-package devices. pinstub Graphic Symbol Editors, pinstub location boundary symbol represented Symbol File (.sym) name that represents input output primitive megafunction macrofunction design file that symbol represents. line (node) drawn schematic must connect this pinstub recognized Compiler connection between logic current file logic primitive, megafunction, macrofunction. specify whether optional pinstub when edit symbol instance Graphic Editor file. Pinstubs Graphic Editor files synonymous with ports AHDL Function Prototypes VHDL Component Declarations. They also synonymous with ports listed Subdesign Sections lower-level Text Design Files (.tdf); Entity Declarations lower-level VHDL Design Files (.vhd); Module
Glossary
Glossary
MAX+PLUS Getting Started
Declarations, Module Instantiations, Gate Instantiations Verilog Design Files (.v). pinstub name symbolic name that identifies input output logic function. Symbol Editor, pinstub name appears both inside outside symbol. This pinstub name abbreviation alias pinstub name, which represents full name original input, output, bidirectional mega- macrofunction design file primitive Function Prototype. specify whether display pinstub name Graphic Editor file when create pinstub Symbol Editor. non-use particular pinstub (and hence visibility) customized when edit symbol instance Graphic Editor with Edit Ports/Parameters (Symbol menu). Pinstubs Graphic Editor files synonymous with ports AHDL Function Prototypes VHDL Component Declarations. They also listed Subdesign Sections lower-level Text Design Files (.tdf); Entity Declarations lower-level VHDL Design Files (.vhd); Module Declarations, Module Instantiations, Gate Instantiations Verilog Design Files (.v). Programmer File. PLS-ES PC-based MAX+PLUS development system, which automatically provided site license when purchase PC-based MAX+PLUS development system.
PLS-ES development systems include following MAX+PLUS applications features:
Hierarchy Display Graphic, Symbol, Text Editors Compilation support Classic, 5000, 7000/7000E/7000S, EPF8282, EPF8452, EPM9320, EPF10K10 devices EDIF Interfaces (input output) Verilog VHDL output Timing Analyzer Message Processor Programmer Programmer Object File.
port symbolic name that represents input output primitive design file. AHDL, port name Subdesign Section represents input output current file. This port name also appears Function Prototype function. When instance primitive lowerlevel design file implemented with Instance Declaration in-line reference, ports used connect other functions TDF. After instance declared, inputs outputs expressed names format <instance name>.<port name> Logic Section. When in-line reference used, either named port association positional port association used connect ports other functions TDF. VHDL, port name Entity Declaration represents input output current file. When instance primitive lower-level design file implemented with Component
Altera Corporation
Glossary
Instantiation, ports connected signals with Port Aspects. Verilog HDL, port Module Declaration represents input output current file. When instance lower-level design file implemented with Module Instantiation, ports connected order name Module Declaration ports module being instantiated. Similarly, when primitive implemented with Module Instantiation, ports used connect order other functions file. Verilog gate primitives also contain ports (called when gate primitive implemented with Gate Instantiation, terminals connected order terminals gate being instantiated. port name AHDL Subdesign Section, VHDL Entity Declaration, Verilog Module Gate Declaration synonymous with name Graphic Design File (.gdf) Waveform Design File (.wdf). port name that appended instance name synonymous with full pinstub name instance symbol Graphic Editor file. Preset input signal that asynchronously sets output register logic high (1), regardless other inputs. primitive basic functional blocks used design circuits with MAX+PLUS software. Primitives used Graphic Design Files (.gdf), AHDL Text Design Files (.tdf), VHDL Design Files (.vhd), Verilog Design Files (.v).
Graphic Editor primitives include buffers, flipflops, latch, input output primitives, logic primitives. Primitive symbols Graphic Editor files provided \maxplus2\max2lib\ prim directory created during installation. AHDL, VHDL, Verilog primitives, which include buffers, flipflops, latch, subset primitive symbols used Graphic Editor files. Other functions represented logical operators, ports, other constructs. Function Prototypes AHDL primitives built into MAX+PLUS software; Component Declarations VHDL primitives provided maxplus2 package \maxplus2\ max2vhdlnn\altera directory, where UNIX workstation, maxplus2 directory subdirectory /usr directory. primitive array single primitive that connected more buses order represent multiple primitives. probe unique name assigned node, e.g., input output primitive, megafunction, macrofunction which used instead full hierarchical node name throughout MAX+PLUS probe name thus provides short name identify node. product term more factors Boolean expression combined with operator constitute product term, where means
Glossary
Glossary
Altera Corporation
MAX+PLUS Getting Started
Programmer File (.plf) ASCII file (with extension .plf) generated Programmer that records programming session commands messages. Programmer Object File (.pof) binary file (with extension .pof) generated Assembler module. This file contains data used MAX+PLUS Programmer program Altera device. MAX+PLUS Programmer optionally save functional test vectors POF. programming file file containing data programming Altera devices. Both MAX+PLUS Compiler Programmer generate programming files. following programming file formats available MAX+PLUS
save data read from examined device JEDEC File format. project project consists files that associated with particular design, including subdesign files related ancillary files created user MAX+PLUS software. project name same name top-level design file project, without filename extension. MAX+PLUS performs compilation, simulation, timing analysis, programming only project time. propagation delay time required signal transition travel between pins and/or nodes device.
FLEX Chain File (.fcf) Hexadecimal (Intel-Format) File (.hex) File (.jam) JEDEC File (.jed) JTAG Chain File (.jcf) Programmer Object File (.pof) Binary File (.rbf) Serial Bitstream File (.sbf) Serial Vector Format File (.svf) SRAM Object File (.sof) Tabular Text File (.ttf) radix number base. Group logic level numerical values entered displayed binary, decimal, hexadecimal, octal radix MAX+PLUS Random-access memory. implement with Embedded Array Blocks (EABs) FLEX device family, with arrays flipflops latches other device families. range sequence numbers arithmetic expressions that define width group (bus). range enclosed brackets; most significant (MSB) range shown first; least significant (LSB) shown last. start range separated periods Graphic Editor AHDL, colon Verilog HDL.
POFs, SOFs, JEDEC Files, JCFs, FCFs used program configure devices with MAX+PLUS Programmer; test vectors functional testing saved POFs JEDEC Files. other file formats used program configure devices other environments. JEDEC Files generated A+PLUS PLDshell Plus software also used program Classic devices. Programmer
Altera Corporation
Glossary
Example: group a[2.0] consists nodes Binary File (.rbf) binary file (with extension .rbf) containing configuration data FLEX 6000, FLEX 8000, FLEX devices. This file binary equivalent Tabular Text File (.ttf). create RBFs that support Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) configuration schemes MAX+PLUS register flipflop. register packing feature logic cells 9000 FLEX devices that allows logic combinatorial logic function register with single data implemented same logic cell. manually implement register packing assigning logic functions same logic cell. addition, Global Project Logic Synthesis command (Assign menu) includes Automatic Register Packing option allow Compiler automatically implement register packing appropriate pairs logic functions. Altera strongly recommends using Automatic Register Packing option rather than manual logic cell assignments implement register packing. This option available both multi-level standard synthesis. ignored does apply current device family. registered feedback Feedback that output flipflop latch.
Altera Corporation
registered output output flipflop latch, which feed output device. registered performance minimum required Clock period maximum Clock frequency circuit, which calculated MAX+PLUS Timing Analyzer. Clock period equals maximum delay from output flipflop Clock Enable input flipflop, plus internal setup time propagation delay through flipflop. Clock skew calculations increase Clock period. Clock frequency equals (1/Clock period). Timing Analyzer does calculate registered performance signal path that passes through primary (data) input flipflop. Report File (.rpt) ASCII text file (with extension .rpt), generated Fitter module, that shows device resources used project. module preceding Partitioner generates error, this file generated. Partitioner generates error, Report File generated most cases. Reset active-high input signal that asynchronously resets output register logic state machine initial state, regardless other inputs. resource resource portion Altera device that performs specific, userdefined task (e.g., pins, logic cells).
Glossary
Glossary
MAX+PLUS Getting Started
resource assignment assignment logic function project particular pin, logic cell, cell, embedded cell, logic array block (LAB), embedded array block (EAB), row, column, chip. This type resource assignment assigns logic function physical resource device. resource assignment also consist clique, logic option, connected pin, timing requirement, local routing assignment particular logic function project. This type resource assignment assigns compilation resource logic function. horizontal line LABs connected FastTrack Interconnect path FLEX 6000, FLEX 8000, FLEX 10K, 9000 device. RS-232 port port.
segment
memory segment.
Serial Bitstream File (.sbf) ASCII file (with extension .sbf) that contains data configuring FLEX 6000, FLEX 8000, FLEX device with BitBlaster from system prompt. This file generated with Combine Programming Files command (File menu) Compiler Simulator. Serial Vector Format File (.svf) ASCII file (with extension .svf) that stores programming data programming more fixed algorithm devices Automated Test Equipment (ATE)-type programming environments. 7000S 9000 devices programmed with Files. JTAG chain contain other device that complies with IEEE 1149.1 JTAG specification, including FLEX 10K, FLEX 6000, some FLEX 8000 devices. create Files with Create File command (File menu) Programmer Compiler. setup time flipflop, setup time minimum time interval between application signal input that feeds data Clock Enable input low-to-high transition input that feeds Clock input flipflop Latch Enable input latch. latch, setup time minimum time interval between application signal input that feeds data input latch low-to-high transition input that feeds Latch Enable input latch. (Setup hold time analysis latches available only 5000 devices. other device families, latches implemented using combinatorial logic with feedback.)
Altera Corporation
Simulator Channel File.
Output File Standard Delay Format Output File. secondary input Clock, Preset, synchronous asynchronous Reset (Clear), synchronous asynchronous Load inputs register state machine design file. Security that prevents EPROM- EEPROM-based Altera device from being interrogated. This also prevents EPROM-based Altera devices from being inadvertently reprogrammed. Security turned each device project, entire project.
Glossary
asynchronous block, setup time minimum time interval between application signal input that feeds data address inputs low-to-high high-to-low transition input that feeds Write Enable input block. Internal setup times flipflops, latches, asynchronous RAM, which user-defined, similarly constrain signals that generated within device. shared local interconnect Dedicated connection paths FLEX 6000 devices that allow signals travel quickly between logic cells same adjacent LABs, between logic cells periphery device pins. Shared local interconnect fastest interconnect available FLEX 6000 devices. Simulator Initialization File.
group, memory values, including initialized values entered with Initialize Nodes/Groups Initialize Memory commands (Initialize menu) Command File (.cmd) GROUP INIT NODE INIT commands. allows reuse previously saved node group values. Simulator Netlist File (.snf) binary file (with extension .snf) that contains data functional simulation, timing simulation timing analysis, linked multi-device simulation. Three optional Compiler modules create different types SNFs that contain information required different simulation modes and/or timing analysis:
Simulator Channel File (.scf) graphical waveform file (with extension .scf) that both input output Simulator. This file contains waveform representation vector values input nodes that drive simulation, well buried output nodes simulated. Waveforms file represent high (1), (0), high-impedance (Z), undefined logic levels. created viewed Waveform Editor; Simulator also automatically creates updates during simulation. also used provide vector inputs functional testing Programmer. Simulator Initialization File (.sif) file (with extension .sif) that saves node,
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Timing Extractor generates Glossary timing that contains data required timing simulation full timing analysis. Functional Extractor generates functional that contains data required functional simulation. Linked Extractor generates linked that combines timing and/ functional data from timing, functional, and/or linked SNFs other previously compiled projects. combined SNFs timing SNFs, linked also used full timing analysis. Glossary
Only type exist particular time same project. single-range group bus) name name group bus) nodes, consisting identifier with name characters, followed range numbers arithmetic expressions brackets. start range
MAX+PLUS Getting Started
separated periods. Each number sequence represents individual node identifier cannot with digit. Example: group a[4.1] consists nodes Graphic Editor files, sequential name also include more singlerange names series. first node series first node first range most significant bus; last node series last node last range least significant bit. Example: a[8.0], dout[6.4] Simulator Netlist File. SRAM Object File.
simulators that simulation libraries that compliant with VITAL version 2.2b version (VITAL 95); backannotation simulation Verilog simulators; timing analysis resynthesis with EDIF simulation synthesis tools.The Standard Delay Format (SDF) industry-standard format. MAX+PLUS EDIF, VHDL, Verilog Netlist Writer modules MAX+PLUS Compiler generate Output Files version format. standard synthesis Logic synthesis that includes following logic options:
source node node that tagged (designated) source signal purpose timing analysis. source node tagged with Timing Analysis Source command (Utilities menu), node that output primitive, megafunction, macrofunction, pin. spike glitch. SRAM Object File (.sof) binary file (with extension .sof), generated Assembler module, that contains data configuring Altera FLEX 6000, FLEX 8000, FLEX device. Standard Delay Format Output File (.sdo) optional output file (with extension .sdo) containing timing delay information that allows perform backannotation simulation with VHDL
Fast Global Signal Hierarchical Synthesis Insert Additional Logic Cell Minimization (Full Partial) Gate Push-Back Parallel Expanders Slow Slew Rate SOFT Buffer Insertion Turbo (including logic cell Turbo Bit) AHDL Operators Synthesis
Standard synthesis includes only these logic options; other options listed Define Synthesis Style Advanced Options dialog boxes (Assign menu) available only multi-level synthesis. This type logic synthesis available only Classic, 5000, 7000, 9000 device families. state output flipflop used state machine store value state machine.
Altera Corporation
Glossary
state machine sequential circuit that advances through number states. state machine defined Waveform Design File (.wdf), State Machine File (.smf), Vector File (.vec), VHDL Design File (.vhd), Verilog Design File (.v) State Machine Declaration AHDL Text Design File (.tdf). sub-project super-project. subdesign lower-level design file MAX+PLUS project, i.e., Alteraprovided user-created megafunction macrofunction. Altera provides libraries mega- macrofunctions mega_lpm subdirectories \maxplus2\max2lib directory. AHDL Include Files (.inc) these functions located \maxplus2\max2lib\mega_lpm \maxplus2\max2inc directories, respectively. Component Declarations functions supported VHDL provided maxplus2 megacore packages altera library lpm_components package library. Both these libraries located \maxplus2\vhdlnn directory, where Megacore megafunctions must purchased from Altera before them your design(s). UNIX workstation, maxplus2 directory subdirectory /usr directory.) subdesign name entity name name that represents name subdesign. AHDL, subdesign name quoted unquoted symbolic name that must same Text Design File (.tdf) filename. VHDL, entity name identifier.
Unquoted subdesign name (AHDL): Maximum characters length: Legal a-z, A-Z, 0-9, characters: underscore unquoted subdesign name cannot reserved AHDL identifier keyword. Quoted subdesign name (AHDL): Maximum characters length: Legal a-z, A-Z, 0-9, dash (-), characters: underscore Identifier (VHDL): Maximum characters length: Legal a-z, A-Z, 0-9, underscore characters: identifier cannot begin with digit underscore, cannot with underscore, cannot have underscores succession. cannot keyword. Identifier (Verilog HDL): Maximum characters length: Legal a-z, A-Z, 0-9, characters: underscore identifier cannot begin with digit. Identifiers case-sensitive. Verilog keywords cannot used.
Glossary
Glossary
Altera Corporation
MAX+PLUS Getting Started
UNIX workstation environment, filenames hence subdesign names case-sensitive. sum-of-products Boolean expression said sum-of-products form consists product terms combined with operator. super-project sub-project superproject consists top-level design file that contains symbols instances representing multiple, individual projects. sub-project individual project that serves part super-project. super-project sub-project higher-level super-project. File Serial Vector Format File.
numbers nodes when project compiled. Hierarchy Display window, name each lower-level design file appended with colon plus number AHDL,VHDL, Verilog mega- macrofunction instance name.
Table File (.tbl) ASCII file (with extension .tbl) that contains tabularformat list input vectors output logic levels current Vector File (.vec) Simulator Channel File (.scf). Table File generated Simulator Waveform Editor. Tabular Text File (.ttf) ASCII text file tabular format (with extension .ttf) containing configuration data FLEX 6000, FLEX 8000, FLEX devices. contains decimal equivalent Binary File (.rbf). MAX+PLUS Compiler automatically creates TTFs containing configuration data sequential Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) configuration schemes FLEX 8000 devices, configuration scheme FLEX devices, Passive Serial Asynchronous (PSA) configuration schemes FLEX 6000. After compilation, also create TTFs that support other configuration schemes FLEX 6000, FLEX 8000, FLEX devices. (Clock output delay) time required obtain valid output output that register after Clock signal transition input that
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Symbol File (.sym) graphic file (with extension .sym) created Symbol Editor Compiler Netlist Extractor module Compiler. This file represents design file (i.e., megafunction macrofunction) MAX+PLUS primitive with same name used Graphic Design Files (.gdf). When Linked Extractor module turned symbol Graphic Editor file represents Simulator Netlist File (.snf), rather than design file, during compilation. symbol number number number that uniquely identifies every node symbol design file. Graphic Editor, this number appears inside bottom left corner symbol reflects order which symbols entered Graphic Editor file. other types design files, Compiler assigns
MAX+PLUS Getting Started
clocks register. This time always represents external pin-to-pin delay. also timing assignment that specifies maximum acceptable Clock output delay. MAX+PLUS specify required entire project and/or input (INPUT INPUTC), output (OUTPUT OUTPUTC), buffer (i.e., BIDIR BIDIRC output function) pin. Text Design File. ternary operator operator that selects between expressions within AHDL arithmetic expression. ternary operator used following format: <expn <expn <expn first expression non-zero (true), second expression evaluated given result ternary expression. Otherwise, third expression evaluated given result ternary expression. Text Design Export File (.tdx) ASCII text file (with extension .tdx) AHDL that optionally generated when compile Xilinx Netlist Format File (.xnf). contains same logic File. Text Design Export File saved Text Design File (.tdf) used replace corresponding File hierarchy project. Text Design File (.tdf) ASCII text file (with extension .tdf) written AHDL. Text Design Export Files (.tdx) Text Design Output Files (.tdo) saved TDFs compiled with MAX+PLUS
Text Design Output File (.tdo) ASCII text file (with extension .tdo), generated MAX+PLUS Compiler, that contains AHDL equivalent fully optimized logic device project. Compiler generates File, well Assignment Configuration Output File (.aco) when compile project turn Generate AHDL File command (Processing menu). save File Text Design File (.tdf) recompile (You must also save Assignment Configuration Output File (.aco) Assignment Configuration File (.acf) wish preserve assignments device.) Files facilitate back-annotation preserve existing logic synthesis project. time unit unit specifying time MAX+PLUS Five time units available: Time Unit: Abbreviation for: nanosecond millisecond microsecond second megahertz
time value always followed immediately (i.e., with space between) time unit. enter time unit, either assumed default, depending appropriate context. Timing Analyzer Output File (.tao) ASCII text file (with extension .tao) that used save results current
Altera Corporation
MAX+PLUS Getting Started
timing analysis displayed MAX+PLUS Timing Analyzer. timing assignment assignment that specifies desired speed performance more logic functions. tPD, tSU, tCO, fMAX timing assignments, well available. assign timing individual logic functions specify default timing project whole. Timing assignments influence project compilation only FLEX 6000, FLEX 8000, FLEX device families. timing type timing assignment that cuts connections between timing path individual node other nodes project, indicate that Compiler should consider delay along this path when attempts meet desired speed performance while processing project. (input non-registered output delay) time required signal from input propagate through combinatorial logic appear external output pin. also timing assignment that specifies maximum acceptable input non-registered output delay. MAX+PLUS specify required entire project and/or input (INPUT INPUTC), output (OUTPUT OUTPUTC), buffer (i.e., BIDIR BIDIRC output function) pin. tri-state buffer buffer with input, output, controlling Output Enable signal. Output Enable input high, output signal equals input.
Output Enable input low, output signal state high impedance. tri-state buffer implemented with primitive. Tri-state buses implemented tying multiple nodes together Graphic Editor file with TRI_STATE_NODE variable AHDL file. (Clock setup time) length time which data that feeds register data Enable input(s) must present input before Clock signal that clocks register asserted Clock pin. also timing assignment that specifies maximum acceptable Clock setup time. MAX+PLUS specify required entire project and/or input (INPUT INPUTC) bidirectional (BIDIR BIDIRC input function). Tabular Text File.
Turbo logic cell Turbo control choosing speed power characteristics Altera device. Turbo logic option most effective when applied megafunctions, macrofunctions, pins. Turbo speed increases; off, power consumption decreases. Turbo turned design file Compiler. Turbo availability differs each device family
Altera Corporation
MAX+PLUS Getting Started
Altera Device Turbo Availability: Family: Classic Applies entire device (specified device option) available Applies individual logic cells within device (specified logic option) Applies individual logic cells within device (specified logic option) available available available
macrofunctions, Symbol Files (.sym), AHDL Include Files (.inc), precompiled, user-defined VHDL packages. Compiler automatically searches these user-specified libraries when compiles project. VHDL Netlist Settings command (Interfaces menu) specifies VHDL design libraries current project. specify which directories contain your other user libraries with User Libraries command (Options menu) MAX+PLUS application.
5000 7000
9000
FLEX 6000 FLEX 8000 FLEX
variable name that represents node. AHDL, variable also represent state machine instance primitive, megafunction, macrofunction declared Variable Section. VHDL, variables have single current value, declared used only processes subprograms. VHDL variable de
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