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MC145402
Advance Information
Serial 13-Bit Linear Codec (A/D D/A)
MC145402 13-bit linear monotonic digital-to-analog analog- to-digital converter implemented single silicon-gate CMOS Potential applications include analog interface Digital Signal Processor (DSP) applications, high speed modems, telephone systems, SONAR, Adaptive Differential Pulse Code Modulation (ADPCM) converters, echo cancellers, repeaters, voice synthesizers, music synthesizers. Signal-to-(Noise Plus Distortion) Ratio Typical On-Chip Precision Voltage Reference Serial Data Ports Two's Complement Coding Supply Operation Sample Rates from (Both D/A), 21.3 (A/D Only), (D/A Only) Input Sample Hold Provided On-Chip CMOS Inputs; Outputs Capable Driving LSTTL Loads Available 16-Pin Power Consumption: Typical, Power-Down
SUFFIX CERAMIC PACKAGE CASE
ORDERING INFORMATION
MC145402L Ceramic Package
ASSIGNMENT
Aout
BLOCK DIAGRAM
BANDGAP VOLTAGE REFERENCE
Aout
SAMPLE HOLD
CONVERTER
DATA SELECTOR
RECEIVE LATCH
RECEIVE SHIFT REGISTER
SAMPLE HOLD COMPARATOR/ SUCCESSIVE APPROXIMATION REGISTER TRANSMIT LATCH TRANSMIT SHIFT REGISTER
SEQUENCE CONTROLLER
This document contains information product. Specifications information herein subject change without notice.
Motorola, Inc. 1995
MC145402
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced VSS)
Rating Supply Voltage Voltage, Current Drain (Excluding VDD, VSS) Operating Temperature Range Storage Temperature Range Symbol Tstg Value Unit This device contains circuitry protect inputs against damage high static voltages electrical fields; however, advised that normal precautions taken avoid applications voltage higher than maximum rated voltages this high impedance circuit. proper operation recommended that Vout constrained range (Vin Vout) analog inputs/outputs (Vin Vout) digital inputs/outputs. Reliability operation enhanced unused digital inputs tied appropriate logic voltage level (e.g., either VDD) unused analog Inputs tied VAG.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Power Dissipation, Power Dissipation, Conversion Rate Full Cycle Short Cycle Short Cycle Pins 70°C fMSI 25°C 3.27 70°C 10.5 21.3 4096 Unit
Conversion Sequence Rate Data Rate Full Scale Analog Levels (Referenced
TDC,
DIGITAL ELECTRICAL CHARACTERISTICS (VDD 70°C)
Characteristic High Level Input Voltage Level Input Voltage Input Current Input Capacitance High Level Output Voltage Level Output Voltage Iout Iout Iout Iout Symbol Unit
MC145402
CODER DECODER PERFORMANCE (VDD
Coder (A/D) Characteristic Resolution Conversion Time Full Cycle Short Cycle Short Cycle 62.5 46.9 0.35 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 10,000 10,000 0.35 62.5 15.6 0.35
dBm0 1.60 Vrms 6.30 (600 70°C, kHz, 2.048 MHz, kHz) Decoder (D/A) 10,000 10,000 0.35 Unit Bits
Differential Nonlinearity Gain Error Offset Idle Channel Noise, Low-Pass Signal-to-Noise (Referenced 1.02 through fMSI/2 Low-Pass Filter)
dBm0
ANALOG ELECTRICAL CHARACTERISTICS (VDD
Characteristic Input Current Input Impedance Input Capacitance Output Voltage Range Power Supply Rejection Ratio (100 VSS, kHz) Crosstalk, Aout Referenced dBm0 1.02 Slew Rate Settling Time (Full Scale) Symbol Vout PSRR tsettle
dBm0 1.60 Vrms 6.30 (600 70°C, kHz, 2.048 MHz, kHz) 0.01 Unit V/µs
MC145402
SWITCHING CHARACTERISTICS
(VDD 70°C, Figure Characteristic Input Rise Time Input Fall Time Output Rise Time Output Fall Time Pulse Width High Pulse Width Pulse Width Clock Frequency Clock Frequency Clock Frequency Rising Edge Data Valid During High Rising Edge Data Valid During High Rising Edge Low-Impedance Propagation Delay Falling Edge High-Impedance Propagation Delay Rising Edge Falling Edge Setup Time Falling Edge Last Falling Edge Prior Rising Edge Falling Edge Setup Time Last Rising Edge (Prior MSI) Rising Edge Last Rising Edge (Prior MSI) First Rising Edge First Falling Edge Last Rising Edge Prior Rising Edge Falling Edge Setup Time Valid Falling Edge Setup Time Hold Time from Falling Edge RCE, RDC, TDC, TDE, CCI, RCE, RDC, TDC, TDE, CCI, RDC, MSI, CCI, TDC, TDE, MSI, TDC, RCE, Symbol fMSI fCCI tsu1 tsu2 tsu3 tsu4 tsu5 tsu6 tsu6' tsu7 tsu8 tsu9 tsu10 fMSI Unit
MC145402
tsu6 tsu6 tsu1 tsu4 LAST tsu5 LAST tsu2
tsu7
tsu8 tsu10 tsu9 tsu3 LAST CLOCK
Figure Timing Diagram
MC145402
DESCRIPTIONS
Positive Supply (Pin most positive power supply, typically split power supply configurations, single supply systems. Negative Supply (Pin most negative power supply, typically split power supply configurations, single supply systems. Analog Ground (Pin This analog signal reference point. This normally tied split supply operation VDD/2 single supply systems. Digital Ground (Pin This ground reference digital input output pins. CMOS compatible logic signals swing from where established anywhere from 4.75 VSS. Aout Analog Output (Pin This output decoder's sample hold circuit 100% duty cycle analog output last digital word received decoded decoder. Aout updated approximately after rising edge last prior (see Figure Aout capable driving load. Analog Input (Pin This high-impedance input coder. cycle begins first falling edge following rising edge MSI. sampled approximately after rising edge prior start cycle. Power-Down Input (Pin normal operation this Input should tied high. logic this input puts device into minimum power dissipation mode. During power-down, functions stop. complete conversion cycles required establish normal operation after leaving power-down mode. Convert Clock Input (Pin This input controls complete conversion sequence during cycle must receive clock which times frequency MSI. only exception times frequency during short-cycle operation. General Modes Operation section. must synchronous approximately rising edge aligned with MSI.
Master Sync Input (Pin This determines conversion rate both coder decoder. conversion takes place during each period digital clock applied this input (except short-cycle operation, General Modes Operation section). must synchronous approximately rising edge aligned with CCI. Transmit Data Clock (Pin Digital data from coder serially transmitted from rising edges whenever logic high. must approximately rising edge aligned with TDE. Generally, when rises, first rising edge clocks first data bit. high when rises, first will clocked first rising edge after rises will clock second data bit. Transmit Data Enable (Pin This used initiate serial transfer data from coder provides three-state control pin. rising edge follows TDE) signals start data transfer from pin. resulting high logic level also releases from high-impedance state. must remain high throughout data transfer keep low-impedance state must return state prior each data transfer. remains high more than clocks, bits data will recirculated. (Note: cycle begins first falling edge after rising edge MSI. internal transmit latch updated half periods prior start cycle. pulse generated logical first transfers data transmit shift register, this pulse must occur when transmit latch updated. Figure su6, su6, Figure Transmit Digital Data (Pin This three-state output data from coder controlled pins. high- impedance state whenever logic low. first data output from rising edge follows TDE) each subsequent output rising edges TDC. output data formats available described description below. Transmit Data Format (Pin 13-bit digital output coder available 16-bit two's complement formats determined state this pin. logic this causes data from 16-bit sign-extended format follows: SSSSM where represent sign, most significant bit, least significant bit, respectively. logic this formats data follows: LSSS (see Figure data affected state this "digital loopback" needed (TDD data looped back into RDD), this should high.
MC145402
Receive Data Clock (Pin Receive digital data accepted decoder first falling edges after rising edge. Receive Clock Enable (Pin This identifies beginning data transfer into decoder. first falling edges after rising edge will clock data into decoder data input, RDD. must return prior each data transfer. Since receive data latched into receive latch last falling edge prior MSI, data transfers span this falling edge without loss data. Receive Digital Data (Pin This data input decoder controlled pins described above. Two's complement data loaded following sequence: where represent sign, most significant bit, least significant bit, respectively. Only first bits clocked after rises will accepted decoding. additional bits will ignored (see Figure
frequency. Figure shows circuit that generates this clocking configuration; Application Circuits section. SIGNAL DISTORTION RATIO Figures show graphs typical signal distortion ratios versus signal level MC145402. presented data referenced 1020 input sinusoidal frequency with signal levels referenced transmission level point adjusted (e.g., dBm0 with 6.30 4.53 peak-to-peak). comparison, ideal signal noise ratios 10-, 11-, 12-, 13-bit converters also shown. equation used ideal signal distortion ratio 1.76 where number bits resolution, bit, 1.76 20log (3/2). (3/2) approximately ratio sine wave white noise. signal noise plus distortion ratio measured through brickwall low-pass filter Nyquist frequency sample rate. sample rate, low-pass filter block signals above kHz. APPLICATION CIRCUITS Figure shows typical circuit generating clock frequencies MC145402. This circuit uses MC74HC4040 2.048 crystal generate frequency internal sequencing, 1.024 date clocks, sample frequency. 4.096 crystal could used sample rate kHz. Figure shows MC145402 interfaced DSP56000 digital signal processor. DSP56000 internally generate clocks MC145402 using serial interface. provides sequencing data clocks (non-gated continuous dock) (setup Frame Sync Out, provides sample rate data enables MC145402. divide-by-four circuit generate clock recommended optimum MC145402 performance, allows DSP56000 clock data MC145402 quickly, leaving time available processing before another sample available. could used gate enables select four devices bus. TELEPHONE SYSTEM TRANSMISSION LEVEL POINT LINEAR CONVERTER REFERENCED MU-LAW COMPANDING Mu-Law companding, specified AT&T CCITT, requires 8159 quantization levels implement both conversion schemes. This mirrored about signal ground negative part wave form. implement 13-bit 12-bit) linear converter scheme requires 8192 quantization levels mirrored about signal ground. specify this converter such that used interface with, alternative telephony based applications, following explanation gain translation. 13-bit linear converter scheme 8192 quantization levels. goal able convert between these encoding schemes with minimal distortion. This dictates setting LSBs same level. this achieved requires reference voltage linear converter
GENERAL INFORMATION
GENERAL MODES OPERATION MC145402 three modes operation; "full" cycle mode ``short" cycle modes. full cycle mode allows simultaneous analog-to-digital (A/D) digital-to- analog (D/A) operation. short cycle modes allow either only only operation. cycles required MC145402 detect which operating mode been selected. Figure full versus short cycle clocking. Full Cycle Operation When operating full cycle mode, MC145402 performs 13-bit conversion followed 13-bit con- version. Full cycle operation selected using frequency that times frequency MSI. sample rate frequency. Short Cycle Analog-to-Digital Operation times frequency MSI, short cycle analog-to-digital operation selected. This allows 13-bit conversion only. this mode, operational data applied input ignored. Short Cycle Digital-to-Analog Operation Short cycle digital-to-analog operation selected using clock frequency that eight times sample rate. During short cycle operation, operation disabled digital data read from valid. CLOCKING RECOMMENDATIONS optimum differential nonlinearity performance, data transitions should limited first four cycles following rising edge MSI. This achieved setting having duration data clock cycles, clock
MC145402
8192/8159 times reference voltage Mu-Law converter. peak amplitude Mu-Law converter 3.17 dBm0. peak level linear converter will 8192/8159 times peak level Mu-Law converter, which 8192/8159 3.17 dBm0. However, cannot multiply gain factor value without using common term units math (i.e., must convert this gain factor equivalent), which log10 (8192/8159) 0.03 With gain factor Mu-Law peak level: 3.17 dBm0 0.03 3.20 dBm0 Therefore, linear converter peak level 3.20 dBm0.
This another saying dBm0 level linear converter 3.20 below maximum amplitude. determine absolute dBm0 level linear converter from peak level, calculate peak level log10 3.27 (600 9.50 (600
3.20 below this level dBm0 absolute amplitude, which 9.50 3.20 6.30 (600 Therefore, calibration level, transmission level point (TLP), this part 6.30 (600 which Vrms based reference voltage 3.27
MC145402
FULL CYCLE A/D-D/A CONVERSION CONVERSION
SAMPLED UPDATED DATA TRANSFERRED INTO TRANSMIT LATCH CONVERSION CONVERSION SAMPLED DATA TRANSFERRED INTO TRANSMIT LATCH CONVERSION CONVERSION CONVERSION CONVERSION UPDATED DATA LATCHED INTO RECEIVE LATCH
CLOCK CYCLE
SHORT CYCLE ONLY
DATA LATCHED INTO RECEIVE LATCH
Figure MC145402 Full Short Cycle Timing
SHORT CYCLE ONLY
MC145402
MC145402
(TDF
(TDF
Figure MC145402 Digital Data Timing
COMPARED 9-13 IDEAL A/D; kHz; MEASURED THROUGH LOW-PASS FILTER WITH BANDWIDTH MSI/2
13-BIT 12-BIT 11-BIT 10-BIT 9-BIT
SIGNAL (NOISE DISTORTION) (dB)
INPUT LEVEL (dBm0) (1020 REFERENCED
Figure MC145402 Encoder (A/D) Signal Noise Plus Distortion Ratio
COMPARED 9-13 IDEAL D/A; kHz; MEASURED THROUGH LOW-PASS FILTER WITH BANDWIDTH MSI/2
13-BIT 12-BIT 11-BIT 10-BIT 9-BIT
SIGNAL (NOISE DISTORTION) (dB)
INPUT LEVEL (dBm0) (1020 REFERENCED
Figure MC145402 Decoder (D/A) Signal Noise Plus Distortion Ratio
MC145402
MC145402
SERIAL DATA SERIAL DATA MC74HC4040 13-BIT Aout ANALOG VOLTAGE MC74HCU04 MC74HCU04 MC74HC11 POWER CONNECTIONS VCC, GND, MC74HC11 CONTROL 13-BIT ANALOG VOLTAGE 1.024 MC145402
2.048
Figure Typical MC145402 Configuration
fsample MC74HC73
fsample fsample
MC74HC74
MC145402 Aout Vout
DSP56000
1.024
MC74HC74
MC74HC73
Figure MC145402, 13-Bit Linear Codec, Interfaced Motorola DSP56000, Digital Signal Processor, Port
MC145402
PACKAGE DIMENSIONS
SUFFIX CERAMIC CASE 620-09
-A16
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEAD WHEN FORMED PARALLEL. DIMENSION NARROW 0.76 (0.030) WHERE LEAD ENTERS CERAMIC BODY. INCHES 0.750 0.770 0.240 0.290 0.165 0.015 0.021 0.050 0.055 0.070 0.100 0.009 0.011 0.200 0.300 0.015 0.035 MILLIMETERS 19.05 19.55 6.10 7.36 4.19 0.39 0.53 1.27 1.40 1.77 2.54 0.23 0.27 5.08 7.62 0.39 0.88
-TSEATING PLANE
0.25 (0.010)
0.25 (0.010)
MC145402
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MC145402
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298
MC145402
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