HCMOS 32-bit Virtual Memory Microprocessor TS68020 Description

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HCMOS 32-bit Virtual Memory Microprocessor TS68020 Description

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Object Code Compatible with Earlier TS68000 Microprocessors Addressing Mode Extensions Enhanced Support High Level Languages Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics Fast on-chip Instruction Cache Speed Instructions Improves Bandwidth Co-processor Interface Companion 32-bit Peripherals: TS68881 TS68882 Floating Point Co-processors Pipelined Architecture with High Degree Internal Parallelism Allowing Multiple Instructions Executed Concurrently High Performance Asynchronous Non-multiplexed Full Bits Dynamic Sizing Efficiently Supports 16-, 32-bit Memories Peripherals Full Support Virtual Memory Virtual Machine Sixteen 32-bit General-purpose Data Address Registers 32-bit Supervisor Stack Pointers Special Purpose Control Registers Addressing Modes Data Types 4-Gbyte Direct Addressing Range Processor Speed: 16.67 Power Supply:
HCMOS 32-bit Virtual Memory Microprocessor TS68020
Description
TS68020 first full 32-bit implementation TS68000 family microprocessors. Using HCMOS technology, TS68020 implemented with 32-bit registers data paths, 32-bit addresses, rich instruction set, versatile addressing modes.
Screening/Quality
This product manufactured full compliance with either: MIL-STD-883 (class DESC 5962 860320 according Atmel standards
"Ordering Information" page connection: page
suffix Ceramic Grid Array suffix CQFP Ceramic Quad Flat Pack
Rev. 2115A-HIREL-07/02
Introduction
TS68020 high-performance 32-bit microprocessor. first microprocessor have evolved from 16-bit machine full 32-bit machine that provides 32-bit address data buses well 32-bit internal structures. Many techniques were utilized improve performance same time maintain compatibility with other processors TS68000 Family. Among improvements addressing modes which better support high-level language structures, expanded instruction which provides 32-bit operations limited cases supported TS68000 several instructions which support data types. special-purpose applications when general-purpose processor alone adequate, co-processor interface provided. TS68020 high-performance microprocessor implemented HCMOS, power, small geometry process. This process allows CMOS HMOS (high density NMOS) gates combined same device. CMOS structures used where speed power required, HMOS structures used where minimum silicon area desired. This technology enables TS68020 very fast while consuming less power (less than watts) still have reasonably small size. utilizes about 190.000 transistors, 103.000 which actually implemented. package pin-grid array (PGA) with pins, arranged pins side with depopulated center pins ceramic quad flat pack. Figure block diagram TS68020. processor divided into main sections: controller micromachine. This division reflects autonomy with which sections operate.
Figure TS68020 Block Diagram
controller consists address data pads multiplexers required support dynamic sizing, macro controller which schedules cycles basis priority with state machines (one control cycles operated accesses other control cycles instruction accesses), instruction cache with associated control.
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TS68020
micromachine consists execution unit, nanorom microrom storage, instruction decoder, instruction pipe, associated control sections. execution unit consists address section, operand address section, data section. Microcode control provided modified two-level store microrom nanorom. Programmed logical arrays (PLAs) used provide instruction decode sequencing information. instruction pipe other individual control sections provide secondary decode instructions generated actual control signals that result decoding interpretation nanorom micorom information. Figure Terminal Designation
Figure CQFP Terminal Designation
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Figure Functional Signal Groups
Signal Description
Figure illustrates functional signal groups Table lists signals their function. pins separated into four groups provide individual power supply connections address buffers, data buffers, other output buffers internal logic.
Group Address Data Logic Clock
G11,
A10, B9,C3, L11, G12, H13,
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TS68020
Table Signal Index
Signal Name Address Data Function Codes Size Mnemonic A0-A31 D0-D31 FC0-FC2 SIZ0/SIZ1 Function 32-bit Address Used address 294, 967, bytes. 32-bit Data Used Transfer bits Data Cycle. 3-bit Function Case Used Identify Address Space Each Cycle. Indicates Number Bytes Remaining Transferred this Cycle. These Signals, Together with Define Active Sections Data Bus. Provides Indicator that Current Cycle Part Indivisiblereadmodify-write Operation. Provides Indication that Cycle Beginning. Identical Operation that Except that Asserted Only During First Cycle Operand Transfer. Indicates that Valid Address Bus. Indicates that Valid Data Placed Data External Device been Laced Data TS68020. Defines Transfer Read Write. Provides Enable Signal External Data Buffers. Response Signals that Indicate Requested Data Transfer Operation Completed. Addition, these Lines Indicate Size External Port Cycle-by-cycle Basis. Dynamically Disables On-chip Cache Assist Emulator Support. Provides Encoded Interrupt Level Processor. Requests Autovector During Interrupt Acknowledge Cycle. Indicates that Interrupt Pending. Indicates that External Device Requires Mastership. Indicates that External Device Assume Mastership. Indicates that External Device Assumed Mastership. System Reset. Indicates that Processor Should Suspend Activity. Indicates Invalid Illegal Operation Being Attempted. Clock Input Processor. +5-volt Power Supply. Ground Connection.
Read-Modify-Write Cycle External Cycle Start Operand Cycle Start Address Strobe Data Strobe Read/Write Data Buffer Enable Data Transfer Size Acknowledge Cache Disable Interrupt Priority Level Autovector Interrupt Pending Request Grant Grant Acknowledge Reset Halt Error Clock Power Supply Ground
DBEN DSACK0/DSACK1
CDIS IPL0-IPL2 AVEC IPEND BGACK RESET HALT BERR
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Detailed Specifications Scope Applicable Documents
MIL-STD-883
MIL-STD-883: Test Methods Procedures Electronics MIL-PRF-38535 appendix General Specifications Microcircuits Desc Drawing 5962 860320xxx This drawing describes specific requirements microprocessor 68020, 16.67 MHz, MHz, compliance with MIL-STD-883 class
Requirements
General Design Construction
Terminal Connections Depending package, terminal connections shall shown Figure Figure Lead material finish shall option MIL-STD-1835. macrocircuits packages hermetically sealed ceramic packages which conform case outlines MIL-STD-1835 (when defined): 114-pin SQ.PGA Outline 132-pin Ceramic Quad Flat Pack CQFP microcircuits accordance with applicable document specified herein.
Lead Material Finish Package
precise case outlines described Figure Figure
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Electrical Characteristics
Table Absolute Maximum Ratings
Symbol Pdmax Parameter Supply Voltage Input Voltage Power Dissipation Tcase -55°C Tcase +125°C Suffix Tcase Tstg Tleads Operating Temperature Suffix Storage Temperature Lead Temperature Sec. Soldering +150 +270 Test Conditions -0.3 -0.5 +7.0 +7.0 +125 Unit
Table Recommended Condition Unless otherwise stated, voltages referenced reference terminal (see Table
Symbol Tcase Parameter Supply Voltage Level Input Voltage High Level Input Voltage Operating Temperature Value Output Load Resistance Output Loading Capacitance 68020-16 tr(c)-tf(c) Clock Rise Time (See Figure 68020-20 68020-25 68020-16 Clock Frequency (See Figure 68020-20 68020-25 68020-16 tcyc Cycle Time (see Figure 68020-20 68020-25 68020-16 tW(CL) Clock Pulse Width (See Figure 68020-20 68020-25 68020-16 tW(CH) Note: Clock Pulse Width High (See Figure 68020-20 12.5 12.5 -0.3
5.25 +125
Unit
16.67
68020-25 Load network number specified (Table gives maximum loading relevant output.
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This device contains protective circuitry against damage high static voltages electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VCC). Figure Clock Input Timing Diagram
Note:
Timing measurements referenced from voltage 0.8V high voltage 2.0V, unless otherwise noted. voltage swing through this range should start outside pass through range such that rise fall will linear between 0.8V 2.0V.
Table Thermal Characteristics 25°C
Package Symbol Parameter Thermal Resistance Ceramic Junction Ambient Thermal Resistance Ceramic Junction Case Thermal Resistance Ceramic Junction Ambient Thermal Resistance Ceramic Junction Case Value Unit
°C/W °C/W °C/W °C/W
CQFP
Power Considerations
average chip-junction temperature, obtained from: Ambient Temperature, Package Thermal Resistance, Junction-to-Ambient, °C/W PINT PI/O PINT VCC, Watts Chip Internal Power PI/O Power Dissipation Input Output Pins User Determined most applications PI/O PINT neglected. approximate relationship between PI/O neglected) 273) Solving equations gives: 273)
where constant pertaining particular part determined from equation measuring equilibrium) known Using this value values obtained solving equations iterativley value
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total thermal resistance package (JA) separated into components, representing barrier heat flow from semiconductor junction package (case), surface (JC) from case outside ambient (CA). These terms related equation:
device related cannot influenced user. However, user dependent minimized such thermal management techniques heat sinks, ambient cooling thermal convection. Thus, good thermal management part user significantly reduce that approximately equals Substitution equation will result lower semiconductor junction temperature.
Mechanical Environment Marking
microcircuits shall meet mechanical environmental requirements MIL-STD883 class devices. document where defined marking identified related reference documents. Each microcircuit legible permanently marked with following information minimum: ATMEL Logo Manufacturer's Part Number Class Identification Date-code Inspection Identifier Available Country Manufacturing
Quality Conformance Inspection
DESC/MIL-STD-883
accordance with MIL-M-38510 method 5005 MIL-STD-883. Group inspections performed each production lot. Group inspections performed periodical basis.
Electrical Characteristics
General Requirements
static dynamic electrical characteristics specified relevant measurement conditions given below. (last issue request marketing services). Table Static electrical characteristics electrical variants. Table Dynamic electrical characteristics 68020-16 (16.67 MHz), 68020-20 MHz) 68020-25 MHz). static characteristics, test methods refer "Test Conditions Specific Device" page hereafter this specification (Table
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dynamic characteristics (Table test methods refer 748-2 method, where existing. Indication "min." "max." column "test temperature" means minimum maximum operating temperature.
Table Static Characteristics. 5.0VDC 10%; 0VDC; -55/+125°C -40/+85°C (Figure Figure
Symbol Parameter Maximum Supply Current Maximum Supply Current High Level Input Voltage Level Input Voltage High Level Output Voltage Outputs Level Output Voltage Outputs A0-A31, FC0-FC2, D0-D31, SIZ0-SIZ1, Level Output Voltage Outputs RMC, R/W, DBEN, IPEND Level Output Voltage Outputs ECS, Level Output Voltage Outputs HALT, RESET Input Leakage Current (High State) High level leakage current three-state outputs Outputs A0-A31, DBEN, D0-D31, R/W, FC0-FC2, RMC, SIZ0-SIZ1 Level Leakage Current Three-state Outputs Outputs A0-A31, DBEN, D0-D31 R/W, FC0-FC2, RMC, SIZ0-SIZ1 Output Short-circuit Current (Any Output) Condition 5.5V Tcase -55°C +25°C 5.5V Tcase 125°C 0.5V 4.5V 5.5V 0.5V 2.4V 4.5V 5.5V Load Circuit Figure 1.22 Load Circuit Figure Load Circuit Figure 10.7 Load Circuit Figure Figure -0.5V (Max) 2.4V -0.5 Units
IOHZ
IOLZ
0.5V
5.5V (Pulsed. Duration Duty Cycle 10:1)
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Dynamic (Switching) Characteristics
limits values given this section apply over full case temperature range 55°C +125°C range 4.5V 5.5V 0.5V 2.4V (See also note 13). INTERVAL numbers refer timing diagrams. Figure Figure Figure
Table Dynamic Electrical Characteristics
Interval Number 68020-16 68020-20 68020-25 Unit
(11) (11) (11) (11)
Symbol tCPW tCHAV tCHEV tCHAZX tCHAZn tCLSA tSTSA tECSA tOCSA tEOCSN tAVSA tCLSN tCLEN tSNAI tSWA tSWAW tSNSA tCSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tSNDI tDNDBN
Parameter Clock Pulse Width Clock High Address/FC/Size/RMC Valid Clock High ECS, Asserted Clock High Address/Data/FC/RMC/ Size High Impedance Clock High Address/FC/Size/RMC Invalid Clock Asserted Assertion (Read)(Skew) Width Asserted Width Asserted ECS, Width Negated Address/FC/Size/RMC Valid Asserted (and Asserted, Read) Clock Negated Clock ECS/OCS Negated Negated Address/FC/ Size/RMC Invalid (and Read) Width Asserted Width Asserted, Write Width Negated Negated Asserted Clock High AS/DS/R/W/DBEN High Impedance Negated High Clock High High Clock High High Asserted Asserted (Write) Clock High Data Valid Negated Data Valid Negated DBEN Negated (Write)
Notes
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Table Dynamic Electrical Characteristics (Continued)
Interval Number
(11) (11) (4)(11)
68020-16
68020-20
68020-25 Clks Clks Clks Clks
(11)
Symbol tDVSA tDICL tBELCL tSNDN tSNDI tSNDIZ tDADI tDADV tHRrf tCLBA tCLBN tBRAGA tGAGN tGABRN tCHDAR tCLDNR tCLDAW tCHDNW tRADA
Parameter Data Valid Asserted (Write) Data Valid Clock (Data Setup) Late BERR/HALT Asserted Clock Setup Time Negated DSACKx/BERR/HALT/AVEC Negated Negated Data Invalid (Data Hold Time) Negated Data High Impedance DSACKx Asserted Data Valid DSACK Asserted DSACKx Valid (DSACK Asserted Skew) RESET Input Transition Time Clock Asserted Clock Negated Asserted Asserted (RMC Asserted) BGACK Asserted Negated BGACK Asserted Negated Width Negated Width Asserted Clock High DBEN Asserted (Read) Clock DBEN Negated (Read) Clock DBEN Negated (Read) Clock High DBEN Asserted (Read) DBEN Asserted (Write) DBEN Width Asserted READ WRITE Width Asserted (Write Read) Asynchronous Input Setup Time Asynchronous Input Hold Time DSACKx Asserted BERR/HALT Asserted Data Hold from Clock High BERR Negated HALT Negated (Rerun)
Unit
Notes
(2)(11) (3)(11)
(11) (11) (11)
tRWA tAIST tAIHT tDABA tDOCH tBNHN
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Table Dynamic Electrical Characteristics (Continued)
Interval Number 68020-16 16.67 68020-20 12.5 20.0 68020-25 12.5 Clks Clks Unit
(11)
Symbol tRADC tHRPW tBNHN tGANBD tGNBD Notes:
Parameter Frequency Operation Asserted Data Impedance Change RESET Pulse Width (Reset Instruction) BERR Negated HALT Negated (Rerun) BGACK Negated Driven
Notes
(11) (11)
(10)(11)
(10)(11) Negated Driven Clks This number reduced nanoseconds strobes have equal loads. asynchronous setup time requirements satisfied, DSACKx data setup time DSACKx BERR setup time ignored. data must only satisfy data clock setup time following clock cycle, BERR must only satisfy late BERR clock setup time following clock cycle. This parameter specifies maximum allowable skew between DSACK0 DSACK1 asserted DSACK1 DSACK0 asserted pattern must DSACK0 DSACK1. absence DSACKx, BERR asynchronous input using asynchronous input setup time 47). DBEN stay asserted consecutive write cycles. Actual value depends clock input waveform. This pattern indicates minimum high time event internal cache followed immediately cache miss operand cycle. This specification guarantees operations with 68881 co-processor, defines minimum time negated asserted 13A). Without this parameter, incorrect interpretation would indicate that 68020 does meet 68881 requirements. This pattern allows systems designer guarantee data hold times output side data buffers that have output enable signals generated with DBEN. Guarantees that alternate master stopped driving when 68020 regains control after arbitration sequence. Cannot tested. Provided system design purposes only. Tcase -55°C +130°C Power condition under Thermal soak minutes until thermal equilibrium. Electrical parameters tested "instant sec. after power applied. outputs unload except load capacitance. Clock fmax, LOW: HALT, RESET HIGH: DSACK0, DSACK1, CDIS, IPL0-IPL2, DBEN, AVEC, BERR.
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Test Conditions Specific Device
Loading Network applicable loading network shall defined column "Test conditions" Table referring loading network number shown Figure Figure Figure below. Figure RESET Test Loads
Figure HALT Test Load
Figure Test Load
Table Load Network
Load Note: Figure 1.22 Output Application OCS, A0-A31, D0-D31, FC0-FC2, SIZ0-SIZ1 R/W, RMC, DBEN, IPEND
0.74 Equivalent loading simulated tester.
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Time Definitions times specified Table dynamic characteristics defined Figure below, reference number given column "interval tables together with relevant figure number.
Figure Read Cycle Timing Diagram
Note:
Timing measurements referenced from voltage 0.8V high voltage 2.0V, unless otherwise noted. voltage swing through this range should start outside pass through range such that rise fall will linear between 0.8V 2.0V.
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Figure Write Cycle Timing Diagram (Continued)
Note:
Timing measurements referenced from voltage 0.8V high voltage 2.0V, unless otherwise noted. voltage swing thorough this range should start outside pass through range such that rise fall will linear between 0.8V 2.0V.
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Figure Arbitration Timing Diagram
Note:
Timing measurements referenced from voltage 0.8V high voltage 2.0V, unless otherwise noted. voltage swing thorough this range should start outside pass through range such that rise fall will linear between 0.8V 2.0V.
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Input Output Signals Dynamic Measurements Electrical Specifications Definitions specifications presented consist output delays, input setup hold times, signal skew times. signals specified relative appropriate edge TS68020 clock input and, possibly, relative more other signals. measurement specifications defined waveforms Figure order test parameters guaranteed Atmel, inputs must driven voltage levels specified Figure Outputs TS68020 specified with minimum and/or maximum limits, appropriate, measured shown. Inputs TS68020 specified with minimum and, appropriate, maximum setup hold times, measurement shown. Finally, measurements signal-to-signal specification also shown. Note that testing levels used verify conformance TS68020 specifications does affect guaranteed operation device specified electrical characteristics.
TS68020
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Figure Drive Levels Test Points Specification
Legend: Maximum Output Delay Specification Minimum Output Hold Time Minimum Input Setup Time Specification Minimum Input Hold Time Specification Signal Valid Signal Valid Specification (Maximum Minimum) Signal Valid Signal Invalid Specification (Maximum Minimum)
Notes: This output timing applicable parameters specified relative rising edge clock. This timing applicable parameters specified relative falling edge clock. This input timing applicable parameters specified relative falling edge clock. This input timing applicable parameters specified relative falling edge clock. This timing applicable parameters specified relative assertion/negation another signal.
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Additional Information
Power Consideration Capacitance (Not Inspection Purposes
Additional information shall inspection purposes. Table
Symbol
Parameter Input Capacitance
Test Conditions Tamb 25°C
Unit
Capacitance Derating Curves
Figure Figure inclusive show typical derating conditions which apply. capacitance includes stray capacitance. graphs linear outside range shown. Figure Address Capacitance Derating Curve
TS68020
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TS68020
Figure Capacitance Derating Curve
Figure R/W, SIZ0-SIZ1, Capacitance Derating Curve
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Figure IPEND, Capacitance Derating Curve
Figure DBEN Capacitance Derating Curve
TS68020
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TS68020
Figure Data Capacitance Derating Curve
Functional Description
Description Registers
shown programming models (Figure Figure TS68020 sixteen 32-bit general-purpose registers, 32-bit program counter, 32-bit supervisor stack pointers, 16-bit status register, 32-bit vector base register, 3-bit alternate function code registers, 32-bit cache handling (address control) registers. Registers D0-D7 used data registers field 32-bit), byte (8-bit), long word (32-bit), quad word (64-bit) operations. Registers A0-A6 user, interrupt, master stack pointers address registers that used software stack pointers base address registers. addition, address registers used word long word operations. (D0-D7, A0-A7) registers used index registers. status register (Figure contains interrupt priority mask (three bits) well condition codes: extend (X), negated (N), zero (Z), overflow (V), carry (C). Additional control bits indicate that processor trace mode T0), supervisor/user state (S), master/interrupt state (M). microprocessors TS68000 Family support instruction tracing (via status TS68020) where each instruction executed followed trap userdefined trace routine. TS68020 adds capability trace only change flow instructions (branch, jump, subroutine call return, etc.) using status bit. These features important software program development debug. vector base register used determine runtime location exception vector table memory, hence supports multiple vector tables each process task properly manage exceptions independent each other.
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TS68000 Family processors distinguish address spaces supervisor used program/data. These four combinations specified function code pins (FC0/FC1/FC2) during cycles, indication particular address space. Using function codes, memory sub-system distinguish between authorized access (supervisor mode privileged access) unauthorized access (user mode have access supervisor program data areas). support full privileges supervisor, alternate function code registers allow supervisor specify access user program data prelo ading SFC/DFC registers appropriately. cache registers (control CACR, address CAAR) allow software manipulation on-chip instruction cache. Control status accesses instruction cache provided cache control register (CACR), while cache address register (CAAR) holds address those cache control functions that require address. Figure User Programming Model
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Figure Supervisor Programming Model Supplement
Figure Status Register
Data Types Addressing Modes
Seven basic types supported. These data types are: Bits Bits Flieds (String consecutive bits, 1-32 bits long) Digits (Packed: digits/byte, Unpacked: digit/byte) Byte Integers (8-bit) Word Integers (16-bit) Long Word Integers (32-bit) Quad Word Integers (64-bit)
addition, operations other data types, such memory addresses, status word data, etc., provided instruction set. co-processor mechanism allows direct support floating-point data type with TS68881 TS68882 floating-point co-processors, well specialized user-defined data types functions.
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addressing modes, shown Table include nine basic types: Register Direct Register Indirect Register Indirect with Index Memory Indirect Program Counter Indirect with Displacement Program Counter Indirect with Index Program Counter Memory Indirect Absolute Immediate
register indirect addressing modes support postincrement, predecrement, offset, indexing. Programmers find these capabilities particularly useful handling advanced data structures common sophisticated applications high level languages. program counter relative mode also index offset capabilities; programmers find that this addressing mode required support position-independent software. addition these addressing modes, TS68020 provides data operand sizing scaling; these features provide performance enhancements programmer.
Table TS68020 Addressing Modes
Addressing Modes Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Post Increment Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Post-Indexed Memory Indirect Pre-Indexed Program Counter Indirect with Displacement Program Counter Indirect with Index Indirect with Index (8-bit Displacement) Indirect with Index (Base Displacement) Program Counter Memory Indirect Memory Indirect Post-Indexed Memory Indirect Pre-Indexed Syntax (An) (An) (An) (d16An) (d8, (bd, ([bd, An], ([bd, Xn], (d16, (d8, (bd, ([bd, PC], ([bd, Xn]),
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Table TS68020 Addressing Modes (Continued)
Addressing Modes Absolute Absolute Short Absolute Long Syntax xxx.W xxx.L
Immediate =data Notes: Data Register, D0-D7. Address Register, A0-A7. twos-complement, sign-extended displacement; added part effective calculation; size (d8) (d16) bits; when omitted assemblers value zero. Address data register used index register; form SIZE*SCALE, where SIZE is.W or.L (indicates index register size) SCALE (index register multiplied SCALE); SIZE and/or SCALE optional. two-complement base displacement; when present, size 32-bit. Outer displacement, added part effective address calculation after memory indirection; optional with size 32-bit. Program Counter. (data) Immediate value bits. Effective Address. indirect address long word address.
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Instruction Overview
TS68020 instruction shown Table Special emphasis been given instruction set's support structured high-level languages sophisticated operating systems. Each instruction, with exceptions, operates bytes, words, long words most instructions addressing modes. Many instruction extensions have been made TS68020 take advantage full 32-bit operation where, earlier 68000 Family members, only bits values were used. TS68020 upward source- object-level code compatible with family because supports instructions that previous family members offer. Additional instructions provided TS68020 support advanced features. Table Instruction
Mnemonic ABCD ADDA ADDI ADDQ ADDX ANDI ASL, BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BSET BTST Description Decimal with Extend Address Immediate Quick with Extend Logical Logical Immediate Arithmetic Shift Left Right Branch Conditionally Test Change Test Clear Test Field Change Test Field Clear Signed Field Extract Unsigned Field Extract Field Find First Field Insert Test Field Test Field Breakpoint Branch Test Branch Subroutine Test
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Table Instruction (Continued)
Mnemonic CALLM CAS2 CHK2 CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EORI EXT, EXTB ILLEGAL LINK LSL, MOVE MOVEA MOVE MOVE MOVE MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEGX Description Call Module Compare Swap Operands Compare Swap Dual Operands Check Register Against Bound Check Register Against Upper Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory Memory Compare Register Against Upper Lower Bounds
Test Condition, Decrement Branch Signed Divide Unsigned Divide Logical Exclusive Logical Exclusive Immediate Exchange Registers Sign Extend Take Illegal Instruction Tape Jump Jump Subroutine Load Effective Address Link Allocate Logical Shift Left Right Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend Operation Logical Complement
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Table Instruction (Continued)
Mnemonic PACK RESET ROL, ROXL, ROXR RRTR SBCD STOP SUBA SUBI SUBQ SUBX SWAP TRAP TRAPcc TRAPV UNLK UNPK Co-processor Instructions cpBCC cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc Branch Conditionally Test Co-processor Condition, Decrement Branch Co-processor General Instruction Restore Internal State Co-processor Save Internal State Co-processor Conditionally Trap Conditionally Description Logical Inclusive Logical Inclusive Immediate Pack Push Effective Address Reset External Devices Rotate Left Right Rotate with Extend Left Right Return Deallocate Return Exception Return from Module Return Restore Codes Return from Subroutine Subtract Decimal with Extend Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand Trap Trap Conditionally Trap Overflow Test Operand Unlink Unpack
TS68020
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TS68020
Field Operation TS68020 supports variable length field operations 32-bit. field start position span address boundary full length field, 32-bit maximum. field insert (BFINS) inserts value into field. field extract unsigned (BFEXTU) field extract signed (BFEXTS) extract unsigned signed value from field. BFFFO finds first field that set. complement TS68000 manipulation instruction, there field change, clear, test instructions (BFCHG, BFCLR, BFSET, BFTST). Using on-chip barrel shifter, field instructions very fast particularly useful applications using packed bits fields, such graphics communications. TS68000 Family supports operations including add, subtract, negation. TS68020 adds PACK UNPACK operations conversions from binary form well other conversions, e.g., ASCII EBCDIC. PACK instruction reduces bytes data into single byte while UNPACK reverses operation. Previous 68000 Family members offer variable bounds checking only upper limit bound. underlying assumption that lower bound zero. This expanded TS68020 providing instructions, CHK2 CMP2. These instructions allow checking comparing both upper lower bounds. These instructions either signed unsigned. CMP2 instructions sets condition codes upon completion while CHK2 instruction, addition setting condition codes, will take system trap either boundary condition exceeded. Three additions have been made system trap capabilities TS68020. current TRAPV (trap overflow) instruction been expanded TRAPcc format where condition code allowed trapping condition. And, TRAPcc instruction expanded optionally provide additional words following trap instruction user-specified information presented trap handler. These additional words used when needed provide simple error codes debug information interactive runtime debugging post-mortem program dumps. Compilers provide direction run-time execution routines towards handling specific conditions. breakpoint instruction, BKPT, used support program breakpoint function debug monitors real-time in-circuit hardware emulators, operation will dependent actual system implementation. Execution this instruction causes TS68020 breakpoint acknowledge cycle, with 3-bit breakpoint identifier placed address lines This 3-bit identifier permits eight breakpoints easily differentiated. normal response TS68020 operation word (typically instruction, originally replaced debugger with breakpoint instruction) placed data lines external debugger hardware breakpoint acknowledge cycle properly terminated. TS68020 then executes this operation word place breakpoint instruction. debugger hardware count number executions each breakpoint halt execution after pre-determined number cycles.
Binary Coded Decimal (BCD) Support
Bounds Checking
System Traps
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Multi-processing
further support multi-processing with TS68020, compare swap instruction, CAS, been added. This instruction makes read-modify-write cycle compare operands swap third operand pending results compare. variant this instruction, CAS2, performs similarly comparing dual operand pairs, updating operands. These multi-processing operations useful when using common memory share pass data between multiple processing elements. read-modify-write cycle indivisible operand that allows reading updating "lock" operand used control access common memory elements. CAS2 instruction more powerful since dual operands allow "lock" checked values (i.e., both pointers doubly-linked list) updated according lock's status, single operation.
Module Support
TS68020 includes support modules with call module (CALLM) return from module (RTM) instructions. CALLM instruction references module descriptor. This descriptor contains control information entry into associated module. CALLM instruction creates module stack frame stores module state that frame. Rinstruction recovers previous module state from stack frame returns calling module. module interface also provides mechanism finer resolution access control external hardware. Although TS68020 does interrupt access control information, does communicate with external hardware when access control changed, relies external hardware verify that changes legal. CALLM RTM, when used subroutine calls returns with proper descriptor formats, cause TS68020 perform necessary actions verify legitimate access modules.
Virtual Memory/Machine Concepts
full addressing range TS68020 4-Gbyte 294, 967, 296). However, most TS68020 systems implement smaller physical memory. Nonetheless, using virtual memory techniques, system made appear have full 4-Gbyte physical memory available each user program. These techniques have been used many years large mainframe computers minicomputers. With TS68020 with TS68010 TS68012), virtual memory fully supported microprocessor-based systems. virtual memory system, user program written though large amount memory available when actually only smaller amount memory physically present system. similar fashion, system provides user programs access other devices that physically present system, such tape drives, disk drives, printers, terminals. With proper software emulation, physical system made appear user program other 68000 computer system program given full access resources that emulated system. Such emulator system called virtual machine.
Virtual Memory
basic mechanism supporting virtual memory provides limited amount high-speed physical memory that accessed directly processor while maintaining much larger "virtual" memory secondary storage devices such large capacity disk drives. When processor attempts access location virtual memory that resident physical memory (referred page fault), access that location temporarily suspended while necessary data fetched from secondary storage placed physical memory; suspended access then either restarted continued.
TS68020
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TS68020
TS68020 uses instruction continuation support virtual memory. order TS68020 instruction continuation, stores internal state supervisor stack when cycle terminated with error signal. then loads program counter with address virtual memory error handler from exception vector table (entry number two) resumes program execution that address. When error exception handler routine completed execution, instruction executed which reloads TS68020 with internal state stored stack, reruns faulted cycle (when required), continues suspended instruction. Instruction continuation crucial support virtual devices memorymapped input/output systems. Since registers virtual device simulated memory map, access such register will cause fault function register emulated software. Virtual Machine typical virtual machine system development software, such operating system, machine also under development available programming use. such system, governing operating system emulates hardware prototype system allows operating system executed debugged though were running hardware. Since operating system controlled governing operating system, executed lower privilege level than governing operating system. Thus, attempts operating system virtual resources that physically present (and should emulated) trapped governing system handled software. TS68020, virtual machine fully supported running operating system user mode. governing operating system executes supervisor mode attempt operating system access supervisor resources execute privileged instructions will cause trap governing operating system. Though TS68020 full 32-bit data bus, offers ability automatically dynamically downsize 16-bit peripheral devices unable accommodate entire 32-bit. This feature allows programmer ability write code that bus-width specific. example, long word (32-bit) accesses peripherals used code, TS68020 will transfer only amount data that peripheral manage. This feature allows peripheral define port size 16-, 32-bit wide TS68020 will dynamically size data transfer accordingly, using multiple cycles when necessary. Hence, programmers required program each device port size know specific port size before coding; hardware designers have flexibility choose implementations independent software prejudices. This accomplished through DSACK pins occurs cycle-by-cycle basis. example, processor executing instruction that requires reading long word operand, will attempt read 32-bit during first cycle long word address boundary. port responds that 32-bit wide, TS68020 latches 32-bit data continues. port responds that 16-bit wide, TS68020 latches valid bits data runs another cycle obtain other 16-bit data. 8-bit port handled similarly with four read cycles. Each port fixed assignment particular sections data bus. Justification data handled automatically dynamic sizing. When reading 16-bit data from 32-bit port, data appear bottom half bus, depending address data. TS68020 determines which portion needed support transfer dynamically adjusts read write data those data lines.
Operand Transfer Mechanism
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TS68020 will always transfer maximum amount data cycles; i.e., always assumes port 32-bit wide when beginning cycle. addition, TS68020 restrictions concerning alignment operands memory; long word operands need aligned long word address boundaries. When misaligned data requires multiple cycles, TS68020 aligned data requires multiple cycles, TS68020 automatically runs minimum number cycles.
Co-processor Concept
co-processor interface mechanism extending instruction TS68000 Family. Examples these extensions addition specialized data operands existing data types case floating point, inclusion data types operations them implemented TS68881 TS68882 floating point co-processors. programmer's model TS68000 Family microprocessors based sequential, non-concurrent instruction execution. This means each instruction completely executed prior beginning next instruction. Hence, instructions operate concurrently programmer's model. Most microprocessors implement sequential model which greatly simplifies programmer responsibilities since sequencing control automatic discrete. TS68000 co-processor interface designed extend programmer's model provides full support sequential, non-concurrent instruction execution model. Hence, instruction execution co-processor assumed overlap with instruction execution with main microprocessor. Yet, TS68000 co-processor interface does allow concurrent operation when concurrency properly accommodated. example, TS68881 TS68882 floating-point co-processor will allow TS68020 proceed executing instruction while co-processor continues floating-point operation, point that TS68020 sends another request co-processor. Adhering sequential execution model, request co-processor continues floating-point operation, co-processor completes each TS68881 TS68882 instruction before starts next, TS68020 allowed proceed concurrent fashion. co-processors divided into types their utilization characteristics. coprocessor co-processor control independent main processor. co-processor non-DMA co-processor does have capability controlling bus. Both co-processor types utilize same protocol main processor resources. Implementation co-processor non-DMA type based primarily bandwidth co-processor, performance, cost issues. communication protocol between main processor co-processor necessary execute co-processor instruction based group co-processor interface registers (Table which defined TS68000 Family co-processor interface. TS68020 hardware uses standard TS68000 asynchronous cycles access registers. Thus, co-processor doesn't require special hardware; interface implemented co-processor interface register must only satisfy TS68020 address, data, control signal timing guarantee proper communication with main processor. TS68020 implements communication protocol with co-processors hardware (and microcode) handles operations automatically programmer only concerned with instructions data types provided co-processor extensions TS68020 instruction data types.
TS68020
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TS68020
Other microprocessors TS68000 Family operate TS68000 co-processor even though they have hardware implementation co-processor interface does TS68020. Since co-processor operated through coprocessor interface registers which accessed normal asynchronous cycles, co-processor used peripheral device. Software easily emulates communication protocol addressing co-processor interface registers appropriately passing necessary commands operands required coprocessor. co-processor interface registers implemented co-processor addition those registers implemented extensions TS68020 programmer's model. example, TS68881 implements co-processor interface registers shown Table registers programming model, including eight 80-bit floating-point data registers three 32-bit control/status registers used TS68881 programmer. Table Co-processor Interface Registers
Register Response Control Save Restore Operation Word Command Word Condition Word Operand Register Select Instruction Address Operand Address Function Requests Action from Initiate Save Internal State Initiate Restore Internal State Current Co-processor Instruction Co-processor Specific Command Condition Evaluated 32-bit Operand Specifies Register Mask Pointer Co-processor Instruction Pointer Co-processor Operand
Table Co-processor Primitives
Processor Synchronization Busy with Current Instruction Proceed with Next Instruction, Trace Service Interrupts Re-query, Trace Enable Proceed with Execution, Condition True/False Instruction Manipulation Transfer Operation Word Transfer Words from Instruction Stream Exception Handling Take Privilege Violation Take Pre-Instruction Exception Take Mid-Instruction Exception Take Post-Instruction Exception
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Table Co-processor Primitives (Continued)
General Operand Transfer Evaluate Pass (Ea.) Evaluate (Ea.) Transfer Data Write Previously Evaluated (Ea.) Take Address Transfer Data Transfer to/from Stack Register Transfer Transfer Register Transfer Control Register Transfer Multiple Registers Transfer Multiple Co-processor Registers Transfer and/or ScanPC
eight processors supported single system with system-unique co-processor identifier encoded co-processor instruction. When accessing coprocessor, TS68020 executes standard read write cycle address space, encoded function codes, places co-processor identifier address used chip-select logic select particular co-processor. Since standard cycle used access co-processor, co-processor located according system design requirements, whether located microprocessor local bus, another board system bus, other place where chip-select co-processor protocol using standard TS68000 cycles supported. Co-processor Protocol Interprocessor transfers initiated main processor during co-processor instruction execution. During processing co-processor instruction, main processor transfers instruction information data associated co-processor, receives data, requests, status information from co-processor. These transfers based TS68000 cycles. typical co-processor protocol which main processor follows main processor initiates communications writing command information location co-processor interface. main processor reads co-processor response that information. response indicate that co-processor busy, main processor should again query co-processor. This allows main processor co-processor synchronize their concurrent operations. response indicate some exception condition; main processor acknowledges exception begins exception processing. response indicate that co-processor needs main processor perform some service such transferring data from co-processor. coprocessor also request that main processor query co-processor again after service complete. response indicate that main processor needed further processing instruction. communication terminated, main processor free begin execution next instruction. this point coprocessor protocol, main processor continues execute instruction stream, main processor operate concurrently with co-processor.
TS68020
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TS68020
When main processor encounters next co-processor instruction, main processor queries co-processor until co-processor ready; meanwhile, main processor service interrupts context switch execute other tasks, example. Each co-processor instruction type specific requirements based this simplified protocol. co-processor interface many extension words requires implement co-processor instruction. Primitives/Response response register means which co-processor communicates service requests main processor. content co-processor response register primitive instruction main processor which read during co-processor communication main processor. main processor "executes" this primitive, thereby providing services requires co-processor. Table summarizes co-processor primitives that TS68020 accepts.
Exceptions
Kinds Exceptions Exception generated either internal external causes. externally generated exceptions interrupts, error, reset requests. interrupts requests from peripheral devices processor action while error reset pins used access control processor restart. internally generated exceptions come from instructions, address errors, tracing, breakpoints. TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, instructions generate exceptions part their execution. Tracing behaves like very high priority, internally generated interrupt whenever processed. other internally generated exceptions caused illegal instructions, instruction fetches from addresses, privilege violations. Exception processing occurs four steps. During first step, internal copy made status register. After copy made, special processor state bits status register changed. set, putting processor into supervisor privilege state. Also, bits negated, allowing exception handler execute unhindered tracing. reset interrupt exceptions, interrupt priority mask also updated. second step, vector number exception determined. interrupts, vector number obtained processor read that classified interrupt acknowledge cycle. co-processor detected exceptions, victor number included co-processor exception primitive response. other exceptions, internal logic provides vector number. This vector number then used generate address exception vector. third step save current processor status. exception stack frame created filled supervisor stack. order minimize amount machine state that saved, various stack frame sizes used contain processor state depending type exception where occurred during instruction execution. exception interrupt forced off, short four word exception stack frame saved master stack which indicates that exception saved interrupt stack. exception reset, simply forced off, reset vector accessed.
Exception Processing Sequence
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TS68020 provides extension exception stacking process. status register set, master stack pointer (MSP) used task related exceptions. When non-task exception occurs (i.e., interrupt), cleared interrupt stack pointer (ISP) used. This feature allows task's stack area carried within single processor control block tasks initiated simply reloading master stack pointer setting bit. fourth last step exception processing same exceptions. exception vector offset determined multiplying vector number four. This offset then added contents vector base register (VBR) determine memory address exception vector. program counter value fetched from exception vector. instruction address given exception vector fetched, normal instruction decoding execution started.
On-chip Instruction Cache
Studies have shown that typical programs spend most their execution time main routines tight loops. This phenomenon known locality reference, impact performance program. TS68020 takes limited advantage this phenomenon form loop mode operation which allows certain instructions, when coupled with DBcc instruction, execute without overhead instruction fetches. effect, this three word cache. Although cache hardware been supplied full range computer systems many years, technology allows this feature integrated into microprocessor. There were primary goals TS68020 microprocessor cache. first design goal reduce processor external activity. given TS68000 system, TS68000 processor will approximately percent (for greater) available bandwidth. This extremely efficient perfecting algorithm overall speed internal architecture design. Thus, TS68000 system with more than master (such processor device) multiprocessor system, performance degradation occur lack available bandwidth. Therefore, important goal TS68020 on-chip cache provide substantial increase total available bandwidth. second primary design goal increase effective throughput larger memory sizes slower memories increased average access time. placing high speed cache between processor rest memory system, effective access time becomes: tACC h**tCACHE h)*text where tACC effective system access time, tCACHE cache access time, access time rest system, ratio percentage time that data found cache. Thus, given system design, TS68020 onchip cache provides substantial performance increase, allows much slower less expensive memories used same processor performance. throughput increase TS68020 gained ways. First, TS68020 cache accessed clock cycles versus three cycles (minimum) required external access. instruction fetch that currently resident cache will provide improvement over corresponding external access.
TS68020 Cache Goals
TS68020
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TS68020
Second, probably most important benefit cache, that allows instruction stream fetches operand accesses proceed parallel. example, TS68020 requires both instruction stream access operand access, instruction resident cache, operand access will proceed unimpeded rather than being queued behind instruction fetch. Similarly, TS68020 fully capable executing several internal instructions (instructions that require bus) while completing operand access another instruction. TS68020 instruction cache 256-byte direct mapped cache organized long word entries. Each cache entry consists field made upper address bits, (user/supervisor) value, valid bit, 32-bit instruction data (Figure 22). Figure TS68020 On-chip Cache Organization
TS68020 employs 32-bit data fetches instructions long word address boundaries. Hence, each 32-bit instruction fetch brings 16-bit instruction words which then written into on-chip cache. When cache enabled, subsequent prefetch will find next 16-bit instruction word already present cache related cycle saved. cache were enabled, subsequent prefetch will find controller still holds full 32-bit satisfy prefetch again save related cycle. even when on-chip instruction cache enabled, controller provides instruction "cache hit" rate 50%.
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Preparation Delivery
Certificate Compliance Atmel offers certificate compliance with each shipment parts, affirming products compliance with MIL-STD-883 guaranteeing parameters tested extreme temperatures entire temperature range.
Handling
devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended: Device should handled benches with conductive grounded surface. Ground test equipment, tools operator handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above 50%, practical.
TS68020
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TS68020
Package Mechanical Data
Figure 114-lead Ceramic Grid Array
Figure Pins Ceramic Quad Flat Pack
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Mass
grams typically CQFP grams typically
Terminal Connections
114-lead Ceramic Grid Array 132-lead Ceramic Quad Flat Pack
Figure
Figure
TS68020
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TS68020
Ordering Information
Hi-REL Product
Commercial Atmel Part-Number TS68020MRB/C16 TS68020MR1B/C16 TS68020MRB/C20 TS68020MR1B/C20 TS68020MRB/C25 TS68020MR1B/C25 TS68020MFB/C16 TS68020MF1B/C16 TS68020MFB/C20 TS68020MF1B/C20 TS68020MFB/C25 TS68020MF1B/C25 TS68020DESC02XA TS68020DESC03XA TS68020DESC04XA TS68020DESC02XC TS68020DESC03XC TS68020DESC04XC TS68020DESC02YA TS68020DESC03YA TS68020DESC04YA TS68020DESC02YC TS68020DESC03YC TS68020DESC04YC Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC Package 114/tin 114/tin 114/tin CQFP CQFP 132/tin CQFP CQFP 132/tin CQFP CQFP 132/tin 114/tin 114/tin 114/tin CQFP 132/tin CQFP 132/tin CQFP 132/tin CQFP CQFP CQFP Temperature Range (°C) -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 Frequency (MHz) 16.67 16.67 16.67 16.67 16.67 16.67 16.67 16.67 Drawing Number 5962-8603202XA 5962-8603203XA 5962-8603204XA 5962-8603202XC 5962-8603203XC 5962-8603204XC 5962-8603202YA 5962-8603203YA 5962-8603204YA 5962-8603202YC 5962-8603203YC 5962-8603204YC
Standard Product
Commercial Atmel Part-Number TS68020VR16 TS68020VR20 TS68020VR25 TS68020MR16 TS68020MR20 TS68020MR25 Norms Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Package Temperature Range (°C) -40/+85 -40/+85 -40/+85 -55/+125 -55/+125 -55/+125 Frequency (MHz) 16.67 16.67 Drawing Number Internal Internal Internal Internal Internal Internal
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Standard Product
Commercial Atmel Part-Number TS68020VF16 TS68020VF120 TS68020VF25 TS68020MF16 TS68020MF20 TS68020MF25 Norms Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Package CQFP CQFP CQFP CQFP CQFP CQFP Temperature Range (°C) -40/+85 -40/+85 -40/+85 -55/+125 -55/+125 -55/+125 Frequency (MHz) 16.67 16.67 Drawing Number Internal Internal Internal Internal Internal Internal
TS68020
Speed (MHz)
Device Type Temperature range -55, +125°C -40,
Screening Standard Class
Package grid array CQFP Hirel lead finish Gold solder (883C)
Note:
availability different versions, contact your Atmel sales office.
TS68020
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HCMOS 32-bit Virtual Memory Microprocessor TS68020 Description

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