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HCMOS 32-bit Virtual Memory Microprocessor TS68020

Screening / Quality

Features
HCMOS 32-bit Virtual Memory Microprocessor TS68020
Description
The TS68020 is the first full 32-bit implementation of the TS68000 family of microprocessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.
Screening / Quality
This product is manufactured in full compliance with either: · · · MIL-STD-883 (class B) DESC 5962 - 860320 or according to Atmel standards
See "Ordering Information" on page 43. Pin connection: see page 3.
R suffix PGA 114 Ceramic Pin Grid Array F suffix CQFP 132 Ceramic Quad Flat Pack
Rev. 2115A-HIREL-07 / 02
Introduction
The TS68020 is a high-performance 32-bit microprocessor. It is the first microprocessor to have evolved from a 16-bit machine to a full 32-bit machine that provides 32-bit address and data buses as well as 32-bit internal structures. Many techniques were utilized to improve performance and at the same time maintain compatibility with other processors of the TS68000 Family. Among the improvements are new addressing modes which better support high-level language structures, an expanded instruction set which provides 32-bit operations for the limited cases not supported by the TS68000 and several new instructions which support new data types. For special-purpose applications when a general-purpose processor alone is not adequate, a co-processor interface is provided. The TS68020 is a high-performance microprocessor implemented in HCMOS, low power, small geometry process. This process allows CMOS and HMOS (high density NMOS) gates to be combined on the same device. CMOS structures are used where speed and low power is required, and HMOS structures are used where minimum silicon area is desired. This technology enables the TS68020 to be very fast while consuming less power (less than 1.5 watts) and still have a reasonably small die size. It utilizes about 190.000 transistors, 103.000 of which are actually implemented. The package is a pin-grid array (PGA) with 114 pins, arranged 13 pins on a side with a depopulated center and 132 pins ceramic quad flat pack. Figure 1 is a block diagram of the TS68020. The processor can be divided into two main sections: the bus controller and the micromachine. This division reflects the autonomy with which the sections operate.
Figure 1. TS68020 Block Diagram
The bus controller consists of the address and data pads and multiplexers required to support dynamic bus sizing, a macro bus controller which schedules the bus cycles on the basis of priority with two state machines (one to control the bus cycles for operated accesses and the other to control the bus cycles for instruction accesses), and the instruction cache with its associated control.
TS68020
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TS68020
The micromachine consists of an execution unit, nanorom and microrom storage, an instruction decoder, an instruction pipe, and associated control sections. The execution unit consists of an address section, an operand address section, and a data section. Microcode control is provided by a modified two-level store of microrom and nanorom. Programmed logical arrays (PLAs) are used to provide instruction decode and sequencing information. The instruction pipe and other individual control sections provide the secondary decode of instructions and generated the actual control signals that result in the decoding and interpretation of nanorom and micorom information. Figure 2. PGA Terminal Designation
Figure 3. CQFP Terminal Designation
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Figure 4. Functional Signal Groups
Signal Description
Figure 4 illustrates the functional signal groups and Table 1 lists the signals and their function. The VCC and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other output buffers and internal logic.
Group Address Bus Data Bus Logic Clock
VCC A9, D3 M8, N8, N13 D1, D2, E3, G11, G13 -
GND A10, B9, C3, F12 L7, L11, N7, K3 G12, H13, J3, K1 B1
TS68020
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TS68020
Table 1. Signal Index
Read-Modify-Write Cycle External Cycle Start Operand Cycle Start Address Strobe Data Strobe Read / Write Data Buffer Enable Data Transfer and Size Acknowledge Cache Disable Interrupt Priority Level Autovector Interrupt Pending Bus Request Bus Grant Bus Grant Acknowledge Reset Halt Bus Error Clock Power Supply Ground
RMC ECS OCS AS DS R / W DBEN DSACK0 / DSACK1
CDIS IPL0-IPL2 AVEC IPEND BR BG BGACK RESET HALT BERR CLK VCC GND
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Detailed Specifications Scope Applicable Documents
MIL-STD-883
· · · MIL-STD-883: Test Methods and Procedures for Electronics MIL-PRF-38535 appendix A: General Specifications for Microcircuits Desc Drawing 5962 - 860320xxx This drawing describes the specific requirements for the microprocessor 68020, 16.67 MHz, 20 MHz and 25 MHz, in compliance with the MIL-STD-883 class B.
Requirements
General Design and Construction
Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure 3. Lead material and finish shall be any option of MIL-STD-1835. The macrocircuits are packages in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-1835 (when defined): · · 114-pin SQ.PGA UP PAE Outline 132-pin Ceramic Quad Flat Pack CQFP The microcircuits are in accordance with the applicable document and as specified herein.
Lead Material and Finish Package
The precise case outlines are described on Figure 23 and Figure 24.
TS68020
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TS68020
Electrical Characteristics
Table 2. Absolute Maximum Ratings
Table 3. Recommended Condition of Use Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1).
Symbol VCC VIL VIH Tcase RL CL Parameter Supply Voltage Low Level Input Voltage High Level Input Voltage Operating Temperature Value of Output Load Resistance Output Loading Capacitance 68020-16 tr(c)-tf(c) Clock Rise Time (See Figure 5) 68020-20 68020-25 68020-16 fc Clock Frequency (See Figure 5) 68020-20 68020-25 68020-16 tcyc Cycle Time (see Figure 5) 68020-20 68020-25 68020-16 tW(CL) Clock Pulse Width Low (See Figure 5) 68020-20 68020-25 68020-16 tW(CH) Note: Clock Pulse Width High (See Figure 5) 68020-20 8 12.5 12.5 60 50 40 24 20 19 24 20 Min 4.5 -0.3 2.4 -55
Max 5.5 0.5 5.25 +125
5 5 4 16.67 20 25 125 80 80 95 54 61 95 50 61 ns ns ns MHz ns
68020-25 19 1. Load network number 1 to 4 as specified (Table 7) gives the maximum loading of the relevant output.
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This device contains protective circuitry against damage due to high static voltages or electrical fields however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Figure 5. Clock Input Timing Diagram
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
Table 4. Thermal Characteristics at 25°C
Package PGA 114 Symbol JA JC JA JC Parameter Thermal Resistance - Ceramic Junction to Ambient Thermal Resistance - Ceramic Junction to Case Thermal Resistance - Ceramic Junction to Ambient Thermal Resistance - Ceramic Junction to Case Value 26 5 34 2 Unit
CQFP 132
Power Considerations
where K is a constant pertaining to the particular part K can be determined from equation (3) by measuring P D (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iterativley for any value of TA.
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TS68020
JC is device related and cannot be influenced by the user. However, CA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce CA so that JA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature.
Mechanical and Environment Marking
Quality Conformance Inspection
DESC / MIL-STD-883
Is in accordance with MIL-M-38510 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot. Group C and D inspections are performed on a periodical basis.
Electrical Characteristics
General Requirements
All static and dynamic electrical characteristics specified and the relevant measurement conditions are given below. (last issue on request to our marketing services). Table 5: Static electrical characteristics for all electrical variants. Table 6: Dynamic electrical characteristics for 68020-16 (16.67 MHz), 68020-20 (20 MHz) and 68020-25 (25 MHz). For static characteristics, test methods refer to "Test Conditions Specific to the Device" on page 14 hereafter of this specification (Table 7).
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For dynamic characteristics (Table 6), test methods refer to IEC 748-2 method, where existing. Indication of "min." or "max." in the column "test temperature" means minimum or maximum operating temperature.
TS68020
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TS68020
Dynamic (Switching) Characteristics
Table 6. Dynamic Electrical Characteristics
Interval Number 2, 3 6 6A 7 8 9 9A 10 10A 10B 11 12 12A 13 14 14A 15 15A 16 17 18 20 21 22 23 25 25A 15 15 15 0 0 15 75 30 10 10 30 30 68020-16 Min 24 0 0 0 0 3 -15 20 20 15 15 0 0 15 100 40 40 35 60 10 0 0 10 60 25 5 5 25 25 30 30 30 15 Max 95 30 20 60 68020-20 Min 20 0 0 0 0 3 -10 15 15 10 10 0 0 10 85 38 38 30 50 10 0 0 5 50 25 20 20 25 25 25 10 Max 54 25 15 50 68020-25 Min 19 0 0 0 0 3 -10 15 15 5 6 0 0 10 70 30 30 25 40 15 15 18 10 Max 61 25 12 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tCPW tCHAV tCHEV tCHAZX tCHAZn tCLSA tSTSA tECSA tOCSA tEOCSN tAVSA tCLSN tCLEN tSNAI tSWA tSWAW tSN tSNSA tCSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tSNDI tDNDBN
Parameter Clock Pulse Width Clock High to Address / FC / Size / RMC Valid Clock High to ECS, OCS Asserted Clock High to Address / Data / FC / RMC / Size High Impedance Clock High to Address / FC / Size / RMC Invalid Clock Low to AS, DS Asserted AS to DS Assertion (Read)(Skew) ECS Width Asserted OCS Width Asserted ECS, OCS Width Negated Address / FC / Size / RMC Valid to AS Asserted (and DS Asserted, Read) Clock Low to AS, DS Negated Clock Low to ECS / OCS Negated AS, DS Negated to Address / FC / Size / RMC Invalid AS (and DS, Read) Width Asserted DS Width Asserted, Write AS, DS Width Negated DS Negated to AS Asserted Clock High to AS / DS / R / W / DBEN High Impedance AS, DS Negated to R / W High Clock High to R / W High Clock High to R / W Low R / W High to AS Asserted R / W Low to DS Asserted (Write) Clock High to Data Out Valid AS, DS Negated to Data Out Valid DS Negated to DBEN Negated (Write)
Notes
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Table 6. Dynamic Electrical Characteristics (Continued)
Interval Number 26 27 27A 28 29 29A 31 31A 32 33 34 35 37 37A 39 39A 40 41 42 43 44 45 60 120 46 47A 47B 48 53 0 0 150 5 15 30 0 0 50 100 125 5 15 20 0 0 40 80 100 5 10 18 ns ns ns ns ns ns ns ns
68020-16 Min 15 5 20 0 0 60 50 15 1.5 0 0 1.5 1.5 0 90 90 0 0 0 0 15 30 30 30 30 30 30 3.5 3.5 1.5 80 Max
68020-20 Min 10 5 15 0 0 50 43 10 1.5 0 0 1.5 1.5 0 75 75 0 0 0 0 10 25 25 25 25 25 25 3.5 3.5 1.5 65 Max
68020-25 Min 5 5 10 0 0 40 32 10 1.5 0 0 1.5 1.5 0 60 60 0 0 0 0 10 20 20 20 20 20 20 3.5 3.5 1.5 ns Clks ns ns Clks Clks Clks ns ns ns ns ns ns ns
Symbol tDVSA tDICL tBELCL tSNDN tSNDI tSNDIZ tDADI tDADV tHRrf tCLBA tCLBN tBRAGA tGAGN tGABRN tGN tGA tCHDAR tCLDNR tCLDAW tCHDNW tRADA tDA
Parameter Data Out Valid to DS Asserted (Write) 26 Data in Valid to Clock Low (Data Setup) Late BERR / HALT Asserted to Clock Low Setup Time AS, DS Negated to DSACKx / BERR / HALT / AVEC Negated DS Negated to Data On Invalid (Data in Hold Time) DS Negated to Data in High Impedance DSACKx Asserted to Data In Valid DSACK Asserted to DSACKx Valid (DSACK Asserted Skew) RESET Input Transition Time Clock Low to BG Asserted Clock Low to BG Negated BR Asserted to BG Asserted (RMC Not Asserted) BGACK Asserted to BG Negated BGACK Asserted to BR Negated BG Width Negated BG Width Asserted Clock High to DBEN Asserted (Read) Clock Low to DBEN Negated (Read) Clock Low to DBEN Negated (Read) Clock High to DBEN Asserted (Read) R / W Low to DBEN Asserted (Write) DBEN Width Asserted READ WRITE R / W Width Asserted (Write or Read) Asynchronous Input Setup Time Asynchronous Input Hold Time DSACKx Asserted to BERR / HALT Asserted Data Out Hold from Clock High BERR Negated to HALT Negated (Rerun)
Unit ns ns ns
Notes
tRWA tAIST tAIHT tDABA tDOCH tBNHN
TS68020
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TS68020
Table 6. Dynamic Electrical Characteristics (Continued)
Interval Number 68020-16 Min 8.0 55 56 57 58 30 512 0 1 Max 16.67 68020-20 Min 12.5 25 512 0 1 Max 20.0 68020-25 Min 12.5 20 512 0 1 Clks ns Clks Max 25 Unit MHz
Symbol f tRADC tHRPW tBNHN tGANBD tGNBD Notes:
Parameter Frequency of Operation R / W Asserted to Data Bus Impedance Change RESET Pulse Width (Reset Instruction) BERR Negated to HALT Negated (Rerun) BGACK Negated to Bus Driven
Notes
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Test Conditions Specific to the Device
Loading Network The applicable loading network shall be defined in column "Test conditions" of Table 6, referring to the loading network number as shown in Figure 6, Figure 7, Figure 8 below. Figure 6. RESET Test Loads
Figure 7. HALT Test Load
Figure 8. Test Load
Table 7. Load Network
Load NBR 1 2 3 Note: Figure 7 7 R 2k 1.22 k RL 6.0 k 6.0 k CL 50 pF 130 pF Output Application OCS, ECS A0-A31, D0-D31, BG, FC0-FC2, SIZ0-SIZ1 AS, DS, R / W, RMC, DBEN, IPEND
7 0.74 k 6.0 k 130 pF 1. Equivalent loading may be simulated by the tester.
TS68020
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TS68020
Time Definitions The times specified in Table 6 as dynamic characteristics are defined in Figure 9 below, by a reference number given the column "interval N°" of the tables together with the relevant figure number.
Figure 9. Read Cycle Timing Diagram
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
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Figure 10. Write Cycle Timing Diagram (Continued)
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing thorough this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
TS68020
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TS68020
Figure 11. Bus Arbitration Timing Diagram
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing thorough this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V.
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Input and Output Signals for Dynamic Measurements AC Electrical Specifications Definitions The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the TS68020 clock input and, possibly, relative to one or more other signals. The measurement of the AC specifications is defined by the waveforms in Figure 12. In order to test the parameters guaranteed by Atmel, inputs must be driven to the voltage levels specified in Figure 12. Outputs of the TS68020 are specified with minimum and / or maximum limits, as appropriate, and are measured as shown. Inputs to the TS68020 are specified with minimum and, as appropriate, maximum setup and hold times, and are measurement as shown. Finally, the measurements for signal-to-signal specification are also shown. Note that the testing levels used to verify conformance of the TS68020 to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics.
TS68020
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TS68020
Figure 12. Drive Levels and Test Points for AC Specification
Legend: A) Maximum Output Delay Specification B) Minimum Output Hold Time C) Minimum Input Setup Time Specification D) Minimum Input Hold Time Specification E) Signal Valid to Signal Valid Specification (Maximum or Minimum) F) Signal Valid to Signal Invalid Specification (Maximum or Minimum)
Notes: 1. 2. 3. 4. 5. This output timing is applicable to all parameters specified relative to the rising edge of the clock. This out put timing is applicable to all parameters specified relative to the falling edge of the clock. This input timing is applicable to all parameters specified relative to the falling edge of the clock. This input timing is applicable to all parameters specified relative to the falling edge of the clock. This timing is applicable to all parameters specified relative to the assertion / negation of another signal.
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Additional Information
Power Consideration Capacitance (Not for Inspection Purposes
Additional information shall not be for any inspection purposes. See Table 4.
Symbol Cin
Parameter Input Capacitance
Min 20
Unit pF
Capacitance Derating Curves
Figure 13 to Figure 18 inclusive show the typical derating conditions which apply. The capacitance includes any stray capacitance. The graphs may not be linear outside the range shown. Figure 13. Address Capacitance Derating Curve
TS68020
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TS68020
Figure 14. ECS and OCS Capacitance Derating Curve
Figure 15. R / W, FC, SIZ0-SIZ1, and RMC Capacitance Derating Curve
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Figure 16. DS, AS, IPEND, and BG Capacitance Derating Curve
Figure 17. DBEN Capacitance Derating Curve
TS68020
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TS68020
Figure 18. Data Capacitance Derating Curve
Functional Description
Description of Registers
As shown in the programming models (Figure 19 and Figure 20) the TS68020 has sixteen 32-bit general-purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register, a 32-bit vector base register, two 3-bit alternate function code registers, and two 32-bit cache handling (address and control) registers. Registers D0-D7 are used as data registers for bit and bit field (1- to 32-bit), byte (8-bit), long word (32-bit), and quad word (64-bit) operations. Registers A0-A6 and the user, interrupt, and master stack pointers are address registers that may be used as software stack pointers or base address registers. In addition, the address registers may be used for word and long word operations. All of the 16 (D0-D7, A0-A7) registers may be used as index registers. The status register (Figure 21) contains the interrupt priority mask (three bits) as well as the condition codes: extend (X), negated (N), zero (Z), overflow (V), and carry (C). Additional control bits indicate that the processor is in the trace mode (T1 or T0), supervisor / user state (S), and master / interrupt state (M). All microprocessors of the TS68000 Family support instruction tracing (via the T0 status bit in the TS68020) where each instruction executed is followed by a trap to a userdefined trace routine. The TS68020 adds the capability to trace only the change of flow instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit. These features are important for software program development and debug. The vector base register is used to determine the runtime location of the exception vector table in memory, hence it supports multiple vector tables so each process or task can properly manage exceptions independent of each other.
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The TS68000 Family processors distinguish address spaces as supervisor / used and program / data. These four combinations are specified by the function code pins (FC0 / FC1 / FC2) during bus cycles, indication the particular address space. Using the function codes, the memory sub-system can distinguish between authorized access (supervisor mode is privileged access) and unauthorized access (user mode may not have access to supervisor program or data areas). To support the full privileges of the supervisor, the alternate function code registers allow the supervisor to specify an access to user program or data a re as by prelo ading the SFC / DFC registers appropriately. The cache registers (control - CACR, address - CAAR) allow software manipulation of the on-chip instruction cache. Control and status accesses to the instruction cache are provided by the cache control register (CACR), while the cache address register (CAAR) holds the address for those cache control functions that require an address. Figure 19. User Programming Model
TS68020
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TS68020
Figure 20. Supervisor Programming Model Supplement
Figure 21. Status Register
Data Types and Addressing Modes
Seven basic types are supported. These data types are: · · · · · · · Bits Bits Flieds (String of consecutive bits, 1-32 bits long) BCD Digits (Packed: 2 digits / byte, Unpacked: 1 digit / byte) Byte Integers (8-bit) Word Integers (16-bit) Long Word Integers (32-bit) Quad Word Integers (64-bit)
In addition, operations on other data types, such as memory addresses, status word data, etc.., are provided in the instruction set. The co-processor mechanism allows direct support of floating-point data type with the TS68881 and TS68882 floating-point co-processors, as well as specialized user-defined data types and functions.
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The 18 addressing modes, shown in Table 8, include nine basic types: · · · · · · · · · Register Direct Register Indirect Register Indirect with Index Memory Indirect Program Counter Indirect with Displacement Program Counter Indirect with Index Program Counter Memory Indirect Absolute Immediate
The register indirect addressing modes support postincrement, predecrement, offset, and indexing. Programmers find these capabilities particularly useful for handling advanced data structures common to sophisticated applications and high level languages. The program counter relative mode also has index and offset capabilities programmers find that this addressing mode is required to support position-independent software. In addition to these addressing modes, the TS68020 provides data operand sizing and scaling these features provide performance enhancements to the programmer.
Table 8. TS68020 Addressing Modes
Addressing Modes Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Post Increment Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Post-Indexed Memory Indirect Pre-Indexed Program Counter Indirect with Displacement Program Counter Indirect with Index PC Indirect with Index (8-bit Displacement) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Post-Indexed PC Memory Indirect Pre-Indexed Syntax Dn An (An) (An) + - (An) (d16An) (d8, An, Xn) (bd, An, Xn) (bd, An, Xn, od) (bd, An, Xn, od) (d16, PC) (d8, PC, Xn) (bd, PC, Xn) (bd, PC, Xn, od) (bd, PC, Xn), od)
TS68020
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TS68020
Table 8. TS68020 Addressing Modes (Continued)
Addressing Modes Absolute Absolute Short Absolute Long Syntax xxx.W xxx.L
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Instruction Set Overview
Mnemonic ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST Description Add Decimal with Extend Add Add Address Add Immediate Add Quick Add with Extend Logical AND Logical AND Immediate Arithmetic Shift Left and Right Branch Conditionally Test Bit and Change Test Bit and Clear Test Bit Field and Change Test Bit Field and Clear Signed Bit Field Extract Unsigned Bit Field Extract Bit Field Find First One Bit Field Insert Test Bit Field and Set Test Bit Field Breakpoint Branch Test Bit and Set Branch to Subroutine Test Bit
TS68020
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TS68020
Table 9. Instruction Set (Continued)
Mnemonic CALLM CAS CAS2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LSL, LSR MOVE MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEG NEGX NOP NOT Description Call Module Compare and Swap Operands Compare and Swap Dual Operands Check Register Against Bound Check Register Against Upper and Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory to Memory Compare Register Against Upper and Lower Bounds
Test Condition, Decrement and Branch Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Tape Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Left and Right Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement
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Table 9. Instruction Set (Continued)
Mnemonic OR ORI PACK PEA RESET ROL, ROR ROXL, ROXR RTD RTE R RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK Co-processor Instructions cpBCC cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc Branch Conditionally Test Co-processor Condition, Decrement and Branch Co-processor General Instruction Restore Internal State of Co-processor Save Internal State of Co-processor Set Conditionally Trap Conditionally Description Logical Inclusive OR Logical Inclusive OR Immediate Pack BCD Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return and Exception Return from Module Return and Restore Codes Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand Unlink Unpack BCD
TS68020
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TS68020
Binary Coded Decimal (BCD) Support
Bounds Checking
System Traps
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Multi-processing
Module Support
The TS68020 includes support for modules with the call module (CALLM) and return from module (RTM) instructions. The CALLM instruction references a module descriptor. This descriptor contains control information for entry into the associated module. The CALLM instruction creates a module stack frame and stores the module state in that frame. The R instruction recovers the previous module state from the stack frame and returns to the calling module. The module interface also provides a mechanism for finer resolution of access control by external hardware. Although the TS68020 does not interrupt the access control information, it does communicate with external hardware when the access control is to be changed, and relies on the external hardware to verify that the changes are legal. CALLM and RTM, when used as subroutine calls and returns with proper descriptor formats, cause the TS68020 to perform the necessary actions to verify legitimate access to modules.
Virtual Memory / Machine Concepts
The full addressing range of the TS68020 is 4-Gbyte (4, 294, 967, 296). However, most TS68020 systems implement a smaller physical memory. Nonetheless, by using virtual memory techniques, the system can be made to appear to have a full 4-Gbyte of physical memory available to each user program. These techniques have been used for many years in large mainframe computers and minicomputers. With the TS68020 (as with the TS68010 and TS68012), virtual memory can be fully supported in microprocessor-based systems. In a virtual memory system, a user program can be written as though it has a large amount of memory available to it when actually only a smaller amount of memory is physically present in the system. In a similar fashion, a system provides user programs access to other devices that are not physically present in the system, such as tape drives, disk drives, printers, or terminals. With proper software emulation, a physical system can be made to appear to a user program as any other 68000 computer system and the program may be given full access to all of the resources of that emulated system. Such an emulator system is called a virtual machine.
Virtual Memory
The basic mechanism for supporting virtual memory is to provides a limited amount of high-speed physical memory that can be accessed directly by the processor while maintaining of a much larger "virtual" memory on secondary storage devices such as large capacity disk drives. When the processor attempts to access a location in the virtual memory map that is not resident in the physical memory (referred to as a page fault), the access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory the suspended access is then either restarted or continued.
TS68020
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TS68020
Operand Transfer Mechanism
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The TS68020 will always transfer the maximum amount of data on all bus cycles i.e., it always assumes the port is 32-bit wide when beginning the bus cycle. In addition, the TS68020 has no restrictions concerning alignment of operands in memory long word operands need not be aligned on long word address boundaries. When misaligned data requires multiple bus cycles, the TS68020 aligned data requires multiple bus cycles, the TS68020 automatically runs the minimum number of bus cycles.
The Co-processor Concept
TS68020
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TS68020
Register Response Control Save Restore Operation Word Command Word Condition Word Operand Register Select Instruction Address Operand Address Function Requests Action from CPU CPU Initiate Save of Internal State Initiate Restore of Internal State Current Co-processor Instruction Co-processor Specific Command Condition to be Evaluated 32-bit Operand Specifies CPU Register or Mask Pointer to Co-processor Instruction Pointer to Co-processor Operand R / W R W R R / W W W W R / W R R / W R / W
Table 11. Co-processor Primitives
Processor Synchronization Busy with Current Instruction Proceed with Next Instruction, If No Trace Service Interrupts and Re-query, If Trace Enable Proceed with Execution, Condition True / False Instruction Manipulation Transfer Operation Word Transfer Words from Instruction Stream Exception Handling Take Privilege Violation if S Bit Not Set Take Pre-Instruction Exception Take Mid-Instruction Exception Take Post-Instruction Exception
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Table 11. Co-processor Primitives (Continued)
General Operand Transfer Evaluate and Pass (Ea.) Evaluate (Ea.) and Transfer Data Write to Previously Evaluated (Ea.) Take Address and Transfer Data Transfer to / from Top of Stack Register Transfer Transfer CPU Register Transfer CPU Control Register Transfer Multiple CPU Registers Transfer Multiple Co-processor Registers Transfer CPU SR and / or ScanPC
Up to eight processors are supported in a single system with a system-unique co-processor identifier encoded in the co-processor instruction. When accessing a coprocessor, the TS68020 executes standard read and write bus cycle in CPU address space, as encoded by the function codes, and places the co-processor identifier on the address bus to be used by chip-select logic to select the particular co-processor. Since standard bus cycle are used to access the co-processor, the co-processor may be located according to system design requirements, whether it be located on the microprocessor local bus, on another board on the system bus, or any other place where the chip-select and co-processor protocol using standard TS68000 bus cycles can be supported. Co-processor Protocol Interprocessor transfers are all initiated by the main processor during co-processor instruction execution. During the processing of a co-processor instruction, the main processor transfers instruction information and data to the associated co-processor, and receives data, requests, and status information from the co-processor. These transfers are all based on the TS68000 bus cycles. The typical co-processor protocol which the main processor follows is: a) The main processor initiates the communications by writing command information to a location in the co-processor interface. b) The main processor reads the co-processor response to that information. 1) The response may indicate that the co-processor is busy, and the main processor should again query the co-processor. This allows the main processor and co-processor to synchronize their concurrent operations. 2) The response may indicate some exception condition the main processor acknowledges the exception and begins exception processing. 3) The response may indicate that the co-processor needs the main processor to perform some service such as transferring data to or from the co-processor. The coprocessor may also request that the main processor query the co-processor again after the service is complete. 4) The response may indicate that the main processor is not needed for further processing of the instruction. The communication is terminated, and the main processor is free to begin execution of the next instruction. At this point in the coprocessor protocol, as the main processor continues to execute the instruction stream, the main processor may operate concurrently with the co-processor.
TS68020
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TS68020
When the main processor encounters the next co-processor instruction, the main processor queries the co-processor until the co-processor is ready meanwhile, the main processor can go on to service interrupts and do a context switch to execute other tasks, for example. Each co-processor instruction type has specific requirements based on this simplified protocol. The co-processor interface may use as many extension words as requires to implement a co-processor instruction. Primitives / Response The response register is the means by which the co-processor communicates service requests to the main processor. The content of the co-processor response register is a primitive instruction to the main processor which is read during co-processor communication by the main processor. The main processor "executes" this primitive, thereby providing the services requires by the co-processor. Table 11 summarizes the co-processor primitives that the TS68020 accepts.
Exceptions
Kinds of Exceptions Exception can be generated by either internal or external causes. The externally generated exceptions are the interrupts, the bus error, and reset requests. The interrupts are requests from peripheral devices for processor action while the bus error and reset pins are used for access control and processor restart. The internally generated exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, and DIV instructions can all generate exceptions as part of their execution. Tracing behaves like a very high priority, internally generated interrupt whenever it is processed. The other internally generated exceptions are caused by illegal instructions, instruction fetches from odd addresses, and privilege violations. Exception processing occurs in four steps. During the first step, an internal copy is made of the status register. After the copy is made, the special processor state bits in the status register are changed. The S bit is set, putting the processor into supervisor privilege state. Also, the T1 and T0 bits are negated, allowing the exception handler to execute unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is also updated. In the second step, the vector number of the exception is determined. For interrupts, the vector number is obtained by a processor read that is classified as an interrupt acknowledge cycle. For co-processor detected exceptions, the victor number is included in the co-processor exception primitive response. For all other exceptions, internal logic provides the vector number. This vector number is then used to generate the address of the exception vector. The third step is to save the current processor status. The exception stack frame is created and filled on the supervisor stack. In order to minimize the amount of machine state that is saved, various stack frame sizes are used to contain the processor state depending on the type of exception and where it occurred during instruction execution. If the exception is an interrupt and the M bit is on, the M bit is forced off, and a short four word exception stack frame is saved on the master stack which indicates that the exception is saved on the interrupt stack. If the exception is a reset, the M bit is simply forced off, and the reset vector is accessed.
Exception Processing Sequence
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On-chip Instruction Cache
TS68020 Cache Goals
TS68020
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TS68020
Second, and probably the most important benefit of the cache, is that it allows instruction stream fetches and operand accesses to proceed in parallel. For example, if the TS68020 requires both an instruction stream access and an operand access, and the instruction is resident in the cache, the operand access will proceed unimpeded rather than being queued behind the instruction fetch. Similarly, the TS68020 is fully capable of executing several internal instructions (instructions that do not require the bus) while completing an operand access for another instruction. The TS68020 instruction cache is a 256-byte direct mapped cache organized as 64 long word entries. Each cache entry consists of a tag field made up of the upper 24 address bits, the FC2 (user / supervisor) value, one valid bit, and 32-bit of instruction data (Figure 22). Figure 22. TS68020 On-chip Cache Organization
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Preparation for Delivery
Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance with MIL-STD-883 and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range.
Handling
TS68020
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TS68020
Package Mechanical Data
Figure 23. 114-lead - Ceramic Pin Grid Array
Figure 24. 132 Pins - Ceramic Quad Flat Pack
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PGA 114 - 6 grams typically CQFP 132 - 14 grams typically
Terminal Connections
114-lead - Ceramic Pin Grid Array 132-lead - Ceramic Quad Flat Pack
See Figure 2.
See Figure 3.
TS68020
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TS68020
Ordering Information
Hi-REL Product
Commercial Atmel Part-Number TS68020MRB / C16 TS68020MR1B / C16 TS68020MRB / C20 TS68020MR1B / C20 TS68020MRB / C25 TS68020MR1B / C25 TS68020MFB / C16 TS68020MF1B / C16 TS68020MFB / C20 TS68020MF1B / C20 TS68020MFB / C25 TS68020MF1B / C25 TS68020DESC02XA TS68020DESC03XA TS68020DESC04XA TS68020DESC02XC TS68020DESC03XC TS68020DESC04XC TS68020DESC02YA TS68020DESC03YA TS68020DESC04YA TS68020DESC02YC TS68020DESC03YC TS68020DESC04YC Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC Package PGA 114 PGA 114 / tin PGA 114 PGA 114 / tin PGA 114 PGA 114 / tin CQFP 132 CQFP 132 / tin CQFP 132 CQFP 132 / tin CQFP 132 CQFP 132 / tin PGA 114 / tin PGA 114 / tin PGA 114 / tin PGA 114 PGA 114 PGA 114 CQFP 132 / tin CQFP 132 / tin CQFP 132 / tin CQFP 132 CQFP 132 CQFP 132 Temperature Range Tc (°C) -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 -55 / +125 Frequency (MHz) 16.67 16.67 20 20 25 25 16.67 16.67 20 20 25 25 16.67 20 25 16.67 20 25 16.67 20 25 16.67 20 25 Drawing Number 5962-8603202XA 5962-8603203XA 5962-8603204XA 5962-8603202XC 5962-8603203XC 5962-8603204XC 5962-8603202YA 5962-8603203YA 5962-8603204YA 5962-8603202YC 5962-8603203YC 5962-8603204YC
Standard Product
Commercial Atmel Part-Number TS68020VR16 TS68020VR20 TS68020VR25 TS68020MR16 TS68020MR20 TS68020MR25 Norms Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Package PGA 114 PGA 114 PGA 114 PGA 114 PGA 114 PGA 114 Temperature Range Tc (°C) -40 / +85 -40 / +85 -40 / +85 -55 / +125 -55 / +125 -55 / +125 Frequency (MHz) 16.67 20 25 16.67 20 25 Drawing Number Internal Internal Internal Internal Internal Internal
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Standard Product
Commercial Atmel Part-Number TS68020VF16 TS68020VF120 TS68020VF25 TS68020MF16 TS68020MF20 TS68020MF25 Norms Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Internal Standard Package CQFP 132 CQFP 132 CQFP 132 CQFP 132 CQFP 132 CQFP 132 Temperature Range Tc (°C) -40 / +85 -40 / +85 -40 / +85 -55 / +125 -55 / +125 -55 / +125 Frequency (MHz) 16.67 20 25 16.67 20 25 Drawing Number Internal Internal Internal Internal Internal Internal
TS68020
20 Speed (MHz)
Device Type Temperature range M: -55, +125°C V: -40, +85
Note:
For availability of the different versions, contact your Atmel sales office.
TS68020
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