There critical issues metastability characterization. devise accurate

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

There critical issues metastability characterization. devise accurate

Datasheet Thumbnail

Top Searches for this datasheet

Metastability Lattice Devices
There critical issues metastability characterization. devise accurate practical measurement technique other basic knowledge metastability. measurement procedure requires comprehensive knowledge metastability. actual applications, user deviate from meeting ideal register setup hold times. When data clock satisfy setup hold times, logic state flip-flop becomes unpredictable. measurable symptom problem increased clock-to-out time. susceptibility circuit reach this metastable state described using probabilistic equation. This technical note describes basics metastability, measurement methods equations necessary arrive device characteristics Lattice Programmable Logic Devices (PLDs). sample device from each family used summarize data. assumed that devices within each family have similar characteristics.
Basics Metastability
Refer single-stage Flip-Flop shown Figure Figure Single-Stage Synchronizer
METASTABILITY RESOLUTION TIME
CLOCK
Asynchronous Data Clock
Synchronous Data
DATA
Decision Window Output Metastable
CO_max
Resolution time available following metastable event CO_max Maximum Clock Output Delay Data Setup Time Data Hold Time
Minimum data set-up (tSU) hold (tHD) times must register output synchronized data. data input flip-flop asynchronous clock. arrival time input data relative clock known "danger zone" created. transition correct input data could enter Decision Window illustrated Figure After clock-to-output delay (tCO), input data appears output. input data enters "danger zone", output likely metastable state until internal silicon settles either logic high low. extra time required resolve logic state called resolution time (tR) Decision Window represented Metastability Window (W).
www.latticesemi.com
tn1055_01
Lattice Semiconductor
Metastability Lattice Devices
Solution Metastability
flip-flops series best known easiest solution avoid metastability. resolution time varies exponentially with size Metastability Window. other words, data barely missed set-up/hold time requirement, flip-flop decision will take slightly longer than tCO. When data arrives middle Metastability Window, resolution time will much longer. Figure Flip-Flop Solution
Asynchronous Data Q1_Out Clock Q2_Out
When input data transition falls within Metastability Window FF1, causes longer resolution time output Q1_Out. When resolved Q1_Out arrives FF2, probability that signal transition will fall Metastability Window data input very low. practical circuit, cascading flip-flops essentially squares probability failure.
Measurement Method
Devising reliable repeatable measurement methods challenging. wealth information been published about metastability characterization these techniques have proven difficult recreate reliably. report Foley[1] describes measurement technique that reliable repeatable. measured data resolution accurate test equipment resolution. data used this technical note derived using Foley's technique. This method does require additional external active circuitry other than test equipment.
Derivation Equations
Available Resolve Time
Assume that output will sampled next clock event, output must resolved prior next clock set-up time. maximum available resolution time given clock frequency, tSU) where: Clock frequency Maximum clock-to-output delay Minimum set-up time shown Figure time where output given recover legal logic level after before set-up time next clock. Figure Available Resolution Time
Clock
Lattice Semiconductor Resolving Time Constant
Metastability Lattice Devices
Resolving Time Constant, comes from expression that describes probability metastable event lasting longer than some time, This probability expressed e-t/
method uses stable synchronous source measurement. set-up hold times input data relative clock adjusted while observing output metastable event. output appears have equally distributed high logic levels.
Metastability Window
Metastability Window, determined accurately measuring Clock-To-Output Propagation Delay Time (tCO) with variation Set-up (tSU) Hold (tHD) times. Figure shows versus tSU/tHD curves. When Set-up time Hold time violated, Clock-To-Output Delay increased. tCO_MAX specified device data sheet. When measured longer than tCO_MAX, device considered metastable state. Figure Metastability Window
tCO_max tCO_norm
Clock
Assume data arrives uniformly over clock cycle probability that data will arrive clock period where: Metastability window Clock frequency data rate then data will arrive data rate rate metastability becomes: where data rate. probability metastable event lasting longer than some time, from Equation e-tr/ (etr/) Failure rate Metastability Rate Probability Metastability. e-tr/
Lattice Semiconductor Mean Time Between Failures (MTBF)
Metastability Lattice Devices
Metastability Failure Rate defined susceptibility flip-flop reach metastable state designated time following clock. phrase designated time following clock" understanding data correctly. This failure rate often converted Mean Time Between Failure (MTBF). MTBF Metastability Failure Rate MTBF Failure Rate e-tr/) etr// where: Clock frequency Data rate (not data frequency) Metastability window Resolve time available Resolving time constant Note: measured frequency meter, data changes twice cycle. this case, must replaced above equation. graphical representation data been represented semi-log graph. Converting exponential expression decades form, etr/ 10tr/ where: log(e) Equation becomes: MTBF 10tr/
Test Set-up
Using signal generator shown Figure set-up hold time varied relative clock. scope displays output waveform while adjusting data clock relative timing. Metastability Window starts when data enters Metastable Window ends data escapes Metastable Window. resolution signal generator only sizable limitation accuracy measurement. practice, limitation does count much importance accuracy data. After Metastability Window measured, data timing center window observe decay function resolution time, Figure Test Set-up
Clock Data Output
Tektronix HFS9003 Trigger
Tektronix 11801B Trigger
Signal Generator
Digitizing Oscilloscope
Mask Counting
logic level plots accumulated scope screen shown Figure decay this metastable behavior over time observed expected.
Lattice Semiconductor
Figure Masks Used Overlaid Output
Metastability Lattice Devices
11801B digital oscilloscope used event counter zones (masks). bottom each mask VOH_MIN VOL_MAX device, respectively. width each mask represents time unit comparing events different times. tallies these masks reveal population decay rate expressed Equation number masks should chosen that enough decay rate observed. Table represents actual measurements taken ispMACH4000 device. Eight masks used. population column numbers actual illegal event counts. Table Example Data
Mask Population 5.10E+03 2.66E+03 1.21E+03 4.50E+02 1.29E+02 3.20E+01 9.00E+00 4.00E+00
Lattice Semiconductor Exponential Decay Failure
Figure Exponential Decay Failure
6000 5000 4000 3000 2000 1000
Metastability Lattice Devices
Figure chart plotted semi-log scale. Figure Semi-log Scale Chart
1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
calculation purposes, column style chart converted line style Figure 9.In this plot, each mask represented time unit. straight line with data points approximation actual data calculation.
Lattice Semiconductor
Measurement Example Figure Plot Metastability Decay versus Time
1.00E+05
Metastability Lattice Devices
1.00E+04 1.00E+03
1.00E+02 1.00E+01
1.00E+00
DUT: LC4128C-27T100C (Data rate, data frequency measured clock frequency) measurement, tco_max_begin: 12.880, tco_max_end, 12.910, 12.910 12.880 0.30 3E-11 Mask size (ps) 1E-10 Total mask span 1.6V 0.2V From exponential decay function derive slope curve: log(b2) log(b1)] (mask size total mask span) [log(7.08E+03) (1E-10 8.3) -4638554210 2.156E-10 (11)
(10)
Note: slope (-1/ calculated natural logarithm [ln(b2) ln(b1)], Equation will produce same result. Now, available resolution time test set-up from Equation tco_max tsu_min) (4.0E+07) (2.7E-09) (2.0E-09) (2.03E-08) where tco_max 2.7E-08 tsu_min 2.0E-08 (from data sheet) (12)
Lattice Semiconductor
From Equation MTBF 10tr/ Substitution values results:
Metastability Lattice Devices
(13)
MTBF 1.81E+88 seconds 5.76E+80 years, which almost forever
Summary Metastability Characteristics
Metastability dependent device technology. constants, fixed each device with same speed grade. exponential nature MTBF formula extremely sensitive small changes
Table Metastability Data Lattice Devices
Part Number ispLSI 2128VE-100LT100 ispLSI 5256VE-125LT100 ispLSI 5384VA-125LQ208 LFX1200C-03F900C LX256B-35F484 M4A3-128/64-10VC ORT82G5-3BM680C (ps) Max. Available (ns) 38.5 10.5 15.0 11.6 13.5 19.2 (ps) (MHz) (MHz) (ns) Year MTBF1 6.43 5.15 5.46 1.44 1.06 1.59 1.48
Assumes that other parameters same test conditions with maximum available specified table. arbitrarily chosen measurement.
References
Clark Foley, "Characterizing Metastability," 1996 IEEE Howard Johnson, "High-Speed Digital Design," 1993, pp120-131. Ginosar, "VLSI Lecture Synchronization(I)", 2003 K.U. Leuven, "Fault-Tolerant Computing" 2000 ESAT/ACCA
Technical Support Assistance
Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com

There critical issues metastability characterization. devise accurate

Top Searches for this datasheet

Other recent searches