Morihiro Kada Abstract three-dimensional chip-stacked CSP, which

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Morihiro Kada Abstract three-dimensional chip-stacked CSP, which

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Dawn Packaging System-in-Package (SIP)
Morihiro Kada
Abstract three-dimensional chip-stacked CSP, which started with flash/SRAM combination memory cellular phones, forerunner from which system packages realize full-scale capability. future, package technology will savior achieving greater shrink silicon processes whose limits have come into sight. SIP, will surpass SOC, and, core technology electronic equipment high-speed digital network society, expected lead into first period 21st century. Today, seeing signs this transition. Keyword: package, SIP, CSP, Stacked CSP, Cellular phone Introduction curtain opened 21st century, time onto which people have often projected their dreams future. world information communications, that dream fast becoming reality. half century's time since invention transistor computer, this become possible. development internet last years been astonishing. Today, people transcend time distance barriers, communicate with world time, anywhere. Broadband digital communication technology expected develop rapidly future, will bring even greater changes daily life. There doubt that digital information network society will leader first years 21st century. Last year, when witnessed transition 21st century, there historical event Japan. stationary telephone system, which built over years, gave leading role explosive growth cellular phones. fact, Japan cellular phones first became practical 1979 cellular phones, this achievement only took about twenty years. Cellular phones their capabilities rapidly expanding. They have functions appropriate being referred mere "telephone", with W-CDMA system (IMT-2000), service scheduled begin this year, possible achieve high-speed communication maximum Mbits second, this will enable transmit receive moving pictures. This speed about times that current system, exceeds thirty times speed ISDN. With optical fiber cable, service Mbits/sec begun, services exceeding Mbits planned. What supports this high-speed digital information network society electronic information equipment, there doubt that silicon forms core that equipment. history silicon industry been history process shrink. This progressed steadily, through baptism silicon cycle, accordance with Moore's Law. Such progression been smooth, enabling response entire range needs, including cost, higher integration, higher speed power consumption. However, process shrink micron level, have begun technical barriers. These various, manifest terms design technology, cost characteristics. have begun look technology overcome those barriers. example, said that when process reaches microns less, mask setting cost becomes extremely high, model produced extremely high volume, cost effective. Various technologies have been proposed future, including DNA, molecular quantum computers, these will take some time reach practical level. what shall meantime? author believes that package technology solution. latter half 20th century, when silicon industry developed, package technology played just supporting role, subordinated chip. years ago, this began change. What created opportunity chip size package (CSP). Package technology began take center stage
technology which determined product value. next technology stacked pushed this development from behind. author only asserting that package technology will become ever more important future. Others charge package design have said same thing. Today, even those involved circuit design wafer processes have same opinion. package technology live expectations? this paper, would like discuss future package technologies meeting those expectations, while looking back history package development analyzing recent tendencies. History package technology development history package technology development roughly divided into following three periods Through-Hole mount Device (THD) (1970s) represented dual in-line package (DIP). functionality that high, with upper limit pins. Increased board mounting density that important requirement. packages could mounted inserting them into through-holes even with worker's fingers. rule, terminal pitch fixed (100 mil), package size increased together with number terminals. Package mounting density distributed over range about pins/cm2 max. This type package almost ended role 20th century. Surface Mount Device (SMD) (1980s) This SMD, represented small outline package (SOP) quad flat package (QFP). They enabled greater number pins high density mounting. This package which supported prosperous period Japanese semiconductor industry, Japan standardization. result, terminal pitches were switched metric system (1.0, 0.8, 0.65, 0.5, mm), shrinkage rule determined. These packages have different design concept than DIP. They employ concept where package designed with fixed package body size, terminal pitch varied necessary. This also improved productivity. maximum number terminals increased 300, mounting density increased pins/cm2.
This also golden metal lead frame type plastic package. Ball Grid Package (BGA)/Chip Size Package (CSP) (1990s) Japanese semiconductor industry, which held lead over America throughout 1980's, them ahead Japan 1990's. This period fact referred Japan "the lost 90's". Subsequently, 1990's package technology course realized America. Japan succeeded with QFP, then pursued them far. They polished their production technology, achieved high-density multi-pin packages, terminal pitches shrunk They figured they were sure out, long they superior Japanese packaging technology. America transferred manufacturing strength Southeast Asia search cost benefits, they chose easy production method which could used anywhere, rather than technology requiring high-precision. They widened terminal pitch, used package which terminals arranged bottom package body. main terminal pitches were 1.27 Expansion terminal pitch facilitated mounting technology improved productivity. problem that could connecting points become issue number mounting defects. mounting density about pins/cm2, these chips frequently used, mainly PCs. There differences composition products consumer equipment Japan, which watching this from side, applied concept reducing terminal pitch less, thereby inaugurating Era. This latter half 1990's. contributed reduction product size weight, improved competitiveness. representative electronic device this case cellular phone, this technology supported development cellular phone industry. 1996, mass production first started companies Japan. Originally, CSPs were used camcorder ICs, both base band control memory cellular phones. gradually shifted BGA/CSP starting middle 1990s. development competition improve industry allowed Japanese package industry again pull into
lead over America. this time, majority American semiconductor manufacturers longer have package development capability. Except some companies, because they have left package process production development subcontractors, mainly Southeast Asia. Japan Electronics Information Technology Industries Association (JEITA formerly EIAJ) JEDEC call this Fine pitch (FBGA). Mounting density exceed pins/cm2 There various definitions CSP, general generic term packages which same, slightly bigger than chip size." Dawn System-In-Package (SIP) (The 2000's) author predicts that next generation package will expressed change package form based mounting technology, been case past thirty years. package technology play leading role industry future, will have change rather than continue extend along line past. signs this change becoming evident. First, contributed reduction size weight cellular phones, having come into being driving force cellular phone development. success connected stacked CSP. Most cellular phone memory were designed both flash SRAM. Sharp, stacked these chips succeeded 1998) incorporating them into single CSP. called this combination memory. result promoting facto standardization, this memory used cellular phone manufacturers throughout world. 1999, Sharp successfully mass-produced 3-chip stacked CSP. This combination memory chips, could really called system However, author called this stacked system integration package (S2IP), proposed stacking logic memory chips, advocated superiority future potential this package. result, many semiconductor electronic equipment manufacturers stacked packages system package (SIP) consumer equipment, there rising awareness increased expectations this technology superior alternative system chip (SOC) applications. year 2000, various companies began propose package solutions system LSI,
thus indicating advent Era. Concurrently, industry/government system integration (SI) project started Energy Industrial Technology Development Organization (NEDO) 1999, development stacking technology began with achieving mounting technology breakthrough. addition, Tohoku University moved achieve system integration stacking wafers, they have announced successful prototype. Fig. shows changes package periods, described above, together with number pins unit area, this shows that likely come after year 2000.
Pins/cm2
1,000
BGA/CSP
1980
1990
2000
2010 Year
Fig. Package form eras count density paradigm shift package technology With advent CSP, paradigm shift occurred package technology. There were reasons this. First, already been explained, silicon industry developed process shrink. This situation will also continue future. However, barriers have come into view. Package technology expected eliminate these barriers. already impossible make single chips timely fashion, appropriate cost, with ever more complex functions. Another reason that, with process shrink only, becoming impossible capture diversifying interests individuals society, create products that make impression. Optimization required design electronic equipment. Naturally performance essential, there other factors like cost, time axis, ease use, design. course many factors must optimized achieve this. Recent products clearly indicate this fact. Function cost matter course. Design factor sales. shrink silicon process does determine design electronic equipment. conventional package technology,
silicon chip product have only tenuous relationship. However, advent changed that relationship. Package technology lies between two, blurred boundary between silicon chip product design technology. both chip designer product designer formulate design that integrated with package, become impossible create products that competitive market. other words, fusion technology progressed. This particularly true products, like cellular phones, which used public whose human interface crucial. somewhat self-serving claim, "CSP what made cellular phones small, lightweight more fun." system package Since chip size, become foundation concept that corresponds SOC. America, regarded alternative known good (KGD), whereas Japan thought smallest possible package. From KGD, only idea chip, from package idea multiple chips. There also significance fact that design realized chip size, this becoming technology that superior SOC. From long time ago, there been idea multi chip module (MCM). There large conceptual difference between this SIP. First, term "MCM" mentioned systemization does have concept active systemization. That positioned simply technology complementing SOC. technology actively optimizing systemization. Furthermore, does address importance package size, simply cannot technology that surpasses SOC. Here, relationship between systemization package technology should clarified. author feels that impossible discuss systemization equipment design without touching concepts such expansion stabilization electronic equipment function. times change, electronic equipment evolves through repetitive cycles function expansion stabilization. example, electronic calculators evolved with basically fixed function. result, calculators have become SOC. With PCs, other hand, function still expanding, they become SOC. long function expanding, device will become SOC, products will
made with system board (SIB). Today, function cellular phones still expanding, they will become SOC. However, assume that certain degree functional stabilization begun, then function block conversion sub-system conversion will occur, finally resulting SOC. That optimization design takes precedence even here. This fact indicates that there relationship between product system size time axis. This shown Fig.
Expansion Function Expansion Function Large System(Ex. Large System(Ex. s-SOC s-SOC
s-SOC s-SOC
s-SIP
s-SIP
s-SOC:sub-System Chip s-SOC:sub-System Chip s-SIP:sub-System Package s-SIP:sub-System Package
Stabilization Function Small System(Ex. Calculator)
4567
s-SOC
s-SOC s-SOC
past
Today
future
Fig. Systemization package technology
Development cellular phones conversion Cellular phones have been developing rapidly last years, here author would like predict their future terms function expansion mounting technology. Cellular phones typical example electronic equipment that seen consistent function expansion, miniaturization weight reduction since they first appeared. Until 1998-1999, process shrink package technology development speed over function expansion, cellular phones kept getting smaller, finally reaching weight less than 60g. appeared that size weight reduction would continue, progress high-density packaging technology like CSP. However, least last years, there been size weight reduction, instead there been some trend toward little gaining weight. human interface most crucial factor cellular phone. size equipment determined naturally size keyboard inputting data screen that must display ever more information function expands. People form preconception that "cellular phone" something that everyone has, which certain shape.
Furthermore, weight already less than grams, extra grams doesn't really make difference. speed cellular phone function expansion begun exceed progress process shrink package technology. example, with highly functional equipment, like iMode Japan that enables Internet connection, number packages seems same greater than conventional voice centric phones contrary expectations package engineers. This because expansion memory capacity will stop, whereas base band logic circuits have already been highly integrated almost into single chip, number memory packages increase. need more memory will wait evolution process technology. This function expansion being softwareoriented, hardware-oriented. iMode device equipped with Java virtual machine that enables execution applications downloaded from Internet. Just with this trend convenient design engineer must respond frequent changes function difficult-to-predict, fickle customer requirements. thought that this function expansion technique will become mainstream equipment future. Multi-layer stacked good this sort high-capacity memory that cannot wait process evolution. conversion, using stacked necessarily required logic analog circuits, also effective. section, efforts have been made achieve miniaturization weight reduction using modules where ordinary capacitors inductors fired onto ceramic board. There also efforts toward realizing circuits with silicon chips, this successful, expect integration with base band section, entire system will likely progress. Even systems expand rapidly like W-CDMA future, thought that size cellular phones kept fixed these techniques. Another conceivable solution make system small possible, mount modules Bluetooth, game functions, Global Positioning Systems (GPS), MP-3 like empty space. Fig. shows changes cellular phone mounting forms, other proposals. Naturally, cellular phone functions progress further phones used part other cellular equipment, best still keep
unit small possible. future, everything goes expected, should possible realize cellular phone with single SIP.
2001 Solution RF+IF RF+IF
Analog Analog Logic Memory Logic Memory Logic
Optional
RF+IF
Analog Logic
Memory
Module Optional
Memory
Module
~1998
Solution
Fig. Changes cellular phone mounting forms, other proposals birth stacked Here more detailed explanation shall given background behind birth stacked forerunner SIP. Sharp succeeded converting flash memory CSP, these devices were leader being adopted cellular phone manufacturers, amidst severe development competition cellular phones, there insatiable demand from customers, even before shifted mass production. author asked could hardly believe questions such "Can't supply flash memory SRAM single CSP?" then said himself, "How about chips CSP?" this time, were already mass-producing stacked packages conventional packages like QFP. However, hard conceive applying technology that just born field cellular phones, where cost competition most severe vertical (short-period) large-volume start-up required. However, stringent customer requirements provided pressure, succeeded development. that time (1998), common sense technology interconnecting electrode chip stacking undoubtedly flip chip (FC) technique. However, decided wirebonding technique that enabled immediate shift mass production. crucial point here that SRAM packaged together with
same size flash memory. stacked technology achieving this combination memory gave rise idea combination with logic ICs. Furthermore, chip stacked helped accelerate concept. layering done CSP, should result high integration good better than SOC. original layer stacking technology also enabled layers, further development multiple layers progresses. Photo shows form memory logic chip stacking developed Sharp.
Table Examples combination
Combination circuits with different functions -Analog circuits logic circuits -Logic circuits memory circuits control circuits -Devices which have functional interference which cause function degradation -Custom using FPGA (PLD) etc. -I/O conversion using converters -Active elements passive elements Combination from standpoint manufacturing (different materials, processes etc.) -Compound semiconductors like GaAs -Chips with different process design rules -Different processes like SiGe, SSOX -Systems large hard integrate into single chip (Testability etc.) -Combinations where single chip integration economically difficult (Yield drop etc.) -Chips from multiple manufacturers -Devices where time market (TTM) difficult with -Devices where increased mounting density desirable
Photo Internal photograph memory/logic chip stacked
Both concept stacked package concept have been previously proposed. However, explained Section very fact that layering done chip size that enables that superior SOC. Furthermore, system becomes large, case today, often case that functions cannot achieved with company's technology. Fortunately, with easy gather combine chips from multiple companies. This very significant achieving results cost suitable consumer mass-market products. Table lists examples combinations expect from SIP. Combination viewed from standpoint circuit function, from standpoint manufacturing (materials, process etc.) Here give examples.
stacked package technology Previously, stacked packages have been developed America high-end applications such those found military equipment. However, trend that began around 1998 Japan clearly different. wave digital systemization moved into consumer equipment that Japanese excel making, result, demand created low-cost high-density packaging. other words, rapid progress digital systems electronic equipment arrived without waiting progress semiconductor process technology. There three methods stacking. They classified into wafer level, chip level package level stacking. There also intermediate technology where chip stacked chip wafer form. wafer level stacking, both wiring length connection length shortened, improved performance expected, there many limitations stacking, technical achievement takes some time. Alternatively, package stacking achieved extending current package technology, conversion difficult. Chip stacking positioned between these alternatives, (depending method) achieved least easily package stacking. Furthermore, cost performance comparatively good. This what chip stacking ahead other alternatives. advantages disadvantages these three technologies shown Table
Table Comparison stacked package technologies
Wafer Level Advantage -Real chip size -Electrical high performance Disadvantage -Future technology -Yield loss (KGD) -Combination limitation -Long-time development -Yield loss (KGD)
exceeds 100%, chip stacked close 200%. silicon mounting efficiency increases number layers increases. This reason stacked better than SOC. Examples stacked package development Here shall indicate stacked package development trends wafer level, chip level package level. 10.1 Wafer level stacking This enables design minimize wiring length between chips, superior electrical performance easier achieve. However, there serious restrictions combinations, thought this technique will used only special applications. present, this still prototype level, shift products will take some time. Normally, wafer between bottom thinly polished tens microns, connection between chips done through via-holes opened wafer. development example that Professor Koyanagi's group Tohoku University. Their areas here reported following five technologies: -Embedded wiring technology etching Via: Diameter polycrystal embedding -Thinning technology, wafer thickness -Bump formation Lift off, Au/In, diameter -Positioning Using infrared rays -Adhesive Epoxy adhesive This technology theme "Global Interface Integration Research" (initiated year 2000 Ministry Education, Science Culture (now called Ministry Education, Culture, Sports, Science Technology). project staffed twenty university researchers from Japan. American Tru-Si Technology Company proposed opening via-holes etching silicon wafer using atmospheric down stream plasma (ADP) technique, using these stacking. 10.2 Chip level stacking chip level stacking core stacking technology, development progressed point that there many examples enumerate. this point there rapid shift mass production companies outside Japan, focusing particularly aforementioned
Chip Level (CSP)
Package Level
-Extended current technology -CSP size -Easy integrate different processes materials -Short-time development -Extended current technology Yield loss -Easy integrate different processes materials -Short-time development
-Package size
author proposes that divide these technologies follows: three chips, chip level stacking, anything above that, chip level stacking package level stacking. multiple layer stacking, package stacking. Wafer stacking will continue developed technology future. Silicon mounting efficiency stacked CSP, silicon-mounting efficiency where outperform SOC. silicon process progressed terms process shrink, even wiring three dimensions progresses, functional elements were made three dimensions. they were integrated dimensions. functional elements easily made three dimensional stacking silicon chips three dimensions. Previously, final mounting form said bare chip mounting. Wafer level CSP, where real chip size achieved, attracted great deal attention. However, wafer level producer side theory. Except cost, customer doesn't care product made. Conversely stacked superior bare chip (i.e. wafer level CSP) mounting density. silicon mounting efficiency bare chip defined 100%. other words, silicon mounting efficiency 100%. Wafer level also 100%, will absolutely never exceed 100%. Even though called CSP, normally package size somewhat large, utmost 80%. other hand, 2-chip stacked
combination memory. previously described, Sharp created opportunity this technology develop, and, wink eye, this flash/SRAM combination memory spread throughout world facto technology cellular phones. Companies like Mitsubishi, Fujitsu Intel joining pursuit Sharp. Sharp structure uses polyimide tape substrate, skillfully employs conventional technologies like wire bonding molding. Even chips shrink with each generation, compatibility maintained. Most Southeast Asian subcontractors have started mass production after Sharp laminate substrate, basically technology different. explained earlier, this technology evolving toward three layer stacked CSP, logic/memory combinations (i.e. Package solutions alternative SOC) have also developed. Electric Industry, Rohm other firms also actively working commercialize SIP. Rohm uses bump type method rather than wire bonding connecting upper lower chip. Association Super-Advanced Electronics Technologies (ASET) group Project conducting following types development. -Via electrode formation technology Blind via, µm-sq/70 depth, metal electrode embedding -Chip thinning technology thickness -Layer mounting technology connection, pitch, epoxy injection -Inspection/Evaluation technology Probing, Xrays etc. -Packaging/Mounting design Thermal design, structure design, electric design 10.3 Package level stacking There have been previous proposals stack memory conventional plastic package. More than anything, advantage package level stacking fact that devices that have been screened burn-in used. Recently, Toshiba commercialized memory card which stacks multiple thick packages called paper-thin package (PTP), Matsushita commercialized card using package stacking. There other examples flourishing development package level stacking technology. most cases, development focusing high-capacity high-density memory packages, with achieving multi-level stacking,
future combinations with logic devices will surely achieved. still debatable whether package level stacking effective SIP. With multi-level stacking, there problems like yield, desirable stack package level. However, this fan-out structure, problematic call this CSP. Other cases development most cases, package must equipped with passive components like capacitors, inductors resistors order achieve system including analog circuits. Therefore, there accelerating trend toward integrating printed circuit boards, ceramic substrate package technology. present, progress being made converting circuit blocks cellular phones into system modules. method used here draw thin film pattern ceramic board, stack these multiple layers, create passive components firing. This field specialty ceramic manufacturers like Murata Mfg. Co., Ltd. future, sections Bluetooth wireless will also modularized. similar vein, resin substrate manufacturers like Ibiden Co., Ltd. Victor Company Japan, Ltd. also developing same sort blocks. Conclusion This paper described package development trends over last years, shown that stacked packages stacked particular, technology that outperform SOC. Today, limitations silicon process shrink coming into view, would like close with prediction expectation that first years 21st century will mark start stacked package. Reference Robert Ristelhueber, Expanding role packaging seem relegating niche status, Times, November 1999. M.Kada, Packaging Trends Mobile Applications, Halbleiter-Industrie 2000, Berlin, September 25-26, 2000. M.Koyanagi, Nikkei Microdevices, pp.50-51, August, 1999. [4]K.Takahashi, chip stacked packaging technology, Internepcon Japan Seminar, 2001
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Morihiro Kada Abstract three-dimensional chip-stacked CSP, which

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