Application Note. October 26th, 1998 Sylvie Kadivar, Philips Semi

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Application Note. October 26th, 1998 Sylvie Kadivar, Philips Semi

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Logic Families LFBGA packages: Balls Profile Fine Pitch Packages.
Application Note.
October 26th, 1998 Sylvie Kadivar, Philips Semiconductors Maria Balian, Texas Instruments Agis, Texas Instruments Valentino Liva, Integrated Device Technology
Disclaimers
Philips Semiconductors
Disclaimers
Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088- 3409 Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
print code Date release: 10-98
rights reserved. Printed U.S.A.
IMPORTANT NOTICE
Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
LIFE SUPPORT POLICY
Integrated Device Technology's products authorized components life support other medical devices systems (hereinafter life support devices) unless specific written agreement pertaining such intended executed between manufacturer officer IDT. Life support devices devices which intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. This policy covers component life support device system whose failure perform cause failure life support device system, affect safety effectiveness.
Note: Integrated Device Technology, Inc. reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. does assume responsibility circuitry described hereinother than circuitry embodied product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication, estoppel, otherwise under patent, other rights, Integrated Device Technology, Inc.
logo Orion registered trademarks IDT. AdvantageIDT, BiCameral, BiFIFO, BurstRAM, BUSMUX, CacheRAM, Centaurus, ClockDoubler, CZAR, DECnet, Double-Density, DualSync, FASTX, FlexBus, FLEXI-CACHE, Flexi-PAK, Flow-thruEDC, Four-Port, Fusion Memory, IDT/c, IDTenvY, IDT/sae, IDT/sim, IDT/ux, Libra, MacStation, MicroMonitor, MICROSLICE, NICStAR, Orion, PalatteDAC, Pegasus, QuickStart, RC3041, RC3051, RC3052, RC3071, RC3081, RC36100, RC3715, RC3740, RC4600, RC4650, RC4700, RV3041, RV3081, RV4600, RV4650, RV4700, RC5000, REAL8,RISCard, RISCompiler, RISController, RISCNT, RISC Subsystems, RISC Windows, SARAM, SmartLogic, SolutionPak, SyncFIFO, SyncBiFIFO, SuperSync, TargetSystem, Zero-BusTurnaround, Smart Zero-Bus-Turnaround, SmartZBT trademarks Integrated Device Technology, Inc. Powering What's Next" Enabling Digitally Connected World" service marks IDT. MIPS registered trademark MIPS Computer Systems, Inc. Pentium Processor trademark Intel Corporation. PowerPC trademark IBM. other brand names product names included this publication trademarks, registered trademarks trade names their respective owners. product violation this policy voids warranties associated with product, used customer's risk.
Table Contents
DISCLAIMERS.II TABLE CONTENTS INTRODUCTION EXAMPLES APPLICATIONS WITH LFBGA PACKAGES Industry expressed requirements Logic Customer needs problems targeted Application examples Existing alternative solutions: Comparison PACKAGE DESCRIPTIONS LFBGA Package Characteristics.8
3.1.1 LFBGA-96 package dimensions. 3.1.2 LFBGA-114 package dimensions. 3.1.3 LFBGA Power Dissipation.
LFBGA TVSOP, TSSOP, MillipaQfootprint.14 Benefits customer Contribution JEDEC Definition Evaluation Units LFBGA PACKAGE MARKING, SHIPPING MEDIA HANDLING. Marking Tape Reel Sockets, Socket Manufacturer (Ordering Information) MANUFACTURING CONSIDERATIONS Land Pads Line Spaces Vias.21 Routing CONCLUSION Acknowledgements:.23
Introduction
With increasing systems circuit complexity constant downward pressure system prices, requirements interface solutions demand approaches system needs. major challenges goals digital processing industry continue decreasing overall system costs system complexity increases. Consequently, circuit integration board miniaturization have become words trends present future applications. direct consequence these trends need wider interfacing. Today, many networking, telecom computer systems begin using DSP's MPU's that require 32bit, even wide interfacing, there increasing demand 32bit wide buffer, driver transceiver functions. These functions will become standard years come. address evolving customer requirements, three suppliers, Integrated Device Technology, Philips Semiconductors Texas Instruments have come together define package 32bit functions. Collectively Integrated Device Technology, Philips Semiconductors Texas Instruments evaluated many customer inputs identified Profile Fine Pitch Ball Grid Array (LFBGA) package solution that would best serve customers' needs. Studies have shown that LFBGA optimal solution reducing inductance, improving thermal performance minimizing board real estate support integrated functions. Together, objective provide multi-source products package that enables significant electrical improvements when compared existing packages, well cost savings manufacturing process. From supplier standpoint, guarantee multi-sourcing package that will become standard very near future. purpose this document discuss Fine Pitch solutions, ball LFBGA packages. Five functions will initially introduced LFBGA package. Additional products will manufactured market interest customer demand. definition description ball LFBGA packages discussed this application note. Content technical exhibits from application note should used develop layouts using and/or ball LFBGA packages. Examples routing, layout mechanical dimensions also included this document. initial introduction Logic noted table below:
Number Balls Connection
LVCH Functions 74LVCH32244 74LVCH32245 74LVCH32373 74LVCH32374 ALVCH Function 74ALVCH32501
Package
Table Initial Functions
LFBGA packages offer lower inductance parasitic capacitance than other TSSOP, TVSOP MillipaQpackages. LFBGA package characteristics supports improvements Ground bounce, undershoot, pin-to-pin skew, signal propagation delay 50ps. definition these packages terms standardization, both physical mechanical, developed Integrated Device Technology, Philips Semiconductors Texas Instruments provide industry pinout compatible solutions.
Examples Applications with LFBGA Packages
Industry expressed requirements Logic
With growing trend towards increased widths, OEMs looking consolidate logic functions effort effectively make board real estate. This requirement from customers prevalent across many equipments. requirement reduce board real estate also necessitates packaging solution, which integrates logic well addresses improved thermal packaging characteristics addition minimizing pin-to-pin skew. selection Ball LFBGA addresses these careabouts with improved performance standardization outs agreed upon Integrated Device Technology, Philips Semiconductors Texas Instruments. initial month study, consisting OEMs several worldwide subcontractors, found that preferred pitch introducing logic either LFBGA 0.8mm with 0.5mm ball diameter. Both packages being offered Integrated Device Technology, Philips Semiconductors Texas Instruments support customer requirements enable easier design/layout along with more robust solder joint based life cycle studies. While other solutions were looked such staggered depopulated balls, with smaller pitch, well smaller ball diameter, none were considered suitable address current market needs OEM's subcontractors. LFBGA packages selected IDT, Philips Semiconductors Texas Instruments optimal solution addresses current customer needs. More details package comparison noted within other subsections this application note.
Customer needs problems targeted
Workstations: Workstations busses extend 128, bits, wider structures; Require denser faster logic products. PCs: trend integrate much logic possible into fewer packages; space constraint, Cards require dense integration small package foot-prints; structures require tolerance addition integrating logic circuits. Datacommunication: "Intelligent" routers switches require more logic support interfaces build real time lookup tables routing addresses with statistics.
Telecommunication: Base stations becoming small ubiquitous requiring repackaging many circuits into dense boards; complex smaller equipment must interface with legacy equipment.
Application examples
Motherboards Data communications Telecommunications Back Planes Base stations Cellular cordless telephone
Existing alternative solutions: Comparison
While other packages have been introduced address integrated logic solutions, these packages have only limited success, such TQFPs 80/96 MillipaQ. comparison, these solutions have reduce number ground pins leading believe that ground bounce pin-to-pin skew cannot optimally designed address these design issues. Comparisons foot print space show that TQFP 80/96 MillipaQpackages takes respectively 245% more area than corresponding LFBGA. further details refer tables 2.2. 96-ball LFBGA package provides optimal area/bit ratio improved pin-topin skews. Pin-to-pin skew minimized number signals connected same ground connection. Package LFBGA MillipaQ80/96 TVSOP TSSOP SSOP TQFP Footprint Area mm2) 74.25 123.0 132.5 213.0 342.0 256.0 Area/Bit (mm2) 2.32 3.84 4.14 6.66 10.7 8.00 Weight (g.) 0.132 0.332 0.227 0.383 1.180 0.660 Total Balls pins 80/96
Note Area/bit computed bits assumes 1.3mm spacing two-package solution. Note MillipaQoffers logic functions with reduced ground Vccs; such configuration compromises signal integrity logic functions.
Table Comparison Foot Print Size with LFBGA.
Package LFBGA TVSOP TSSOP SSOP TQFP
Footprint Area mm2) 88.00 153.0 237.3 394.6 256.0
Area/Bit (mm2) 2.44 4.25 6.59 11.0 7.11
Weight (g.) 0.167 0.271 0.423 1.360 0.660
Total Balls pins
Note Area/bit computed bits assumes 1.3mm spacing two-package solution.
Table Comparison Foot Print Size with LFBGA
Package Descriptions
Figure shows cross section LFBGA package.
Figure LFBGA Cross Section
Table summarizes package attributes LFBGA. LFBGA-96 13.5 1.2min 1.5max 1000 Level LFBGA-114 1.2min -1.5max 1000 Level
Ball count Ball configuration (rows, columns) Square/Rectangular Ball-to-ball pitch (mm) Ball diameter (mm) Package body width (mm) Package body length (mm) Package thickness (mm) Package weight (mg) Shipping media Tape Reel (units) Desiccant pack
Table LFBGA Package Attributes
LFBGA Package Characteristics
3.1.1 LFBGA-96 package dimensions.
Max. 0.8mm
View
5.5mm
13.5mm
Ball organization: Footprint: balls; grid 0.8mm; 74.25
Figure LFBGA-96 Package Layout Advantages: Industry accepted 0.8mm pitch industry standard; easy pad-via-to-ball routing; Easy customer layout; easy locate near connectors; Robust solderability standard .5mm ball size.
LFBGA-96 Configuration: Note: configuration below adopts same naming convention applied industry logic devices packages (i.e. TSSOP, SSOP, TVSOP).
Control
Note: This topside view
Figure View Assignment Electrical: electrical parameters package dependant upon parasitic elements, which include inductance, capacitance, electrical propagation delays throughout package. table below summarizes typical parasitic components LFBGA package. should note that reported values LFBGA package about better than TVSOP package better than TSSOP package. Overall LFBGA package better than existing industry standard package market today. Figure provides electrical comparison LFBGA-96 with other industry standard packages.
Inductance
LFBGA MillipaQ TVSOP TSSOP TQFP Minimum Maximum
Figure Electrical Comparisons.
3.1.2 LFBGA-114 package dimensions.
Max.
View
Ball organization: Footprint:
balls (112 used); grid 0.8mm; Figure LFBGA-114 Package Layout
Advantages: Industry accepted 0.8mm pitch; easy pad-via-to-ball routing; Easy customer layout; easy locate near connectors; Robust solderability standard .5mm ball size.
LFBGA-114 Configuration: Note: configuration below adopts same naming convention applied industry logic devices packages (i.e. TSSOP, SSOP, TVSOP).
Control
Control
Note: This topside view
Figure view assignment Electrical: electrical parameters package dependent upon parasitic elements, which include inductance, capacitance electrical propagation delays throughout package. table below summarizes typical parasitic components LFBGA package. should note that reported values LFBGA package about better than TVSOP package better than TSSOP package. Overall LFBGA package better than existing industry standard package market today.
3.1.3 LFBGA Power Dissipation. power dissipation LFBGA very much dependent upon thermal conduction paths between chip printed circuit board (PCB). ball LFBGA package outline small, thereby limiting amount power dissipation convection radiation, becomes major heat source package. thermal performance packages good when chip overlaps solder balls fact that balls under chip thermal conduction paths PCB. thermal resistance LFBGA packages better than TVSOP package better than TSSOP package. well-designed board further enhances power dissipation both LFBGA packages. adding thermal vias (i.e from solder ball buried ground plane), significant benefit obtained over existing designs.
3.50 3.00 Power 2.50 2.00 1.50 1.00 0.50 0.00 Ambient Temperature
96/114 LFBGA TQFP TSSOP TVSOP
Note: maximum power dissipation calculated using junction temperature 150C.
Figure Thermal Comparisons Multi-layer JEDEC Board.
4.00 3.50 3.00 2.50 @Tj=150C @Tj=150C @Tj=150C @Tj=150C
Power
2.00 1.50 1.00 0.50 0.00
Ambient Temperature
Note: maximum power dissipation calculated using junction temperature 150C.
Velocity (ft/min) (C/W)
39.8
38.0
37.2
35.9
Figure LFBGA thermal derating curves without thermal vias using multilayer JEDEC Board.
4.50 4.00 3.50
Power
3.00 2.50 2.00 1.50 1.00 0.50 0.00
@Tj=150C @Tj=150C @Tj=150C @Tj=150C
Ambient Temperature
Note: maximum power dissipation calculated using junction temperature 150C.
Velocity (ft/min) (C/W)
36.1
34.4
33.6
32.5
Figure LFBGA thermal derating curves with thermal vias using multilayer JEDEC Board.
LFBGA TVSOP, TSSOP, MillipaQfootprint
Newspace savaind
Routing Space
over
48-Pin
SSOP
48-Pin
TSSOP
48-Pin
TVSOP
48-Pin
TSSOP
48-Pin
TVSOP
80/96-Pin MillipaQ
96-Ball
Logic
Logic
Figure 3.10 Package Comparisons
Comparison normalized thermal dissipation TSSOP, TVSOP, LFBGA-96 shows that LFBGA-96 with thermal vias exceeds factor capability TSSOP packages.
mW/mm Normalized Power Dissipation 25oC
48-Pin
TSSOP
48-Pin
TVSOP
96-Ball
without thermal vias
96-Ball
with thermal vias
Figure 3.11 Normalized Power Dissipation 25oC
Note: Calculations based data from figure figure 3.10.
Benefits customer
following table summarizes features corresponding benefit logic products assembled LFBGA packages.
Feature
Offer minimum foot print Industry Minimize Skew parameter Minimize package propagation delay Rise Time Fall Time typical
Benefit
Uses smallest real estate among industry standard packages; Cost savings boards; Provides user with reliable solution faster busses configurations; Provides user with additional design margin high speed busses; Again, optimized meet good duty cycle 100mhz 133mhz while keeping ground bounce under 500mV Allows more noise margin. Meet mechanical electrical specifications define IDT/TI/PHILIPS working group 2.5V other special supply from 3.3V cost, maintenance, better reliability LFBGA packages less capacitance pin-to-pin inductance ground inductance. This provides better support high-speed applications.
Lower Ground Bounce Selected JEDEC standard package
external components other than bypass Capacitors Supports/enables high speed applications
Table Feature/benefits LFBGA packages
Contribution JEDEC Definition
LFBGA packages have received JEDEC (Joint Electronics Device Engineering Council) JC-11 under semiconductor package standard MO-205 EIAJ (Electronic Industry Association Japan) registration. IDT, Texas Instruments Philips Semiconductors have also submitted JEDEC proposed ball LFBGA pin-out JC-40 council final voting JEDEC participants expected 1998.
Evaluation Units
evaluation units, contact authorized distributors more information refer following URLs: Integrated Device Technology URL: http://www.idt.com Philips Semiconductors URL: http://www.philipslogic.com Texas Instruments URL: http://www.ti.com/sc/lfbga
LFBGA Package Marking, Shipping Media Handling.
following section describes symbolization these LFBGA packages.
Marking
Integrated Device Technology, Philips Semiconductors Texas Instruments laser marking identify vendor, product number, year month fabrication, manufacturing site, trace code. Each vendor adopted specific package designator LFBGA packages reported table 4.1: Philips Texas Semiconductor Instruments Table Vendor package designator Integrated Device Technology
LFBGA LFBGA
Marking examples LVCH32244 device: Marking: Part LVCH322244A Date Code, Marking Location number, Assembly Location Texas Instruments Marking: Part CH244A Year, Month, Site trace code Philips Semiconductors Marking: Part LVCH32244A number, Site Date Code Device Name LVCH32244A Logo X9848Y Xmax10xX
CH244A Logo LLLL
Logo LVCH32244A Trace YYWW
Integrated Device Philips Texas Instruments Technology Semiconductors LVCH32244A LVCH32244A LVCH32244A CH244A LVCH32245A LVCH32245A LVCH32245A CH245A LVCH32373A LVCH32373A LVCH32373A CH373A LVCH32374A LVCH32374A LVCH32374A CH374A ALVCH32501 ALVCH32501 ALVCH32501 ACH501 Table Vendor part number marked package
Tape Reel
embossed Tape Reel method preferred automatic pick-and-place machines. Integrated Device Technology, Philips Semiconductors Texas Instruments offer Tape Reel packaging ball LFBGA packages. packaging materials used include Carrier Tape, Cover Tape Reel. material used meets industry guidelines protection design full compliance with Standard 481-A, "Taping Surface Mount Components Automatic Placement." dimensions that interest end-user tape width (W), pocket pitch quantity reel. figure below illustrates Tape Reel design LFBGA package.
Reel Diameter
Reel Width Cover Tape Width
Figure Tape Reel mechanical dimensions
Package
Cover Tape Pocket Width Pitch 21.0 21.0 8.00 8.00
Reel Width 24.0 24.0
LFBGA LFBGA
Reel Diamete
Quantity Reel 1000 1000
Table Tape Reel assembly information
Package
Pocket Width (A0)
Pocket Length (B0)
Pocket Depth (K0)
Pedestal Depth (K1)
Hole Pocket Centerline
LFBGA 13.7 LFBGA 16.2 dimensions millimeters
11.5 11.5
Table Tape Reel Dimension LFBGA package.
Sockets, Socket Manufacturer (Ordering Information)
Yamaichi Socket numbers: LFBGA-96 LFBGA-114 IC280-096-144 IC280-114-145
Yamaichi Electronics USA, Inc. 2235 Zanker Road Jose, 95131 Loranger Socket numbers: Loranger International Corp. Fourth Avenue Warren, 16365 California Contact Office
Tel: (408) 456-0797 LFBGA-96 LFBGA-114 135055096U6617 169055114U6617
Tel: (814) 723-2250 Tel: (408) 727-4234
Manufacturing Considerations
following section describes assembly PCBs LFBGA products.
Land Pads
design land pads LFBGA packages printed circuit board critical, end-user wants achieve good manufacturability optimum reliability. optimum design when diameter land equal diameter package vias; (i.e. fatigue life solder balls enhanced when ratio these dimensions equal 1.0). There methods defining land pads solder mask defined non-solder mask defined. solder mask defined, desired land area defined opening solder mask. advantage this technique that land size controlled solder mask promotes adhesion copper PCB. However, copper dimension larger which makes routing more difficult. non-solder mask defined, land area etched inside solder mask area. final land dimension dependent accuracy copper etching method. advantage non-solder mask defined over solder mask defined methods routability allows larger trace width/spacing between solder balls). Figure illustrates land dimension ball LFBGA package using solder mask defined non-solder mask defined method.
Solder Mask Defined 0.48mm 0.38mm
Non-solder Mask Defined 0.35 0.50
Figure LFBGA Recommended Land Design
Line Spaces
This section describes maximum trace width/spacing dimension allowed 0.8mm ball pitch LFBGA packages with 0.5mm ball diameter. becomes challenge designers route this package single layer board unless supplier fine pitch trace width/spacing capabilities. capabilities currently (100 trace width/spacing range using finer pitch trace width/spacing will increase overall cost end-user. optimum design current capability, which allows signal routed between land pads. Using recommended land dimension outlined section 5.1, supplier needs have trace width/spacing capabilities (107 (150 respectively solder mask nonsolder mask defined pads. Figure represents visual layout described section 5.3.
Figure LFBGA Trace Width/Spacing Dimensions
Vias
density just challenging designers when routing high-density board. density defined number vias particular board area. Using smaller vias increases density routability board requiring less board space. Holes mechanically drilled down (152 however, mechanically drilled holes less than (305 begin cost PCB. avoid higher costs, other technology exist (such laser, punched plasma-etched) used form smaller holes. invention microvia solved many problems associated with density. Micro-vias often created using plasma-etched technique, which penetrates layers dielectric allows signal routing internal layers. Current micro-via technology allows diameter. Micro-vias also designed directly into land thereby obsoleting trace fan-outs. Table summarizes maximum diameter that used routing LFBGA package using recommended land dimensions outlined section 5.1. Solder Mask Non-solder Mask Defined Land Defined Land Trace width/spacing 0.107mm (4.2 mil) 0.150mm (5.9 mil) Drill diameter 0.35 0.38 0.23 0.25 mil) mil) Unplated hole 0.35 0.38 0.23 0.25 mil) mil) Finished size (plated) 0.30 0.33 0.178 mil) mil) Note: Unplated diameter assumes mil) land dimension mil) clearance between land adjacent land pad. Table Maximum diameter
Routing
figures below examples routing with layers interconnect:
Note Ground balls connected together within PCB. Figure LFBGA-96 recommended routing
Note Ground balls connected together within PCB. Figure LFBGA-114 recommended routing
Conclusion
This joint study Integrated Device Technology, Philips Semiconductors Texas Instruments shows LBGA packages most effective solution addressing performance issues: minimal skew package layout design; improved thermal power dissipation taking advantage chip overlap over solder balls; reduced inductance functions these packages take advantage less capacitance pin-to-pin inductance, thereby enabling support high speed applications with close bandwidth. terms board integration miniaturization, these LFBGA packages will reduce board space compared corresponding TSSOP package same functionality. Additionally, designers take advantage improved reliability reduced manufacturability costs when diameter land equal diameter package vias explained section With introduction LFBGA Integrated Device Technology, Philips Semiconductors Texas Instruments, OEMs assured agreed upon JEDEC standardized package, availability product families functions initially introduced. Integrated Device Technology, Philips Semiconductors Texas Instruments will continue work with market identifying requirements terms product family, functions.
Acknowledgements:
Authors would like thank following contributors this Application Note with relevant diagrams technical information: Ciani, Purdom, Craig St.Martin from Texas Instruments; Jeff West, Allen Glaus, Hanson, Schultze, Henk Kloen, Alma Anderson from Philips Semiconductors; Ernie Oregano, Ronnie Tanhueco, from Integrated Device Technology.
AN-Original Revision.

Application Note. October 26th, 1998 Sylvie Kadivar, Philips Semi

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