3.3V CMOS 18-BIT IDT74LVCH16601A UNIVERSAL TRANSCEIVER WITH 3-STATE OU

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

3.3V CMOS 18-BIT IDT74LVCH16601A UNIVERSAL TRANSCEIVER WITH 3-STATE OU

Datasheet Thumbnail

Top Searches for this datasheet

IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
3.3V CMOS 18-BIT IDT74LVCH16601A UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS, VOLT TOLERANT I/O, BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion Drive Features LVCH16601A: High Output Drivers: ±24mA Reduced system switching noise
Data flow each direction controlled output-enable (OEAB OEBA), latched-enable (LEAB LEBA), clock (CLKAB CLKBA) inputs. clock controlled clock-enable (CLKENAB CLKENBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held high logic level. LEAB low, A-bus data stored latch/ flip-flop low-to-high transition CLKAB. Output enable OEAB active low. When OEAB low, outputs active. When OEAB high, outputs high-impedance state. Data flow similar that uses OEBA, LEBA, CLKBA CLKENBA. pins driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH16601A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. LVCH16601A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
DESCRIPTION
LVCH16601A 18-bit universal transceiver built using advanced dual metal CMOS technology. LVCH16601A combines Dtype latches D-type flip-flops allow data flow transparent, latched clocked modes.
Functional Block Diagram
OEAB
CLKAB LEAB LEBA
CLKENBA
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4074/1
IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
CONFIGURATION
OEAB LEAB OEBA LEBA SO56-1 SO56-2 SO56-3 CLKENAB CLKAB
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Unit
Link
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
CLKBA CLKENBA
CI/O
NOTE: applicable device type.
FUNCTION TABLE
CLKENAB OEAB Inputs LEAB CLKAB Outputs B0(3) B0(3) B0(4)
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names OEAB OEBA LEAB LEBA CLKAB CLKBA CLKENAB CLKENBA Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1) A-to-B Clock Enable Input (Active LOW) B-to-A Clock Enable Input (Active LOW)
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
1998 Integrated Device Technology, Inc.
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition A-to-B data flow shown. B-to-A data flow similar uses OEBA, LEBA, CLKBA CLKENBA. Output level before indicated steady-state input conditions were established. Output level before indicated steady-state input conditions were established, provided that CLKAB HIGH before LEAB went LOW.
DSC-123456
IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance transceiver Outputs enabled Power Dissipation Capacitance transceiver Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Propagation Delay LEBA LEAB Propagation Delay CLKBA CLKAB Output Enable Time OEBA OEAB Output Disable Time OEBA OEAB Set-up Time, HIGH CLKAB, CLKBA Hold Time HIGH after CLKAB, after CLKBA Set-up Time Clock HIGH LEAB, Clock LEBA HIGH Set-up Time, CLKENAB CLKAB Set-up Time, CLKENBA CLKBA Hold Time, HIGH after LEAB, after LEBA Hold Time, CLKENAB after CLKAB Hold Time, CLKENBA after CLKBA LEAB LEBA Pulse Width HIGH CLKAB CLKBA Pulse Width HIGH Output Skew(2) Min.
2.7V Max. Min. 3.3V±0.3V Max. Unit
tSK(o)
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
ORDERING INFORMATION
Bus-H Family XXXX Device Type Package Temp. Range
601A
Shrink Outline Package (SO56-1) Thin Shrink Outline Package (SO56-2) Thin Very Outline Package (SO56-3) 18-Bit Universal Transceiver 3-State Outputs Double-Density with esistors, ±24m
Bus-hold -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com*
search sales office near you, please click sales button found home page dial 800# above press logo registered trademark Integrated Device Technology, Inc.

3.3V CMOS 18-BIT IDT74LVCH16601A UNIVERSAL TRANSCEIVER WITH 3-STATE OU

Top Searches for this datasheet

Other recent searches