3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT TOLERANT BUS-HOLD T

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3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT TOLERANT BUS-HOLD T

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IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT TOLERANT BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion Drive Features LVCH16260A: High Output Drivers: ±24mA Reduced system switching noise
IDT74LVCH16260A
multiplexer/transceiver high-speed microprocessor applications. This exchanger supports memory interleaving with latched outputs ports address multiplexing with latched inputs ports. LVCH16260A tri-port exchanger three 12-bit ports. Data transferred between port either/both ports. latch enable (LE1B, LE2B, LEA1B LEA2B) inputs control data storage. When latch-enable input high, latch transparent. When latchenable input low, data input latched remains latched until latch enable input returned high. Independent output enables (OE1B OE2B) allow reading from port while writing other port. pins 12-bit Exchanger driven from either 3.3V devices. This feature allows device translator mixed 3.3V/5V supply system. LVCH16260A been designed with ±24mA output driver. driver capable driving moderate heavy load while maintaining speed performance. LVCH16260A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
DESCRIPTION:
LVCH16260A tri-port exchanger built using advanced dual metal CMOS technology. LVCH16260A high-speed 12-bit latched
Functional Block Diagram
OE1B
LEA1B
A-1B LATCH
1:12
LE1B
1B-A LATCH
1:12
LE2B
2B-A LATCH
LEA2B
A-2B LATCH
1:12
OE2B
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4229/1
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
CONFIGURATION
LE1B LE2B 56-1 56-2 56-3 OE2B LEA2B LEA1B OE1B
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Unit
Link
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
NOTE: applicable device type.
SSOP/ TSSOP/ TVSOP VIEW
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
FUNCTION TABLES
Inputs LE1B
Outputs
Inputs LEA1B LEA2B OE1B OE2B B0(2) B0(2)
Outputs B0(2) B0(2) B0(2) Active Active
LE2B
A0(2)
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance Output level before indicated steady-state input conditions were established.
Active Active
DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) LEA1B LEA2B LE1B LE2B OE1B OE2B Description Bidirectional Data Port Usually connected CPU's Address/Data bus.(1) Bidirectional Data Port Connected even path even bank memory.(1) Bidirectional Data Port Connected path bank memory.(1) Latch Enable Input A-1B Latch. Latch open when LEA1B HIGH. Data from A-port latched HIGH transition LEA1B. Latch Enable Input A-2B Latch. Latch open when LEA2B HIGH. Data from A-port latched HIGH transition LEA2B. Latch Enable Input 1B-A Latch. Latch open when LE1B HIGH. Data from port latched HIGH transition LE1B. Latch Enable Input 2B-A Latch. Latch open when LE2B HIGH. Data from port latched HIGH transition LE2B. Path Selection. When HIGH, enables data transfer from Port Port. When LOW, enables data transfer from Port Port. Output Enable Port (Active LOW). Output Enable Port (Active LOW). Output Enable Port (Active LOW).
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance exchanger Outputs enabled Power Dissipation Capacitance exchanger Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Propagation Delay LEXB Propagation Delay LEA1B LEA2B Propagation Delay Output Enable Time OE1B 1BX, OE2B Output Disable Time OE1B 1BX, OE2B Set-Up Time, HIGH Data Latch Hold Time, Latch Data Pulse Width, Latch HIGH Output Skew
2.7V±0.2V Min. Max. Min. 3.3V±0.3V Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT
ORDERING INFORMATION
Bus-Hold Family XXXX Device Type Package Temp. Range
260A
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 12-Bit Tri-Port Exchanger Double-D ensity with Resistors, ±24m
Bus-hold -40°C +85°C
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3.3V CMOS 12-BIT TRI-PORT EXCHANGER WITH VOLT TOLERANT BUS-HOLD T

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