2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
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ST5092
2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
FEATURES: Complete CODEC FILTER system including: LINEAR ANALOG DIGITAL DIGITAL ANALOG CONVERTERS. COMPANDED ANALOG DIGITAL DIGITAL ANALOG CONVERTERS A-LAW µ-LAW. TRANSMIT RECEIVE BAND-PASS FILTERS ACTIVE ANTIALIAS NOISE FILTER. Phone Features: THREE SWITCHABLE MICROPHONE AMPLIFIER INPUTS. GAIN PROGRAMMABLE: PREAMP. (+MUTE), 22.5 AMPLIFIER, STEPS. EARPIECE AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: STEPS. EXTERNAL AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: STEPS. TRANSIENT SUPRESSION SIGNAL DURING POWER DURING AMPLIFIER SWITCHING. INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATION PROGRAMMABLE: RANGE, STEP. ROUTING POSSIBLE BOTH OUTPUTS. INTERNAL RING TONE GENERATOR INCLUDING DTMF TONES, SINEWAVE SQUAREWAVE WAVEFORMS. ATTENUATION PROGRAMMABLE: 27dB RANGE, STEP. THREE FREQUENCY RANGES: 3.9Hz 996Hz, 3.9Hz STEP 7.8Hz 1992Hz, 7.8Hz STEP 15.6Hz 3984Hz, 15.6Hz STEP PROGRAMMABLE PULSE WIDTH MODULATED BUZZER DRIVER OUTPUT. General Features: SINGLE 2.7V 3.6V SUPPLY EXTENDED TEMPERATURE RANGE OPERATION -40°C 85°C. STANDBY POWER (TYP. 3.0V). 15mW OPERATING POWER (TYP. 3.0V). 13mW OPERATING POWER (TYP. 2.7V). CMOS COMPATIBLE DIGITAL INTERFACES. PROGRAMMABLE CONTROL INTERFACE MICROWIRE COMPATIBLE.
September 2003
TQFP44(10x10x1.4)
SO28
ORDERING NUMBERS: Package ST5092AD ST5092ADTR ST5092TQFP ST5092TQFPTR SO28 SO28 TQFP44 TQFP44 Dim. Cond. Tube Tape&Reel Tray 8x20 Tape&Reel
10x10x1.4 10x10x1.4
APPLICATIONS: DIGITAL CELLULAR TELEPHONES. DIGITAL CORDLESS TELEPHONES. DECT DIGITAL CORDLESS TELEPHONES. BATTERY OPERATED AUDIO FRONT-ENDS DSPs.
Functionality guaranteed range 40°C +85°C; Timing Electrical Specifications guaranteed range 30°C +85°C.
GENERAL DESCRIPTION ST5092 high performance power combined CODEC/FILTER device tailored implement audio front-end functions required next generation voltage/low power consumption digital terminals. ST5092 offers number programmable functions accessed through serial control channel that easily interfaces classical microcontroller. interface supports both non-delayed (normal reverse) delayed frame synchronization modes. ST5092 configurated either 14-bit linear 8-bit companded coder. Additionally CODEC/FILTER function, ST5092 includes Tone/Ring/DTMF generator, sidetone generation, buzzer driver output. ST5092 fulfills exceeds D3/D4 CCITT recommendations ETSI requirements digital handset terminals. Main applications include digital mobile phones, cellular cordless phones, battery powered equipment that requires audio codecs operating single supply voltages
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ST5092
CONNECTIONS (Top view)
MIC3+ MIC1+
MIC1N.C. MIC2+ MIC2N.C. N.C. N.C. MCLK N.C.
GNDA
VCCP
VCCA
MIC3-
N.C.
N.C.
N.C.
N.C.
N.C. VFrVFr+ N.C. VLr1
N.C. VCCA VCCP N.C. VFrVFr+ VLrVLr+ GNDP CCLK CSCI
D94TL094
MIC3+ MIC3GNDA MIC1+ MIC1MIC2+ MIC2LO MCLK
SO28
VLr+ N.C. GNDP N.C. N.C.
TQFP44
N.C.
N.C.
CCLK
N.C.
N.C.
D94TL095
BLOCK DIAGRAM
MIC3MIC2-
PREAMP 20dB MUTE
22.5 1.5dB STEP
MIC1(A)
MIC2+
PREFILTER BANDPASS FILTER
TRANSMIT REGISTER
MIC1+ MIC3+ EARA OUTPUT
-30dB, STEP
BANDPASS FILTER
RECEIVE REGISTER
VFr-
12dB VFr+
VLr-1
TONE, RING DTMF GENER. FILTER
TONE -27dB STEP
CONTROL INTERFACE µ-WIRE CLOCK GENERATOR SYNCHRONIZER
CSCCLK MCLK
12dB VLr+
EXTA OUTPUT
INTERFACE LATCH
SIDETONE -12.5 -27.5dB STEP
BUZZER DRIVER
LEVEL ADJUST (PWM)
TL074
GNDP
GNDA
VCCA
VCCP
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ST5092
FUNCTIONS (SO28)
Name
N.C. VCCA VCCP N.C. VFr+, VFr-
Description
Connected. Positive power supply input analog section. must directly connected together. Positive power supply input power section. VCCP must connected together. Connected. Receive analog earpiece amplifier complementary outputs. These outputs drive directly earpiece transductor. signal this output Receive Speech signal from Internal Tone Generator, Sidetone signal. Receive analog extra amplifier complementary outputs. signal these outputs Receive Speech signal from Internal Tone generator, Sidetone signal. Power ground. driver referenced this pin. GNDP must connected together close device. Receive data input: Data shifted during assigned Received time slots delayed nondelayed normal frame synchr. modes voice data byte shifted MCLK frequency falling edges MCLK, while non-delayed reverse frame synchr. mode voice data byte shifted MCLK frequency rising edges MCLK. Control Clock input: This clock shifts serial control information into from when input low, depending current instruction. CCLK asynchronous with other system clocks. Chip Select input: When this low, control information written into from ST5092 pins. Control data Input: Serial Control information shifted into ST5092 this when rising edges CCLK. Pulse width modulated buzzer driver output. Positive power supply input digital section. Control data Output: Serial control/status information shifted from ST5092 this when falling edges CCLK. Transmit Data ouput: Data shifted this during assigned transmit time slots. Elsewhere output high impedance state. delayed non-delayed normal frame synchr. modes, voice data byte shifted from TRISTATE output MCLK rising edge MCLK, while non-delayed reverse frame synchr mode voice data byte shifted falling edge MCLK. Ground: digital signals referenced this pin. Frame Sync input: This signal 8kHz clock which defines start transmit receive frames. three formats used this signal: delayed normal mode, delayed mode, delayed reverse mode. Master Clock Input: This signal used switched capacitor filters encoder/decoder sequencing logic. Values must kHz, 1.536 MHz, 2.048 2.56 selected means Control Register CRO. MCLK used also shift-in data. logic written into (CR1) appears logic logic written into (CR1) appears logic Second negative high impedance input transmit pre-amplifier microphone connection. Second Positive high impedance input transmit pre-amplifier microphone connection. Negative high impedance input transmit pre-amplifier microphone connection. Positive high impedance input transmit pre-amplifier microphone connection. Analog Ground: analog signals referenced this pin. GNDA must connected together close device. Third negative high impedance output transmit preamplifier microphone connection. Third positive high impedance output transmit preamplifier microphone connection.
VLr+, VLr-
GNDP
CCLK
CSCI
MCLK
MIC2MIC2+ MIC1MIC1+ GNDA MIC3MIC3+
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ST5092
FUNCTIONS (TQFP44) Name
Description
N.C. Connected. VFr+, VFr- Receive analog earpiece amplifier complementary outputs. These outputs drive directly earpiece transductor. signal this output summ Receive Speech signal from Internal Tone Generator, Sidetone signal. N.C. Connected. VLr+, VLr- Receive analog extra amplifier complementary outputs. signal these outputs Receive Speech signal from Internal Tone generator, Sidetone signal. N.C. Connected. GNDP Power ground. driver referenced this pin. GNDP must connected together close device. N.C. Connected. Receive data input: Data shifted during assigned Received time slots delayed non10 delayed normal frame synchr. modes voice data byte shifted MCLK frequency falling edges MCLK, while non-delayed reverse frame sinchr. mode voice data byte shifted MCLK frequency rising edges MCLK. 11,12,13 N.C. Connected. CCLK Control Clock input: This clock shifts serial control information into from when input low, depending current instruction. CCLK asynchronous with other system clocks. CSChip Select input: When this low, control information written into from ST5092 pins. Control data Input: Serial Control information shifted into ST5092 this when rising edges CCLK. Pulse width modulated buzzer driver output. Positive power supply input digital section. Control data Output: Serial control/status information shifted from ST5092 this when falling edges CCLK. Transmit Data ouput: Data shifted this during assigned transmit time slots. Elsewhere output high impendance state. delayed non-delayed normal frame synchr. modes, voice data byte shifted from TRISTATE output MCLK rising edge MCLK, while non-delayed reverse frame synchr mode voice data byte shifted falling edge MCLK. Ground: digital signals referenced this pin. 22,23 N.C. Connected. Frame Sync input: This signal 8kHz clock which defines start transmit receive frames. Either three formats used this signal: delayed normal mode, delayed mode, delayed reverse mode. MCLK Master Clock Input: This signal used switched capacitor filters encoder/decoder sequencing logic. Values must kHz, 1.536 MHz, 2.048 2.56 selected means Control Register CRO. MCLK used also shift-in data. logic written into (CR1) appears logic logic written into (CR1) appears logic 27,28,29 N.C. Connected. MIC2- Second negative high impedance input transmit pre-amplifier microphone connection. MIC2+ Second Positive high impedance input transmit pre-amplifier microphone connection. N.C. Connected. MIC1- Negative high impedance input transmit pre-amplifier microphone connection. MIC1+ Positive high impedance input transmit pre-amplifier microphone connection. N.C. Connected. GNDA Analog Ground: analog signals referenced this pin. GNDA must connected together close device. MIC3- Third negative high impedance output transmit preamplifier microphone connection. MIC3+ Third positive high impedance output transmit preamplifier microphone connection. 39,40 N.C. Connected. Positive power supply input analog section. VCCA must directly connected together. Positive power supply input power section. VCCP must connected together. VCCP 43,44 N.C. Connected.
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FUNCTIONAL DESCRIPTION DEVICE OPERATION Power initialization: When power first applied, power reset circuitry initializes ST5092 puts into power down state. Gain Control Registers various programmable gain amplifiers programmable switches initialized indicated Control Register description section. CODEC functions disabled. desired selection programmable functions intialized prior power command using MICROWIRE control channel. mute case, analog transmit signal grounded sidetone path also disabled. Following first stage programmable gain amplifier which provides from 22.5 additional gain 1.5dB step. total transmit gain should adjusted that, reference point Block Diagram description, internal dBm0 voltage 0.49 Vrms (overload level Vrms). Second stage amplifier gain programmed with bits CR5. active prefilter then precedes order band pass switched capacitor filter. converter either 14-bit linear (bit register CR0) have compressing characteristics (bit register CR0) according CCITT MU255 coding laws. precision chip voltage reference ensures accurate highly stable transmission levels. offset voltage arising gain-set amplifier, filters comparator cancelled internal autozero circuit. Each encode cycle begins immediatly beginning selected Transmit time slot. total signal delay referenced start time slot approximatively (due transmit filter) plus (due encoding delay), which totals Voice data shifted during selected time slot transmit rising edges MCLK delayed non-delayed normal mode falling edges MCLK non-delayed reverse mode.
Power up/down control: Following power-on initialization, power power down control accomplished writing control instructions listed Table into ST5092 with power power down. Normally, recommended that programmable functions initially programmed while device powered down. Power state control then included with last programming instruction separate single byte instruction. programmable registers also modified while ST5092 powered down setting indicated. When power down control entered single byte instruction, must When power command given, de-activated circuits activated, output will remain high impedance state until second pulse after power Power down state: Following period activity, power down state reentered writing power down instruction. Control Registers remain their current state changed MICROWIRE control interface. addition power down instruction, detection loss MCLK transition detected) automatically enters device "reset" power down state with output high impedance state. Transmit section: Transmit analog interface designed stages enable gains 42.5 realized. Stage noise differential amplifier providing gain. microphone capacitevely connected MIC1+, MIC1- inputs, while MIC2+ MIC2- MIC3+ MIC3- inputs used capacitively connect second microphone third microphone respectively auxiliary audio circuit. MIC1 MIC2 transmit mute selected with bits register CR4.
Receive section:
Voice Data shifted into decoder's Receive voice data Register during selected time slot falling edges MCLK delayed non-delayed normal mode rising edges MCLK non-delayed reverse mode. decoder consists either 14-bit linear expanding with MU255 decoding characteristic. Following Decoder 3400 order band-pass switched capacitor filter with integral correction sample hold. dBmO voltage this reference point (see Block Diagram description) 0.49 Vrms. transcient suppressing circuitry ensure interference noise suppression power analog speech signal output routed either earpiece (VFR+, VFR- outputs) extra analog output (VLr+, VLr- outputs) setting bits CR4). Total signal delay approximatively (filter plus decoding delay) plus 62.5 (1/2 frame) which gives approximatively Differential outputs VFR+,VFR- intended directly drive earpiece. Preceding outputs programmable attenuation amplifier, which must
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ST5092
writing bits register CR6. Attenuations range relative maximum level step programmed. input this programmable amplifier several signals which selected writing register CR4.: Receive speech signal which been decoded filtered, Internally generated tone signal, (Tone amplitude programmed with bits register CR7), Sidetone signal, amplitude which programmed with bits register VFR+ VFR- outputs capable driving output power level 66mW into differentially connected load impedance Piezoceramic receivers 50nF also driven. Differential outputs VLr+,VLr- intended directly drive extra output. Preceding outputs programmable attenuation amplifier, which must writing bits register CR6. Attenuations range relative maximum level step programmed. input this programmable amplifier signals which selected writing register CR4: Receive speech signal which been decoded filtered, Internally generated tone signal, (Tone amplitude programmed with bits register CR7), Sidetone signal, amplitude which programmed with bits register CR5. VLr+ VLr- outputs capable driving output power level 66mW into differentially connected load impedance Piezoceramic receivers 50nF also driven. BUZZER OUTPUT: Single ended output intended drive buzzer, external BJT, with squarewave pulse width modulated (PWM) signal frequency which stored into register CR8. some applications also possible amplitude modulate this signal with squarewave signal having frequency stored register CR9. Maximum load 50pF. delayed data mode similar long frame timing ST5080A: first time slot begins nominally coincident with rising edge Alternative delayed data mode, which similar short frame sync timing ST5080A, which input must high least half cycle MCLK earlier frame beginning. case companded code only (bit register CRO) time slot assignment circuit chip used with timing modes, allowing connection voice data channels. data formats available: Format time slot corresponds MCLK cycles following immediately rising edge while time slot corresponds MCLK cycles following immediately time slot Format time slot identical Format Time slot appears slots after time slot This bits space left available insertion channel data. Data format selected register CR0. Time slot selected Control Register CR1. control register enables disables voice data transfer appropriate. During assigned time slot, output shifts data from voice data register rising edges MCLK case delayed non-delayed normal modes falling edges MCLK case non-delayed reverse mode. Serial voice data shifted into input during same time slot falling edges MCLK case delayed nondelayed normal modes rising edges MCLK case non-delayed reverse mode. high impedance Tristate condition when selected time slots.
Control Interface:
Control information data written into readback from ST5092 serial control port consisting control clock CCLK, serial data input output Chip Select input, CS-. control instructions require bytes listed Table with exception single byte powerup/down command. shift control data into ST5092, CCLK must pulsed high times while low. Data input shifted into serial input register rising edge each CCLK pulse. After data shifted content input shift register decoded, indicate that byte control data will follow. This second byte either defined second byte-wide CSpulse follow first contiguously, i.e. mandatory return high between first second control bytes. control byte, data loaded into
Digital Interface (Fig. Frame Sync input determines beginning frame. have duration from single cycle MCLK squarewave. Three different relationships established between Frame Sync input first time slot frame setting bits register CR1.
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ST5092
Figure Digital Interface Format
FORMAT
(delayed timing)
(non delayed timing)
MCLK
FORMAT
(delayed timing)
(non delayed timing)
MCLK
D93TL075
Significant Only Companded Code.
propriate programmable register. must return high byte. read-back status information from ST5092, first byte appropriate instruction strobed during first pulse, defined Table must further CCLK cycles, during which data shifted falling edges CCLK. When high, high impedance Tri-state, enabling pins several devices multiplexed together. Thus, summarise, byte READ WRITE instructions either 8-bit wide CSpulses single wide pulse.
Control channel access interface: possible access channel previously
selected Register case companded code only. byte written into Control Register will automatically transmitted from output following frame place transmit data. byte written into Control Register will automatically sent through receive path Receive amplifiers. order implement continuous data flow from Control MICROWIRE interface channel, necessary send control byte each frame. current byte received input read register CR2. order implement continuous data flow from channel MICROWIRE interface, necessary read register each frame.
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PROGRAMMABLE FUNCTIONS both formats Digital Interface, programmable functions configured writing number registers using 2-byte write cycle. Most these registers also read-back
verification. Byte always register address, while byte Data. Table lists register their respective adresses.
Table Programmable Register Intructions
Function Single byte Power up/down Write Read-back Write Read-back Write Data receive path Read data from Write Data Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back Write CR10 Read-back CR10 Write CR11 Read-back CR11 Write Test Register CR14 Address byte Data byte
none TABLE TABLE TABLE TABLE TABLE
TABLE TABLE TABLE TABLE TABLE CR10 TABLE CR10 CR11 TABLE CR11 reserved
NOTE
address byte data byte always first clocked into from: pins when MICROWIRE serial port enabled. reserved: write Power up/down Control bit. Means Power Down. indicates, set, presence second byte. write/read select bit. Registers CR12, CR13, CR15 accessible.
NOTE NOTE NOTE
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ST5092
Table Control Register Functions
MCLK MCLK 1.536 MCLK 2.048 MCLK 2.560 Linear code Companded code Linear Code 2-complement sign magnitude 2-complement 1-complement consecutive separated bits time-slot bits time-slot Normal operation Digital Loop-back Function
Companded Code MU-law: CCITT D3-D4 MU-law: Bare Coding A-law including even inversion A-law: Bare Coding
(1):
state power initialization significant companded mode only
Table Control Register Functions
Function delayed data timing non-delayed normal data timing non-delayed reverse data timing latch latch connected rec. path connected rec. path Trans path connected connected voice data transfer disable voice data transfer enable channel selected channel selected
(1):
state power initialization significant companded mode only reserved: write
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Table Control Register Functions
Significant companded mode only.
Function Data sent Receive path Data received from input
Table Control Registers Functions
Significant companded mode only
data transmitted
Function
Table Control Register Functions
Transmit input muted MIC1 Selected MIC2 Selected MIC3 Selected Internal sidetone disabled Internal sidetone enabled Receive output muted output selected output selected ALLOWED Ring Tone disabled Ring Tone enabled Receive filter enabled Receive filter disabled Receive Signal disabled Receive Signal enabled Function
state power initialization reserved: write
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ST5092
Table Control Register Functions
state power initialization
gain gain step 22.5 gain
Transmit amplifier
Sidetone amplifier
Function
-12.5 gain -13.5 gain step -27.5 gain
Table Control Register Functions
Function gain gain step gain
state power initialization
Earpiece ampifier [EARA]
Extra amplifier [EXTA]
gain gain step gain
Table Control Register Functions
Tone gain
(2): state power initialization value provided selected alone. selected summed mode, f1=0.89 while f2=0.7 Vpp. reserved: write
Attenuation muted selected selected summed mode
Function .1.6(2)
1.26(2)
0.066
0.053
Squarewave signal selected Sinewave signal selected Normal operation Tone Ring Generator connected Transmit path
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Table Control Register Functions
Function Binary equivalent decimal number used calculate
Table Control Register Functions
Function Binary equivalent decimal number used calculate
Table Control Register CR10 Functions
Default values inserted into Register Power reserved, write
Function
Standard Frequency Tone Range Halved Frequency Tone Range Doubled Frequency Tone Range Forbidden
Table Control Register CR11 Functions
Function Buzzer output disabled (set Buzzer output enabled
state power initialization
Duty Cycle intended relative width logic Duty cycle intended relative width logic Binary equivalent decimal number used calculate duty cycle.
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ST5092
CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Master Clock Frequency Selection master clock must provided ST5092 operation filter coding/decoding functions. MCLK frequency either kHz, 1.536 MHz, 2.048 2.56 MHz. must during initialization select correct internal divider. Default value kHz. clock different from default must selected prior Power-Up instruction. Coding Selection Bits permit selection Mu-255 coding with without even inversion companded code (bit selected. Bits MA(4) IA(3) permit selection 2-complement, 1-complement sign magnitude linear code (bit selected. Coding Selection permits selection either linear coding (14-bit) companded coding (8-bit). Default value linear coding. Digital Interface format FF(2) selects digital interface Format where channel consecutive. FF=1 selects Format where channel separated bits. (See digital interface format section.) 56+8 selection 'B7' selects capability ST5092 take into account only seven most significant bits data byte selected. When 'B7' set, ignored high impedance. This function allows connection external band" data generator directly connected Digital Interface. Digital loopback Digital loopback mode entered setting bit(0) equal Digital Loopback mode, data written into Receive Data Register from selected received time-slot read-back from that Register selected transmit time-slot decoding encoding takes place this mode. Transmit Receive amplifier stages muted. CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Digital Interface Timing DM1(7) selects digital interface delayed timing mode, while selects non-delayed normal data timing mode, selects non-delayed reverse data timing mode. Default delayed data timing. Latch output control controls directly logical status latch output "ZERO" written puts output logical while "ONE" written sets output zero. Microwire access channel receive path selects access from MICROWIRE Register Receive path. When high, data written register decoded each frame, sent receive path data input ignored. other direction, current data input received read from register each frame. Microwire access channel transmit path selects access from MICROWIRE write only Register output. When high, data written output every frame output encoder ignored.
Significant companded mode only
full scale full scale
True even inversion
without even inversion
always first shifted ST5092.
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Transmit/Receive enabling/disabling 'EN' enables disables voice data transfer pins. When disabled, data from decoded time-slots high impedance Default value disabled. B-channel selection TS(1) permits selection between channels. Default value channel. CONTROL REGISTER Data sent receive path data received from input. Refer MR(4) "Control Register CR1" paragraph. CONTROL REGISTER data transmitted. Refer MX(3) "Control Register CR1" paragraph. CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Transmit Input Selection MIC1 MIC2 MIC3 transmit mute selected with bits TE). Transmit gain adjusted within 22.5 range step with Register CR5. Sidetone Selection "SI" enables disables Sidetone circuitry. When enabled, sidetone gain adjusted with Register (CR5). When Transmit path disabled, sidetone circuit also disabled. Output Driver Selection Bits OE1(4) OE2(3) provide selection among earpiece output extra amplifier output both outputs muted. allowed. Ring/Tone signal selection provide select capability connect on-chip Ring/Tone generator either extra amplifier input earpiece amplifier input. Receive High Pass Filter Selection provide selection receive high pass filter cutoff frequency. receive data selection Bits "SE" provide select capability connect received speech signal either extra amplifier input earpiece amplifier input. CONTROL REGISTER First byte READ WRITE instuction Control Register shown TABLE Second byte shown TABLE Transmit gain selection Transmit amplifier programmed gain from 22.5dB 1.5dB step with bits dBmO level output transmit amplifier reference point) 0.492 Vrms (overload voltage 0.707 Vrms). Sidetone attenuation selection Transmit signal picked after switched capacitor pass filter back into both Receive amplifiers. Attenuation signal output sidetone attenuator programmed from -12.5dB -27.5dB relative reference point step with bits CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Earpiece amplifier gain selection: Earpiece Receive gain programmed step from relative maximum with bits dBmO voltage output amplifier pins VFr+ VFr- then 1.965 Vrms when gain selected down 61.85 Vrms when -30dB gain selected. Extra amplifier gain selection: Extra Receive amplifier gain programmed step from relative maximum with bits dBmO voltage output amplifier pins VLr+ VLr- 1.965 Vrms when gain selected down 61.85 mVrms when gain selected. CONTROL REGISTER CR7: First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE
Significant companded mode only
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Tone/Ring amplifier gain selection Output level Ring/Tone generator, before attenuation programmable attenuator Vpkpk when generator selected alone summed with generator 1.26 Vpk-pk when generator selected alone. Selected output level attenuated down programmable attenutator setting bits Frequency mode selection Bits 'F1' 'F2' permit selection and/or frequency generator according TABLE When selected, output Ring/Tone squarewave sinewave) signal frequency selected CR9) Register. When selected summed mode, output Ring/Tone generator signal where frequency summed. order meet DTMF specifications, output level attenuated relative output level. Frequency temporization must controlled microcontroller. Waveform selection 'SN' selects waveform output Ring/Tone generator. Sinewave squarewave signal selected. DTMF selection permits connection Ring/Tone/DTMF generator Transmit Data path instead Transmit Amplifier output. Earpiece extra receive output feed-back provided sidetone circuitry setting directly setting Register CR4. Loudspeaker feed-back provided directly setting Register CR4. CONTROL REGISTERS First byte READ WRITE instruction Control Register shown TABLE Second byte respectively shown TABLE "standard frequency tone range" selected, Tone Ring signal frequency value defined formula: 0.128 0.128 where decimal equivalents binary values registers respectively. Thus, frequency between 1992 selected step. "halved frequency tone range"is selected, Tone Ring signal frequency value defined formula: 0.256 0.256 This frequency between 3.9Hz 996Hz selected 3.9Hz step. "doubled frequency tone range"is selected, Tone Ring signal frequency value defined formula: 0.064 0.064 Thus frequency between 15.6Hz 3984Hz selected 15.6Hz step. TABLE gives examples main frequencies usual Tone Ring generation. CONTROL REGISTER CR10 DFT(1) HFT(0) permits selection among "standard frequency tone range" (i.e. from 7.8Hz 1992Hz 7.8Hz step), "halved frequency tone range" (i.e. from 3.9Hz 996Hz 3.9Hz step), "doubled frequency tone range" (i.e. from 15.6Hz 3984Hz 15.6Hz step) according values described CONTROL REGISTER CR9. CONTROL REGISTER CR11 BE(7) permits connection squarewave Ring signal, amplitude modulated squarewave signal, buzzer driver output Bits define duty cycle squarewave, according following formula: Duty Cycle CR11(5 0.78125% where CR11(5 decimal equivalent binary value BZ0. When bits register CR7, ring signal present buzzer output, while bits register ring signal also amplitude modulated squarewave frequency. allows chose logic level which duty cycle referred: means that duty cycle intended relative width logic1, while means that duty cycle intended relative width logic When during power down)
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Table Examples Usual Frequency Selection (Standard frequency tone range)
Description Tone Tone Tone Tone Tone Tone 1330 DTMF DTMF DTMF DTMF DTMF 1209 DTMF 1336 DTMF 1477 DTMF 1633 flat sharp sharp value (decimal) Theoretic value (Hz) 1330 1209 1336 1477 1633 523.25 587.33 622.25 659.25 698.5 830.6 987.8 1046.5 1174.66 1318.5 Typical value (Hz) 328.2 421.9 437.5 796.9 1328.1 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 Error -.56 -.73 -.56 -.39 -.14 -.24 +.44 -.05 -.37 +.16 -.01 -.30 -.56 -.34 +.04 -.23 +.45 -.45 -.45 +.30 -.34 -.29 +.33 -.34 +.04 -.23 +.14
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TIMING DIAGRAM Delayed Data Timing Mode (Normal)
Delayed Data Timing Mode
case companded code timing applied bits instead bits (see ST5080A data sheet)
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TIMING DIAGRAM (continued) Delayed Reverse Data Timing Mode
tHMFR
tWMM
MCLK
tSFMR tHMFR
tWML
tDFD tDMDR tDMZR
tSDM tHMDR
D93TL076A
case companded code timing applied bits instead bits.
Serial Control Timing (MICROWIRE MODE)
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage (VCC 3.6V) Current Current digital output Voltage digital input (VCC 3.6V); limited 50mA Storage temperature range Lead Temperature (wave soldering, 10s) Value Unit
TIMING SPECIFICATIONS (unless otherwise specified, 2.7V 3.6V, -30°C 85°C typical characteristics specified 3.0V, signals referenced GND, Note timing definitions) NOTICE: timing specifications changed. MASTER CLOCK TIMING
Symbol fMCLK Parameter Frequency MCLK Test Condition Selection frequency programmable (see table Min. Typ. 1.536 2.048 2.560 Max. Unit
tWMH tWML
Period MCLK high Period MCLK Rise Time MCLK Fall Time MCLK
Measured from Measured from Measured from Measured from
INTERFACE TIMING
Symbol tHMF tSFM tDMD tDMZ tDFD Parameter Hold Time MCLK Setup Time, high MCLK Delay Time, MCLK high data valid Delay Time, MCLK disabled Delay Time, high data valid Load Applies only rises later than MCLK rising edge Delayed Mode only Load 100pF Load Test Condition Min. Typ. Max. Unit
tSDM tHMD tHMFR tSFMR tDMDR tDMZR tHMDR
Setup Time, valid MCLK receive edge Hold Time, MCLK invalid Hold Time MCLK High Setup Time, high MCLK High Delay Time, MCLK data valid Delay Time, MCLK High disabled Hold Time, MCLK High invalid
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SERIAL CONTROL PORT TIMING
Symbol fCCLK tWCH tWCL tHCS tSSC tSDC tHCD tDCD tDSD tDDZ Parameter Frequency CCLK Period CCLK high Period CCLK Rise Time CCLK Fall Time CCLK Hold Time, CCLK high Setup Time, CCLK high Setup Time, valid CCLK high Hold Time, CCLK high invalid Delay Time, CCLK data valid Delay Time, CS-low data valid Delay Time CS-high CCLK high impedance whichever comes first Hold Time, CCLK high high Time, high CCLK high
signal valid above below invalid between VIH. purpoes this specification following conditions apply: input signal defined 0.2VCC, 0.8VCC, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid.
Test Condition Measured from Measured from Measured from Measured from
Min.
Typ.
Max. 2.048
Unit
Load
tHSC tSCS
Note
ELECTRICAL CHARACTERISTICS (unless otherwise specified, 2.7V 3.6V, --30°C 85°C typical characteristic specified 3.0V, 25°C signals referenced GND) DIGITAL INTERFACES
Symbol Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Input Current Input High Current Output Current High impedance (Tri-state) Test Condition digital inputs digital inputs digital outputs, 10µA digital outputs, digital outputs, 10µA digital outputs, digital input, digital input, Min. 0.7VCC 0.8VCC VCC-0.1 VCC-0.4 Typ. Max. 0.3VCC 0.2VCC Unit
A.C. TESTING INPUT, OUTPUT WAVEFORM
INTPUT/OUTPUT
0.8VCC 0.7VCC TEST POINTS 0.2VCC 0.3VCC 0.3VCC
D93TL077
0.7VCC
Testing: inputs driven 0.8VCC logic "1"and 0.2VCC logic Timing measurements made 0.7VCC logic "1"and 0.3VCC logic "0".
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ST5092
ANALOG INTERFACES
Symbol IMIC RMIC RLVFr CLVFr ROVFr0 VOSVFr0 Parameter Input Leakage Input Resistance Load Resistance Load Capacitance Output Resistance Differential offset: Voltage VFr+, VFrLoad Resistance Load Capacitance Output Resistance Differential offset Voltage VLr+, VLrTest Condition VMIC VMIC VFr+ VFrFrom VFr+ VFrSteady zero code applied Alternating zero code applied maximum receive gain; VLr+ VLrfrom VLr+ VLrSteady zero code applied Alternating zero code applied maximum receive gain; -100 -100 Min. -100 +100 Typ. Max. +100 Unit
RLvLr CLvLr ROLVrO VOSVLrO
+100
application note connections.
POWER DISSIPATION
Symbol ICC0 ICC1 Parameter Power down Current Power Current Test Condition CCLK,CI 0.1V; VCC-0.1V VLr+, VLr- VFr+, VFr- loaded Min. Typ. Max. Unit
TRANSMISSION CHARACTERISTICS (unless otherwise specified, 2.7V -30°C typical characterist specif 3.0V, 25°C, MIC1/ 0dBm0, -6dBm0 code, 1015.625 signal referenced GND) AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Transmit path Absolute levels MIC1 MIC2 MIC3
Parameter dBm0 level Overload level dBm0 level Overload level Transmit Amps connected 42.5dB gain Test Condition Transmit Amps connected 20dB gain Min. Typ. 49.26 70.71 3.694 5.302 Max. Unit mVRMS mVRMS mVRMS mVRMS
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ST5092
TRANSMISSION CHARACTERISTICS (continued) AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Receive path Absolute levels (Differentially measured)
Parameter dBM0 level dBM0 level Test Condition Receive programmed gain Receive programmed 30dB attenuation Min. Typ. 1.965 61.85 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Receive path Absolute levels (Differentially measured)
Parameter dBM0 level dBM0 level Test Condition Receive programmed gain Receive programmed 30dB gain Min. Typ. 1.965 61.85 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE Transmit path
Symbol Parameter Transmit Gain Absolute Accuracy Test Condition Transmit Gain Programmed minimum. Measure deviation Digital Code from ideal 0dBm0 code Measure Transmit Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GXA, i.e. GAXG actual prog. Measured relative GXA. min. gain Max. gain Measured relative Minimum gain Relative 1015,625 multitone test technique used. min. gain Max. gain 3000 3400 4000 4600 8000 Sinusoidal Test method. Reference Level dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 Min. -0.5 Typ. Max. Unit
GXAG
Transmit Gain Variation with programmed gain
-0.5
GXAT GXAV GXAF
Transmit Gain Variation with temperature Transmit Gain Variation with supply Transmit Gain Variation with frequency
-0.1 -0.1
-1.5 -0.5 -1.5
GXAL
Transmit Gain Variation with signal level
-0.5 -0.5 -1.2
limit frequencies between 4600Hz 8000Hz lies straight line connecting frequencies linear (dB) scale versus (Hz) scale.
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ST5092
AMPLITUDE RESPONSE Receive path
Symbol GRAE Parameter Receive Gain Absolute Accuracy Test Condition Receive gain programmed maximum Apply dBm0 code Measure VFr+ Receive gain programmed maximum Apply dBm0 code Measure VLr+ Measure Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRAE, i.e. GRAGE actual prog. GRAE Measure Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRAL, i.e. GRAGL actual prog. GRAL Measured relative GRA. (VLr VFr) min. gain Max. gain Measured relative GRA. (VLr VFr) Maximum Gain Relative 1015,625 multitone test technique used. min. gain Max. gain 60Hz 100Hz 3000 3400 4000 Relative 1015,625 multitone test technique used. min. gain Max. gain 50Hz 3000 3400 4000 Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 Min. -0.5 Typ. Max. Unit
GRAL
Receive Gain Absolute Accuracy
-0.5
GRAGE
Receive Gain Variation with programmed gain
-0.5
GRAGL
Receive Gain Variation with programmed gain
-0.5
GRAT
Receive Gain Variation with temperature Receive Gain Variation with Supply Receive Gain Variation with frequency (VLr VFr)
-0.1
GRAV
-0.1
GRAF
-1.5 -0.5 -1.5
Receive Gain Variation with frequency (VLr VFr)
-1.5 -0.5 -1.5
GRAL
Receive Gain Variation with signal level (VFr)
-0.5 -0.5 -1.2
GRAL
Receive Gain Variation with signal level (VLr)
-0.5 -0,5 -1.2
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ST5092
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol Parameter Delay, Absolute Delay, Relative Test Condition 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 1000 1000 1600 1600 2600 2600 2800 2800 3000 Min. Typ. Max. Unit
Delay, Absolute Delay, Relative
1600
NOISE
Symbol Parameter Noise, weighted 35dB) Noise, weighted (max. gain) Noise, Single Frequency Test Condition VMIC Receive code Positive Zero Loop-around measurament from mVrms; 50KHz Code equals Positive Zero, mVrms, input dBm0 code 3400 Input Code applied 4600 5600 5600 7600 7600 8400 Min. Typ. Max. Unit dBm0p µVrms dBm0
PPSRx
PSRR,
PPSRp
PSRR,
Spurious Out-Band signal output
Weighted
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ST5092
DISTORTION
Symbol STDX Parameter Signal Total Distortion 35dB gain) Typical values measured with 30.5dB gain Test Condition Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 dBm0 input signal Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 dBm0 input signal Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 dBm0 input signal Loop-around measurement Voltage dBm0 dBm0, Frequencies range 3400 Min. 37.5 28.5 Typ. Max. Unit
SDFx STDRE
Single Frequency Distortion transmit Signal Total Distortion (VFr) 20dB attenuation) Typical values measured with 20dB attenuation.
SDFr STDRL
Single Frequency Distortion receive (VFr) Signal Total Distortion (VLr) 20dB attenuation) Typical values measured with 20dB attenuation
SDLr
Single Frequency Distortion receive (VLr) Intermodulation
limit curve shall determined straight lines joining successive coordinates given table. Lower limits used during automatic testing avoid unrealistic yield loss ±2dB imprecision time-limited noise measurements.
CROSSTALK
Symbol CTx-r Parameter Transmit Receive Test Condition Transmit Level dBm0, 3400 Quiet Code Receive Level dBm0, 3400 Min. Typ. -100 Max. Unit
CTr-x
Receive Transmit
25/29
ST5092
APPLICATIONS Application Note Microphone Connections
ST5092
ST5092
ST5092
Application Note Connections
DYNAMIC RECEIVERS (32) VFr+ VFr+ VFr+ CERAMIC RECEIVERS (50nF) DYNAMIC/CERAMIC RECEIVERS (REVERSIBLE)
VFr-
VFr-
VFr-
ST5092 ST5090
VLr+
ST5090 ST5092
VLr+ VLr+
ST5090 ST5092
VLr-
VLr-
VLr-
D93TL078A
must greater than higher capacitive transducers, lower values used.
POWER SUPPLIES While pins ST5092 device well protected against electrical misuse, recommended that standard CMOS practise applying before other connections made should always followed. applications where printed circuit card plugged into socket with power clocks already present, extra long ground connector should
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used. minimize noise sources, ground connections each device should meet common point close possible order prevent interaction ground return currents flowing through common impedance. power supply decoupling capacitor should connected from this common point close possible device pins.
ST5092
MIN. 0.45 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030 0.055 0.014 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
DIM.
OUTLINE MECHANICAL DATA
TQFP44
0°(min.), 3.5°(typ.), 7°(max.)
0.10mm .004 Seating Plane
TQFP4410
27/29
ST5092
DIM. MIN. 4.445 15.2 2.54 33.02 14.1 0.23 1.27 37.34 16.68 0.598 TYP. 0.63 0.45 0.31 0.009 MAX. MIN.
inch TYP. 0.025 0.018 0.012 0.050 1.470 0.657 0.100 1.300 0.555 0.175 MAX.
OUTLINE MECHANICAL DATA
DIP28
0.130
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ST5092
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2003 STMicroelectronics rights reserved STMicroelectronics GROUP COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
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