HCMOS8D 0.18µm Standard Cells Family FEATURE 0.18 micron drawn, l
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CB65000 Series
HCMOS8D 0.18µm Standard Cells Family
FEATURE 0.18 micron drawn, layers metal connected fully stackable vias contacts, Shallow Trench Isolation, resistance, salicided active areas gates. Deep lithography. optimized High Performance Leakage transistors with supply interface capability. Average gate density: 85K/mm plus power consumption 30nanoWatt/Gate/MHz/ Stdload. input NAND delay 35ps with High Performane transistor 60ps with Leakage transistor. Library available commercial, industrial military temperature range. Power supply ranging from 1.2V 1.95V Core (according JESD specification) between 3.0V 3.6V I/Os (alligned with JESD specification). Broad functionality including: Voltage CMOS. Voltage TTL,HSTL, SSTL. USB, PCI, LVDS interfaces also available. Drive capability buffer with slew rate control, current spike suppression impedance matching, process compensation capability reduce delay variation. Designs easily portable from previous generations CB55000 with average factor density increase, speed improvement power reduction respective nominal voltages.
CB65000 Super Integration Cost Effective Product Architecture partitioning Trouble-free integration Application-specific Your Product Unique User specified cell integration Design confidentiality fully re-usable pitch linear staggered libraries. Fully independent power ground configuration core I/Os supported. ring capability 1500 pads. Latch-up trigger current protection above H.B.M. Oscillators PLLs wide frequency spectrum. Broad range more than cells. Design test features including IEEE 1149.1 JTAG Boundary Scan architecture. Synopsys, Cadence Mentor based design systems with interface from multiple workstations. Broad range packaging solutions, including PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP, PLCC 1000 pins with enhanced power dissipation options. 1.25 GigaHertzGigabit technique.
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Generators support Single Port, Dual port multiple Port RAM, ROMs with BIST options. Extensive embedded function library including micro-cores, third-party IPs, Synopsys Mentor Inventra synthetic libraries ideally suited complete System Chip fast integration Embedded DRAM Capability
March 2002
CB65000 SERIES
Figure Process cross section Interconnect perspective view
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CB65000 SERIES
GENERAL DESCRIPTION
CB65000 standard cell series uses high performance, low-voltage, 0.18 drawn, metal levels, high density high speed HCMOS8D process. With average routed gate density 85,000 gates/mm2, CB65000 family allows integration million equivalent gates ideal high-complexity high-performance devices computer, telecommunication consumer products. With gate delay with High Performance transistor with Leakage transistor (for 2-input NAND gate fan-out library meets most demanding speed requirements telecommunication computer application designs today. Optimized operation, library features power consumption less than nW/Gate/MHz (High Performance; fan-out=1) nW/Gate/MHz (Low Leakage; fan-out=1) buffers fully configured both interface options, with several high speed buffer types available. These include: voltage differential (LVDS) I/Os, PCI, AGP, USB, LVTTL, LVCMOS SSTL. pitch down staggered arrangement, meets requirements high pin-count devices which tend become pad-limited such library densities. very high pin-count ICs, advanced solutions such Ball Grid Array packages available. packaging solutions using flip-chip approach currently being developed. Figure HCMOS8D Front cross section
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CB65000 SERIES
TECHNOLOGY OVERVIEW
advanced HCMOS8D transistor architecture: 0.18 very thin gate oxide: Amstrong, optimized threshold voltages salicided source, drain, gate leads intrinsically high performances both channel channel driving currents. major scaling factor obtained through deep lithography most masking levels, making sub-micron pitch reality. Further integration process front-end comes from Shallow Trench Isolation process between active regions, both improving density planarity transistors. order allow full utilization such transistor density, levels metal made available routing. local interconnection level made Tungsten, allows short interconnection silicon layer improving memory cell density., while metal levels resistivity aluminum long range interconnection power distribution. Figure HCMOS8D Local Interconnect
thick inter-level dielectric completely planarized Chemical Mechanical Polishing, which provides defect-free isolation between stripes within same well between different levels. Usage Tungsten plugs contacts vias allows extremely dense reliable interconnection between metal layers. These vias contacts fully stackable, providing direct vertical electrical connection from active level sixth metal level. This efficient interconnect scheme makes routing fast easy, well having very positive impact high gate count, random-logic blocks density routability. combination both high drive dense transistors, easily interconnected with fine-pitch metal levels isolated thick dielectric leads optimum gate density, with parasitic resistance capacitance. This results very short interconnected gate delay minimized power consumption. Figure
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CB65000 SERIES
LIBRARY
CB55000 library organized into three categories: cell library cell library Macrofunctions Cell Library Overview design CB65000 family been optimized allow extremely high density, high speed power designs. these reasons, wide range cells with different ranges driving capabilities available library. library cells have been optimized terms functional electrical parameters, order have: Good balancing Maximum speed Optimum threshold voltage Symmetric Vdd/Vss noise margins Minimum power-speed value geometrical aspect cells configured allow extremely dense design, fully exploiting features Place Route tool terms horizontal vertical routing grids. Place Route, layers metal utilized; firsts four layers fully available signal routing, while fifth sixth power distribution, clock bussing routing. Figure examples from CB65000
Core Logic propagation delays shown CB65000 data book given worst case processing 1.55V 125°C will provided design while power data referred fast process model 1.95V -40°C. However, there additional factors that affect delay characteristics cells. These include: loading fanout interconnect routing, supply voltage, junction temperature device, processing tolerance input signal transition time. Prior physical layout, design system estimate delays associated with critical path. impact placement routing accurately back-annotated from layout final simulations critical timing. median effects cells delay junction temperature coefficient) supply voltage coefficient) extracted from real Silicon data.
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CB65000 SERIES
Buffer Libraries basic buffer libraries offered with CB65000, line pitch library staggered library support limited designs. Apart from standard latch-up protections present each I/O, proprietary clamp within each power supply provides proper paths types discharges, efficiently protecting I/Os. result, buffers withstand more than according 883C Human Body Model specification. order limit switching noise keep fixed buffer delay, independent process, supply voltage temperature, compensated active slew rate buffers selected, providing fixed stable dI/dt. order interface with application (from wide range capable input/output buffers (mixable with standard 1.8V ones) chosen. this case rail chip periphery must powered through external supply. True volt tolerant input buffer also available allow different power level managment. Dedicated I/Os special applications have developed, like UDMA Hard Disk Interface LVDS PECL Telecom Standard Peripheral Interface Universal Serial Interface Test Interface cells have dedicated test interface facilitate parametric lddq testing devices. This test interface connects standard core signals dedicated test signals cells allowing output buffers driven high, into tri-state regardless state internal logic. This greatly simplifies parametric testing device also assisting customers wish this feature during board testing. Note that output buffers tri-stated this function including buffers that normally tri-state. This test function also turns pull down resistors, shuts down differential receivers converts them into standard CMOS receivers. This allows lddq test methodologies employed very efficient way, avoiding unneeded circuit overhead. Macrocells CB65000 series internal macrocells that robust variety performance. cell selection been driven need Synthesis HDL-based design techniques. This offering rich buffers, complex combination cells multi-power drive cells, which allow Synthesis tool create netlist compatible with requirements Place Route tools. Macrofunctions series soft-macros facilitating quick capture large functional blocks available such functions counters, shift registers adders. Macrofunctions implemented layout utilizing macrocells interconnecting create logic function. 3.5.1 Module generators series module generators using compiled cell generation techniques available support range megacells. These modules enable designer choose individual parameters order create compiled cell, which meets specific application requirements. These include ROM, single dual port RAM, multiport FIFO, some them specifically optimized speed power. memories have complete standby mode where current consumption limited process leakage. High Density Memories also available fully exploiting technology capability.
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CB65000 SERIES
Table List module generators
Generator Romd RO8L SPS2HD Description High speed Sync. Diffusion Power, High Density Metal programming) High speed Sync. High Density Single port Small cuts Sync. power Single port Power High speed Async. Single port High Density, Multipage, power High speed Single port Power High Density Single Poert High speed Sync. Dual port Power High Density Sync. Dual Port Power Async. Register File High speed (Min.) Kbit (Max) 2048 4096 Word width (Max.)
SPS4
SPS5A
1000
SPS6
1000
4096
byte write
SP8D DPR2
2096
DP8D
DP8E FIFO
Typical case 1.8V 25°C Worst case 1.55V 125°C Characterization range [1.55V 1.95V] [1.2V 1.6V] 3.5.2 MicroLibrary I.P.s MicroLibrary includes extensive portfolio microcores application specific I.P.s; provided through both internal developments partners licensing agreements. short list this portfolio consists General purpose macro functions. Microcores (8,16,32 bits) DSP:D950,ST100, PLL, Frequency synthesizer, Comparators, DAC,ADC (8,10,16 bits). Application specific I.P.s for: Data communications (10/100 PHY, Gigabit,.), Telecommunication (622MHz phase aligner, clock recovery), Computer peripherals Audio (CODEC,.).
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CB65000 SERIES
DESIGN METHODOLOGY
STMicrolectronics (STM) ASIC design flow intended high performance, high complexity submicron ASIC designs. parties tools from leading vendors such Synopsys, Cadence, Mentor Graphics Sproprietary systems integrated into framework free design environment that efficiently supports design phases. hierarchical design methodology with FastLoop, between floorplanning timing-driven placement synthesis/static timing analysis, guarantees fast timing prediction closure after routing. Other features such hierarchical Clock tree synthesis, advanced test methodology, formal verification, parasitic extraction, Crosstalk analysis, IP-reuse, qualifies SASIC design flow industry's leading solutions today's tomorrow's complex designs. Figure
Functional Timing Specification
Description Checks
Behavioural Simulation
Preliminary Floorplan
Synthesis Scan Insertion Floorplan Physical Synthesis SCAN Ordering Routing
Verification Gate Level Full Timing Simulation Functional Formal Verification
Clock Tree Synthesis Routing Optimization
ATPG
Parasitic Extraction
IDDQ Testing
Final Verification Gate Level Full Timing Simulation Functional Formal Verification Test Vectors Final Test Program Generation Final Fault Analysis
Prototype Fabrication
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CB65000 SERIES
DESIGN TESTABILITY
test time cost ASIC testing increases exponentially complexity size ASIC grows. Using design-for-testability methodology allows large, more complex ASICs efficiently economically tested. system level, STMicroelectronics fully supports IEEE 1149.1; structure utilized this family completely compatible. Several types core scan cells provided CB55000 Series library. Examples include FDxS/FJKxS edge sensitive LDxS level sensitive cells. Non-overlapping clock generator macros also available. Test coverage reliability further supported IDDQ (quiescent current) testing; blocks designed "IDDQable" that anomalous leakage metal bridging dielectric defects screened using proper vectors extracted from test patterns. parametric lddq testing, cells contain dedicated test interface described previously (see Section `I/O Test Interface' page
ELECTRICAL SPECIFICATION
Table General Interface Electrical Characteristics
Symbol Vdd3 latchup Vesd Parameter Core Power Supply Voltage Power Supply Voltage Operating Junction Temperature Latch-Up Current Electrostatic Protection Leakage Test Conditions 1.55 4000 1.95 Unit Note
Note Human Body Model
3.3V specifications Table LVTTL Input Specification vdd3 3.6V)
Parameter Vhyst Level Input Voltage High Level Input Voltage Schmitt Trigger Hysteresis Test Conditions Unit
Table LVTTL Output Specification vdd3 3.6V)
Symbol Parameter Level Output Voltage High Level Output Voltage Test Conditions -XmA Unit Note
Note source/sink current under worst case conditions reflected name cell according drive capability.
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CB65000 SERIES
Table Pullup Pulldown Characteristics
Symbol Parameter Pullul current Pulldown current Equivalent pull-up resistance Equivalent pull-down resistance Test Conditions vdd3 vdd3 Unit Kohm Kohm Note
Note condition: vdd3 125°C, process.
condition vdd3 3.6V, -40°C, fast process.
Table IDDQ Current
OUTPUT Typ/25°C/vdd3=3.3V Vdd=1.8V bt2trp_tc I(vdd3) I(vdd) bt4trp_tc I(vdd3) I(vdd) bt8trp_tc I(vdd3) I(vdd) 0.35 0.35 Fast/25°C/vdd3=3.6V Vdd=1.95V 1.95 Fast/125°C/ vdd3=3.6V Vdd=1.95V 1.95 Note
INPUT
Typ/25°C/vdd=1.8 clthc_tc tlchth_tc I(vdd) I(vdd) 0.05 0.15 Fast/25°C/vdd=1.95 Fast/125°C/vdd=1.95
Note that cases I(vdd3) lower than
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CB65000 SERIES
1.8V specification Table Input Specification (1.55V 1.95V)
Symbol Vhyst Parameter level input voltage High level input voltage Schmitt trigger hysteresis 1.26 Test Conditions 0.54 Unit
Table OutputSpecification (1.55V 1.95V)
Symbol Parameter level output voltage High level output voltage Test Conditions -XmA 1.45 0.11 Unit Note
Note source/sink current under worst case conditions reflected name cell according drive capability
Table Pullup Pulldown Characteristics
Symbol Parameter Pullul current Pulldown current Equivalent pull-up resistance Equivalent pull-down resistance Test Conditions Unit Kohm Kohm Note
Note condition: vdd3 125°C, process.
condition vdd3 3.6V, -40°C, fast process
Table IDDQ Current
OUTPUT Typ/25C/vdd=1.8V bt2crp bt4crp bt8crp I(vdd) I(vdd) I(vdd) Fast/25C/vdd=1.95V INPUT ibuf ibuf I(vdd) I(vdd) 0.08 0.07 0.15 1.95 1.95 1.95 Fast/125C/vdd=1.95V 1.95
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CB65000 Series
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics 2002 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan -Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States. http://www.st.com
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