HCMOS7 Standard Cells FEATURE 0.25 micron drawn (0.20 micron effe
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CB55000 Series
HCMOS7 Standard Cells
FEATURE 0.25 micron drawn (0.20 micron effective channel length process), layers metal connected fully stackable vias contacts, Shallow Trench Isolation, resistance, salicided active areas gates. Deep lithography. optimized transistor with supply interface capability. Average gate density: K/mm2, plus power consumption nanoWatt/Gate/MHz/ Stdload. input NAND delay (typical) with fanout=2. Library available commercial, industrial military temperature range with supply ranging from 2.70 down core according EIA/JESD specification. Additional voltage range down very voltage/low power applications supported Broad functionality including: Voltage CMOS. Voltage TTL, PECL, HSTL, SSTL, LVDS, PCI. support interface according EIA/JESD specification. Drive capability buffer with slew rate control, current spike suppression impedance matching, process compensation capability reduce delay variation. Designs easily portable from previous generations CB45000 through cell mapping with average factor density increase, speed increase power reduction respective nominal voltages. Generators support Single Port, Dual port multiple Port RAM, ROMs with BIST options. Extensive embedded function library including micro-cores, third-party IPs, Synopsys Mentor Inventra synthetic libraries ideally suited complete System Chip fast integration pitch linear staggered
DPRAM
ST20
CB55000 Super Integration Cost Effective Product Architecture partitioning
Trouble-free integration Application-specific
Your Product Unique User specified cell integration
Design confidentiality fully re-usable
libraries. Fully independent power ground configuration core I/Os supported. ring capability 1500 pads. Latch-up trigger current protection above H.B.M. Oscillators PLLs wide frequency spectrum. Broad range more than cells. Design test features including IEEE 1149.1 JTAG Boundary Scan architecture. Synopsys, Cadence Mentor based design systems with interface from multiple workstations. Broad range packaging solutions, including BGA, LBGA, TQFP, PQFP, PLCC 1000 pins with enhanced power dissipation options. 1.25 GigaHertzGigabit technique.
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CB55000 Series
Figure Metal perspective view
CMOS 0.25 Shallow Trench Isolation, Tungsten
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CB55000 Series
GENERAL DESCRIPTION
CB55000 standard cell series uses high performance, low-voltage, 0.25 drawn (0.20 effective), metal levels CMOS process HCMOS7 pico-second internal delay while offering very power dissipation high noise immunity. With average routed gate density 30,000 gates/mm2, CB55000 family allows integration million equivalent gates ideal high-complexity high-performance devices computer, telecommunication consumer products. With typical gate delay (for 2-input NAND gate fan-out library meets most demanding speed requirements telecommunication computer application designs today. Optimized operation, library features power consumption less than nW/Gate/MHz (fanout=1) nW/Gate/MHz (fan-out=1) buffers fully configured both interface options, with several high speed buffer types available. These include: voltage differential (LVDS) I/Os, PCI/AGP, PECLs, HSTL. pitch down staggered arrangement, meets requirements high pin-count devices which tend become pad-limited such library densities. very high pin-count ICs, advanced packaging solutions such Chip Scale Packaging fine pitch available. packaging solutions using flip-chip approach currently being developed. Figure HCMOS7 Front cross section
gate length: 0.25 Shallow Trench Isolation, Tungsten
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CB55000 Series
TECHNOLOGY OVERVIEW
advanced HCMOS7 transistor architecture: 0.25 drawn length 0.20 effective length, very thin gate oxide: nanometers, optimized threshold voltages salicided source, drain, gate leads intrinsically high performances both channel channel driving currents. major scaling factor obtained through deep lithography most masking levels, making sub-micron pitch reality. Further integration process front-end comes from Shallow Trench Isolation process between active regions, both improving density planarity transistors. order allow full utilization such transistor density, levels metal made available routing. first metal level Tungsten local interconnection, while other five metal levels resistivity aluminum long range interconnection power distribution. thick inter-level dielectric completely planarized Chemical Mechanical Polishing, which provides defect-free isolation between stripes within same well between different levels. Usage Tungsten plugs contacts vias allows extremely dense reliable interconnection between metal layers. These vias contacts fully stackable, providing direct vertical electrical connection from active level sixth metal level. This efficient interconnect scheme makes routing fast easy, well having very positive impact high gate count, random-logic blocks density routability. combination both high drive dense transistors, easily interconnected with fine-pitch metal levels isolated thick dielectric leads optimum gate density, with parasitic resistance capacitance. This results very short interconnected gate delay minimized power consumption. Figure HCMOS7 Back Cross Section
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CB55000 Series
LIBRARY
CB55000 library organized into three categories: cell library cell library Macrofunctions Cell Library Overview design CB55000 family been optimized allow extremely high density, high speed power designs. these reasons, wide range cells with different ranges driving capabilities available library. library cells have been optimized terms functional electrical parameters, order have: Good balancing Maximum speed Optimum threshold voltage Symmetric Vdd/Vss noise margins Minimum power-speed value geometrical aspect cells configured allow extremely dense design, fully exploiting features Place Route tool terms horizontal vertical routing grids. Place Route, layers metal utilized; first metal layer dedicated intracell wiring, second layer power distribution routing, third forth layers routing, fifth sixth power distribution, clock bussing routing. Figure figure from CB55000
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CB55000 Series
Core Logic propagation delays shown CB55000 data book given nominal processing, 25°C temperature. However, there additional factors that affect delay characteristics cells. These include: loading fanout interconnect routing, supply voltage, junction temperature device, processing tolerance input signal transition time. Prior physical layout, design system estimate delays associated with critical path. impact placement routing accurately back-annotated from layout final simulations critical timing. median effects cells delay junction temperature coefficient) supply voltage coefficient) summarized following tables fixed cell input slope. third factor related process variations minimum median 0.84 best case process maximum median 1.18 worst case process. Table Junction temperature multipliers
Temperature (°C) 1.00 1.09 1.12 1.16 1.20
Table Voltage multipliers
1.80 2.00 2.25 2.50 2.75 1.33 1.21 1.09 1.00 0.94
Buffer Libraries basic buffer libraries offered with CB55000, line pitch library staggered library support limited designs. Apart from standard latch-up protections present each I/O, proprietary clamp within each power supply provides proper paths types discharges, efficiently protecting I/Os. result, buffers withstand more than according 883C Human Body Model specification. order limit switching noise keep fixed buffer delay, independent process, supply voltage temperature, compensated active slew rate buffers selected, providing fixed stable dI/dt 8,16 mA/ns. order interface with application (from wide range capable input/output buffers (mixable with standard 2.5V ones) chosen. this case rail chip periphery must powered through external supply. True volt tolerant input buffer also available with process option.
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CB55000 Series
Test Interface cells have dedicated test interface facilitate parametric lddq testing devices. This test interface connects standard core signals dedicated test signals cells allowing output buffers driven high, into tri-state regardless state internal logic. This greatly simplifies parametric testing device also assisting customers wish this feature during board testing. Note that output buffers tri-stated this function including buffers that normally tri-state. This test function also turns pull down resistors, shuts down differential receivers converts them into standard CMOS receivers. This allows lddq test methodologies employed very efficient way, avoiding unneeded circuit overhead. Macrocells CB55000 series internal macrocells that robust variety performance. cell selection been driven need Synthesis HDL-based design techniques. This offering rich buffers, complex combination cells multi-power drive cells, which allow Synthesis tool create netlist compatible with requirements Place Route tools. Macrofunctions series soft-macros facilitating quick capture large functional blocks available such functions counters, shift registers adders. Macrofunctions implemented layout utilizing macrocells interconnecting create logic function. 3.5.1 Module generators series module generators using compiled cell generation techniques available support range megacells. These modules enable designer choose individual parameters order create compiled cell, which meets specific application requirements. These include ROM, single dual port RAM, multiport FIFO. most above memories, different generators provided, optimized speed optimized power. memories have complete standby mode where current consumption limited process leakage.
Table List module generators
Generator Romd Rom3 SPS2 SPS3 SPS4 Description High speed Sync. Diffusion power Sync. Diffusion High speed Sync. Single port power Sync. Single Port Small cuts Sync. power Single Port power Sync. Single Port High density power voltage High density Sync. Single Port (Min.) Kbit (Max) 2000 Word width (Max.)
SPS5 SPS6
1000 2000
2000 byte write supported
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CB55000 Series
Table List module generators (continued)
Generator SPS2HD Description High speed density High density Sync. Single port High speed Sync. Dual port power Sync. Dual port Asynchronous Reg. file Dual port Multiport High density Sync. High speed (Min.) Kbit (Max) Word width (Max.)
DPR2 DPR3 DP7E MP7A
FIFO
Embedded Volatile Memories (OTP, Flash, with specific process options also under development.
3.5.2 MicroLibrary I.P.s MicroLibrary includes extensive portfolio microcores application specific I.P.s; provided through both internal developments partners licensing agreements. short list this portfolio consists General purpose macro functions. Microcores (8,16,32 bits) DSP:D950,ST100, PLL, Frequency synthesizer, Comparators, DAC,ADC (8,10,16 bits).
Application specific I.P.s for: Data communications (10/100 PHY, Gigabit,.), Telecommunication (622MHz phase aligner, clock recovery), Computer peripherals Audio (CODEC,.).
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CB55000 Series
DESIGN TESTABILITY
test time cost ASIC testing increases exponentially complexity size ASIC grows. Using design-for-testability methodology allows large, more complex ASICs efficiently economically tested. system level, STMicroelectronics fully supports IEEE 1149.1; structure utilized this family completely compatible. Several types core scan cells provided CB55000 Series library. Examples include FDxS/FJKxS edge sensitive LDxS level sensitive cells. Non-overlapping clock generator macros also available. Test coverage reliability further supported IDDQ (quiescent current) testing; blocks designed "IDDQable" that anomalous leakage metal bridging dielectric defects screened using proper vectors extracted from test patterns. parametric lddq testing, cells contain dedicated test interface described previously (see Test Interface' page EVALUATION DEVICE
STMicroelectronics' standard policy, cells macro-blocks fully validated characterized silicon through dedicated test vehicules, before final release library. addition, million-gates evaluation chip: CB55Q, been designed order demonstrate performances qualify global CB55000 library, well verify effectiveness design system. CB55Q packaged Ball Grid Array (BGA) permits accurate characterisation most representative cells from library including buffers, single mixed cell chains (IV, ND2, NR2.),Flip-flops memory cuts from various generators. Typical result ring chain ring oscillator mode show mean between around inverter with standard load toggle frequency above GigaHertz FD2. Figure CB55Q View
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CB55000 Series
Figure CB55Q Silicon ring oscillator characterization
ilicon
Ring illator Charac teriz ation
Cell delay (thl+tlh)/2 (ps)
olt)
PACKAGE AVAILABILITY
CB55000 Series designed that made compatible with types traditional (PLCCs, PQFPs) surface mount packages also more advanced BGAs Profile BGAs. main packaging options include: Plastic Leaded Chip Carriers (PLCC) pins, Metric Quad Flat Pack (xQFP) thin standard, pins including high power dissipation versions with slug spreader. Ball Grid Array package family:
Plastic BGA, 1.27mm ball pitch High performance BGA, 1.27mm ball pitch Flip-Chip BGA, 1.27 ball pitch profile BGA, ball pitch profile Fine pitch BGA. ball pitch Ultra Fine pitch .5mm ball pitch from pins from pins from to1000 pins from pins from pins from pins
diversity count package style gives designer opportunity find best compromise system size, cost performances requirements.
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CB55000 Series
Table Package availability
Package Name PQFP 28x28 with spreader PQFP 10x10 PQFP 14x14 PQFP 14x20 PQFP 28x28 PQFP 28x28 with slug TQFP 10x10 TQFP 14x14 TQFP 20x20 TQFP 24x24 TQFP
Count
PLCC
DESIGN METHODOLOGY
STMicrolectronics (STM) ASIC design flow intended high performance, high complexity submicron ASIC designs. parties tools from leading vendors such Synopsys, Cadence, Mentor Graphics Sproprietary systems integrated into framework free design environment that efficiently supports design phases. hierarchical design methodology with FastLoop, between floorplanning timing-driven placement synthesis/static timing analysis, guarantees fast timing prediction closure after routing. Other features such hierarchical Clock tree synthesis, advanced test methodology, formal verification, parasitic extraction, Crosstalk analysis, IP-reuse, qualifies SASIC design flow industry's leading solutions today's tomorrow's complex designs.
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CB55000 Series
ELECTRICAL SPECIFICATIONS
Table Absolute Maximum Ratings (refer Notes
Symbol Parameters Power Supply Voltage Input Output Voltage Power Supply Voltage Input Output Voltage Value -0.5 -0.5 (Vdd 0.5) -0.5 -0.5 (Vdd3 0.5) Unit
Notes: Referenced Vss. Stresses above those listed under "absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. dedicated power supply needed inputs outputs.
Table Recommended Operating Conditions
Main Supply Normal Range Operating Voltage (refer note Additional Ring Supply Voltage (refer notes Main Supply Extended Range Operating Voltage (refer notes Operating Ambient Temperature Commercial (refer note Industrial (refer note Military (refer note
Notes:
(2.25 2.75 0.3V/-0.6 (2.7 -28% (1.8 2.75
degrees Centigrade degrees Centigrade +125 degrees Centigrade
Commercial, Industrial, Military Conditions. Mandatory buffers only. buffer specifications applicable main supply below 2.25 circuits will operate full specifications with junction temperature +125 degrees centigrade. These junctio temperatures compatible with Commercial Industrial Temperature Ranges. circuits will functional from +150 degrees centigrade junction temperature (military Ambient Temperature Range) will necessary operate published specifications. Only circuits specified operational extended temperature range used when operating Military temperature conditions.
Table General Interface Electrical Characteristics
Symbol Cout Ilatchup Vexd
Parameter level input current without pull-up device High level input current without pull-down device Tri-state output leakage without pull down device Input capacitance Output capacitance capacitance latch-up current Electrostatic protection4
Conditions
Min.
Type
Unit
Vdd2 Leakage
5003 4000
leakage currents generally very small an). value given here, maximum that occur after electrostatic stress pin. Vdd3 buffers. Vdd3 buffers. Human body model.
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CB55000 Series
Table Pull-Up Pull-Down Characteristics
Symbol
Parameter Pull-up current Pull-down current Equivalent pull-up resistance Equivalent pull-down resistance
Conditions Vdd1 Vdd1
Min.
Type
Unit
Vdd3 buffer
Buffer Specifications buffers called "CMOS" buffers. nominal supply voltage 2.25 2.75 However, specifications shown still valid lower voltages. Table Voltage CMOS Input Specifications
Symbol Vhyst
Parameter level threshold (input falling) High level threshold (input rising) level input voltage High level input voltage Schmitt trigger hysteresis level output voltage1 High level output voltage(1)
Conditions Schmitt Schmitt Schmitt input Schmitt input Schmitt input
Min.
Type 0.5*Vdd 0.5*Vdd
Unit
0.26*V 0.7*Vdd 0.23*Vdd 0.15*Vdd 0.85*Vdd
Takes into account 0.075*Vdd voltage drop both supply lines. source/sink current under worst case conditions reflected name cell according drive capability.
output buffers will offered with passive slew rate control process-compensated slew rate control. both cases, typical output current that shown Table Table Slew Rate Versus Drive
Drive (mA): Slew Rate (mA/ns Typical) Active Slew Rate (mA/ns Typical) Typical peak current (mA)
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CB55000 Series
Buffer Specifications buffers comply with JEDEC standard (June, 1994). They also compatible with 74VCX specifications operation. These buffers called "TTL", however they also comply with Voltage CMOS levels. buffers, Vdd(min) 2.25 Vdd(max) 2.75 (core supply). Table LVTTL LVCMOS Input Specifications (2.7 Vdd3
Symbol Vilhyst Vihhyst Vhyst Parameter level input voltage High level input voltage level threshold (input falling) High level threshold (input rising) Schmitt trigger hysteresis 1.35 Conditions Min. Type Unit
Table LVTTL Output Specifications (3.0 Vdd3
Symbol
Parameter level input voltage1,2 High level input voltage1,2
Conditions
Min.
Type
Unit
output buffers functional Vdd3 above specifications guaranteed this voltage. Takes into account voltage drop both supply lines. source/sink current under worst case conditions reflected name cell according drive capability.
Table LVCMOS Output Specifications (2.7 Vdd3
Symbol Parameter level input voltage High level input voltage Conditions -100 Vdd3 Min. Type Unit
Table Slew Rate Versus Drive
Drive (mA): Slew Rate (mA/ns Typical) Typical peak current (mA)
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CB55000 Series
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