3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE

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3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE

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IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V ±0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available SOIC, SSOP, QSOP, TSSOP packages
IDT74ALVCH374
DESCRIPTION:
This octal postive edge-triggered D-type flip-flop built using advanced dual metal CMOS technology. ALVCH374 device particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. positive transition clock (CLK) input, outputs logic levels data inputs. buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without interface pullup components. does affect internal operations latch. data retained data entered while outputs high-impedance state. ALVCH374 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH374 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features ALVCH374: High Output Drivers: ±24mA Suitable heavy loads
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
SEVEN OTHER CHANNELS
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4473/-
IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect Terminal Voltage with Respect Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each Storage Temperature Max. +4.6 -0.5 +0.5 ±100 +150 Unit
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SO20-2 SO20-7 SO20-8 SO20-9
VTERM(3) IOUT TSTG
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
SSOP/ TVSOP/ TSSOP/ QSOP VIEW
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
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NOTE: applicable device type.
DESCRIPTION
Names Description 3-State Output Enable Input (Active LOW) Clock Input Data Inputs(1) 3-State Outputs
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
FUNCTION TABLE (each flip=flop)
Inputs
Output
NOTE: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Level before indicated steady-state input conditions were established.
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
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NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
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Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
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Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Output Enable Time Output Disable Time Pulse Duration, HIGH Setup Time, data before Hold Time, data after Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
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SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
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TEST CIRCUITS OUTPUTS
Pulse Generator
LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY HIGH LOAD/2 tPHZ tPLZ DISABLE LOAD/2
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D.U.T.
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DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM
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NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
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OUTPUT SKEW INPUT tPLH1
tPHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
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OUTPUT
OUTPUT tPLH2 tPHL2
tPLH2 tPLH1 PHL2 tPHL1
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
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IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
ORDERING INFORMATION
ALVC Device Type Package Range Bus-Hold
Small Outline 20-2) Shrink Outline Package (SO20-7) Quarter-size Outline Package (SO20-8) Thin Shrink Small Outline Package (SO20-9) Octal Positive Edge-Triggered D-Type Flip-Flop with 3-State Outputs, ±24mA Bus-Hold -40°C +85°C
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3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE

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