3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
|
|
|
Top Searches for this datasheet
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.8mm pitch LFBGA package, balls Extended commercial range -40°C +85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin
IDT74ALVCH32501
DESCRIPTION:
This 36-bit universal transceiver built using advanced dual metal CMOS technology. ALVCH32501 combines D-type latches Dtype flip-flops allow data flow transparent latched clocked modes. Data flow each direction controlled output-enable (OEAB OEBA), latch enable (LEAB LEBA), clock (CLKAB CLKBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held HIGH logic level. LEAB low, data stored latch/flip-flop low-to-high transition CLKAB. OEAB performs output enable function port. Data flow from port port similar requires using OEBA, LEBA CLKBA. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. This ALVCH32501 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH32501 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features ALVCH32501: High Output Drivers: ±24mA Suitable heavy loads
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1OEAB 1CLKBA 1LEBA 1OEBA 1CLKAB 1LEAB
2OEAB 2CLKBA 2LEBA 2OEBA 2CLKAB 2LEAB
OTHER CHANNELS
OTHER CHANNELS
1999 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4764/-
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
CONFIGURATION
CLKAB
CLKAB
CLKBA
CLKBA
LEBA
OEBA
LEAB
32501
LFBGA VIEW
LFBGA BALL LFBGA PACKAGE ATTRIBUTES TOPVIEW
1.5m 1.4m 1.3m
0.8m
VIEW
5.5m
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Unit
NEW16link
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
Max. ±100
NOTE: applicable device type.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
FUNCTION TABLE (1,2)
OEAB LEAB Inputs CLKAB Outputs B0(3) B0(4)
DESCRIPTION
Names OEAB OEBA LEAB LEBA CLKAB CLKBA Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1)
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
NOTES: A-to-B data flow shown. B-to-A data flow similar uses OEBA, LEBA, CLKBA. HIGH Voltage Level Voltage Level Don't Care High Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established. Output level before indicated steady-state input conditions were established, provided that CLKAB high before LEAB went low.
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
NEW16link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Propagation Delay Output Enable Time OEBA Output Enable Time OEAB Output Disable Time OEBA Output Disable Time OEAB Setup Time, data before Hold Time, data after Setup Time, data before HIGH Hold Time, data after HIGH Pulse Width, HIGH Pulse Width, HIGH Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
PHAS INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORM ALLY CLOSE tPZH OUTPUT ITCH NORM ALLY OPEN HIGH LOAD tPLZ DISABLE LOAD
ALVC Link
LOAD Open
D.U.T.
ALVC Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
Open
OUTPUT SKEW INPUT
tPLH1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2
PLH2
Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER
ORDERING INFORMATION
ALVC XXXX Device Type Package Range Bus-Hold
Low-Profile Fine Pitch Ball Grid Array (BF114-1)
36-Bit Universal Transceiver 3-State Outputs
32-Bit Density with Resistors, ±24m
Bus-Hold -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com*
search sales office near you, please click sales button found home page dial 800# above press logo registered trademark Integrated Device Technology, Inc.
Other recent searches
LCD-160H128C - LCD-160H128C LCD-160H128C Datasheet
IHB100TC - IHB100TC IHB100TC Datasheet
HDG12864L-7 - HDG12864L-7 HDG12864L-7 Datasheet
2N3237 - 2N3237 2N3237 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
