L-band Down Converter with On-Chip Description CXA3108AQ monolith

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L-band Down Converter with On-Chip Description CXA3108AQ monolith

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CXA3108AQ
L-band Down Converter with On-Chip
Description CXA3108AQ monolithic that downconverts L-band GHz) satellite broadcast receivers. integrates local oscillator circuit, double-balanced mixer, amplifier tuning onto single chip. This supports both analog digital satellite broadcasts, achieves reduction number tuner components smaller size. Features On-chip tuning Supports 2.65 oscillator frequency Noise figure: 12.5 typ. (for full gain) gain variation: typ. Wide band amplifier MHz) outputs supports protocol On-chip high voltage drive transistor charge pump (Plastic)
Absolute Maximum Ratings (Ta=25 Supply voltage -0.3 +5.5 Storage temperature Tstg +150 Allowable power dissipation (when mounted substrate) Operating Conditions Supply voltage Operating temperature
Topr
4.75 5.30
Applications Analog satellite broadcast tuners (BS/CS) Digital satellite broadcast tuners (DSS/DVB, etc.) Structure Bipolar silicon monolithic
Notes Handling This weak electrostatic discharge strength. Take care when handling Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
E99904-TE
CXA3108AQ
Block Diagram Configuration
DVCC1
ADSW
DVCC2
STSW
LOCK
XTAL DGND1 BUSSW
Receiver Divider 11bit
EXTIN2
Phase Detector
EXTIN1
Lock
DGND2
Shift Register Charge Pump
Buffer Output Port Driver Buffer RFVCC Driver OUTPUT Driver Buffer Divider STSW Prescaler 1/2, OSCB2 OSCE2 OSCE1 OSCB1
IFOUT2
BIAS
IFOUT1
IFGND2
IFSW
IFVCC2
IFVCC1
IFAGC
RFIN1
RFIN2
IFGND1
RFGND
CXA3108AQ
Description Symbol voltage (IFSW (IFSW (IFSW (IFSW
IFVCC2
Equivalent circuit
Description
IFOUT1
IFVCC2
outputs.
IFOUT2
IFGND2
output circuit GND. Selects whether output When this connected GND, signal output from when connected VCC, signal output from output circuit power supply. amplifier circuit power supply.
IFVCC1
IFSW
100k
IFVCC2 IFVCC1
IFAGC
signal input.
RFIN1
inputs.
RFIN2
IFGND1 RFGND
amplifier circuit GND. block GND.
CXA3108AQ
Symbol
voltage
Equivalent circuit
Description
RFVCC
BIAS
Oscillator circuit current adjustment. Connect this capacitor.
RFVCC OSCB1
block power supply.
OSCE1
Oscillator pins.
2.5k 2.5k
OSCE2
OSCB2 DGND2
GND. Charge pump GND.
EXTIN1
DVCC1
external inputs.
EXTIN2
DVCC2
transistor output varicap diode drive.
Charge pump output. Connect loop filter.
CXA3108AQ
Symbol
voltage
Equivalent circuit
Description Selects either internal oscillator circuit external input input PLL. When this open connected VCC, internal oscillator circuit selected; when connected GND, external input selected. Charge pump power supply.
DVCC1
STSW
DVCC2
DVCC1
LOCK
(LOCK) (UNLOCK)
LOCK detection. High when locked, when unlocked.
DVCC1
input.
DVCC1
2.5k
DATA input.
CXA3108AQ
Symbol
voltage
Equivalent circuit
Description
DVCC1
CLOCK input.
150k
DVCC1
ADSW
address selection.
DVCC1
circuit power supply.
DVCC1
XTAL
Crystal connection reference oscillator.
DGND1
circuit GND.
CXA3108AQ
Symbol
voltage
Equivalent circuit
Description
DVCC1
BUSSW
circuit GND. Connect directly GND.
DVCC1
(OFF) (ON)
Output ports.
GND.
CXA3108AQ
Electrical Characteristics Circuit Current Item Circuit current Circuit current Symbol AICC DICC Measurement conditions Analog circuit current RFVCC, IFVCC1 IFVCC2 currents circuit current DVCC1 DVCC2 currents Min.
(VCC=5 Ta=25 Typ. Max. Unit
OSC/MIX/IF Amplifier Blocks Item Symbol Conversion gain Noise figure IFAGC gain variation range maximum output local oscillator leak local oscillator leak PoSAT RFLK1 RFLK2 RFLK3 IFLK1 IFLK2 IFLK3 fIF=480 MHz, load saturated output fOSC=1430 1830 fOSC=1830 2230 fOSC=2230 2630 fOSC=1430 1830 fOSC=1830 2230 fOSC=2230 2630 Pin=-25 IFAGC=4 (Full Gain) fin=935 MHz, fout=475 MHz, fOSC=1430 offset fOSC=1430 offset f=950 f=950 Measurement conditions fin=950 MHz, fIF=480 IFAGC=4 (Full Gain) fin=1450 MHz, fIF=480 IFAGC=4 (Full Gain) fin=2150 MHz, fIF=480 IFAGC=4 (Full Gain) fin=950 MHz, fIF=480 IFAGC=4 (Full Gain) fin=1450 MHz, fIF=480 IFAGC=4 (Full Gain) fin=2150 MHz, fIF=480 IFAGC=4 (Full Gain) Min. Typ. Max. Unit
Tertiary intermodulation distortion
Local oscillator phase noise
12.9 1.84
dBc/Hz dBc/Hz
input impedance
CXA3108AQ
Block Item External local input level SDA, High level input voltage level input voltage High level input current level input current output voltage Clock input hysteresis (charge pump) Output current Output current Input current LOCK High output voltage output voltage REFOSC Oscillator frequency range Input capacitance Drive level Pull-in current Leak current Symbol LSDA CIHYS ICPO1 ICPO2 IADC VLKH VLKL FXTOSC CXTOSC VXTOSC SinkPS LeakPS When When Measurement conditions Min. Typ. Max. Unit
VIH=VCC VIL=GND Sink current=3 0.25 Byte 4/bit Byte 4/bit Input voltage=5 Load resistance LOCK Load resistance UNLOCK ±125 ±180
-0.1 0.65 ±270
Timing Item clock frequency Start waiting time Start hold time hold time High hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time Symbol fSCL tWSTA tHSTA tLOW tHIGH tSSTA tHDAT tSDAT tSSTO Measurement conditions Min. 1300 1300 1300 Typ. Max. Unit
Electrical Characteristics Measurement Circuit
ADCin LOCK
6.2k 330n
LOCK
DVCC1
ADSW
DVCC2
XTAL DGND1 BUSSW CXA3108AQ IFOUT2 OSCB2 OSCE2 OSCE1 DGND2 EXTIN1 EXTIN2
STSW
100p
EXTIN
IFSW
IFVCC1
RFIN1
IFGND1
IFOUT1
IFGND1
IFVCC2
IFAGC
RFIN2
100p 100p
RFGND
IFAGC
RFin
-10-
1T379
1T379 OSCB1 RFVCC BIAS 0.1µ
IFout2
CXA3108AQ
IFout1
CXA3108AQ
Description Functions CXA3108AQ tuner satellite broadcast receivers. converts signal down-converted GHz) that only desired reception frequency selected detected. This combines mixer, local oscillator amplifier (variable gain) circuits required frequency conversion circuit which controls local oscillator frequency onto single chip. function each block described below. Mixer Circuit This circuit outputs frequency difference between signal input local oscillator signal. double-balanced mixer with minimal local oscillator signal leak used. input equivalent differential amplifier with emitter grounding. Local Oscillator Circuit Colpitts oscillator with differential operation used oscillator circuit, stable relative supply voltage fluctuation, undesired radiation suppressed. This circuit also contains capacitor which part resonance circuit, there minimal parasitic oscillation design external circuits easier. Amplifier Circuit This circuit amplifies mixer output, comprised amplifier stage impedance output stage. gain varied voltage (range amplifier stage. maximum gain approximately (voltage gain between OUT), gain variation width more. output stage unbalanced outputs, directly connect filters with different pass bandwidths. Output selection determined voltage. amplifier circuit wide band amplifier circuit, used frequency range MHz. Circuit-1 (normal operation: when STSW open connected VCC) circuit fixes local oscillator frequency desired frequency. consists prescaler, main divider, reference divider, phase comparator, charge pump reference oscillator. control format supports protocol. When power (DVCC1) turned power-on reset circuit activates frequency division data control data initialized power-on reset threshold normal temperature (Ta=25 °C). Circuit-2 (external input operation: when STSW connected GND) When STSW connected GND, enters independent operation mode where only used with oscillator signal input from external signal input pin.
-11-
CXA3108AQ
Description Block Programming 1-1. main divider frequency division ratio obtained according following formulas. fosc fref (16M fosc fref (16M (when fosc local oscillator frequency fref comparison frequency prescaler fixed frequency division ratio (when main divider frequency division ratio swallow counter frequency division ratio variable frequency division ranges follows. 4095 During independent operation (STSW GND), prescaler halving frequency division cannot added. 1-2. This conforms standard format, bidirectional control possible consisting write mode which various data received read mode which various data sent. Write read modes recognized according setting final (R/W bit) address byte. Write mode when "0", read mode when "1". 1-2-1. Address Setting responding address changed ADSW voltage allow more than system. <Table Address ADSW voltage OPEN
-12-
CXA3108AQ
1-2-2. Data format Write mode used receive various data. this mode, byte contains address data, bytes contain frequency data, bytes contain various control data. These data latch transferred manner byte byte byte byte byte When correct address received, data recognized frequency data first next byte "0", control data this "1". Also, when data transmission stopped part-way, previously programmed data valid. Therefore, once control data been programmed, 3-byte commands consisting address frequency data possible. Further, even stop conditions met, data input sending start conditions address. read mode, power-on reset operation status, phase comparator locked/unlocked status 5value converter input voltage status transmitted master. Power-on reset when supply voltage (DVCC1) power supply off. DVCC1 higher status output read mode, this reset "0". Write mode: slave receiver MODE Address byte Divider byte Divider byte Control byte Control byte bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Read mode: slave transmitter MODE Address byte Status byte bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
-13-
CXA3108AQ
port control main divider frequency division ratio setting swallow counter frequency division ratio setting varicap output (when "1") charge pump current switching prescaler halving frequency division added (when "1") power-on reset lock detection signal 5-value data (ADC voltage conversion: Table reference divider frequency division ratio selection (Table
<Table Conversion Table voltage 0.15VCC 0.15 0.45 0.45
<Table Reference Divider Frequency Division Ratio Frequency division ratio
-14-
CXA3108AQ
Timing Chart
tWSTA
tSSTA tSSTO
tHSTA START
tLOW
tHIGH CLOCK
tSDAT
tHDAT STOP
DATA CHANGE
tSSTA =Start setup time tWSTA =Start waiting time tHSTA =Start hold time tLOW =LOW clock pulse width tHIGH =HIGH clock pulse width
tSDAT tHDAT tSSTO
=Data setup time =Data hold time =Stop setup time =Rise time =Fall time
-15-
CXA3108AQ
Example Representative Characteristics
Current consumption characteristics
Current consumption [mA]
Supply voltage Conversion gain IF=480MHz, AGC=4V
IFOUT
Conversion gain [dB]
input frequency [GHz] characteristics IF=480 MHz, AGC=4V Untuned input, display
Noise figure [dB]
input frequency [GHz]
-16-
CXA3108AQ
local oscillator leak characteristics
local oscillator leak [dBm]
fOSC Local oscillator frequency [GHz] IFOUT local oscillator leak characteristics AGC=4V
IFOUT local oscillator leak [dBm]
fOSC Local oscillator frequency [GHz] Input/output characteristics (untuned input, AGC=4V)
Fundamental wave (480MHz)
output level [dBm]
Tertiary intermodulation distortion component (470MHz)
input level [dBm] (935MHz, 940MHz)
-17-
CXA3108AQ
Input Impedance
2150MHz 950MHz
1450MHz
Output Impedance
479.5MHz
-18-
CXA3108AQ
Package Outline
Unit
40PIN (PLASTIC)
0.35 0.15 0.127 0.05
0.65 0.15 0.15
0.24
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
-19-

L-band Down Converter with On-Chip Description CXA3108AQ monolith

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