LC66354C, 66356C, 66358C Four-Bit Single-Chip Microcontrollers wi
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5484
LC66354C, 66356C, 66358C
Four-Bit Single-Chip Microcontrollers with On-Chip
Preliminary Overview
LC66354C, LC66356C, LC66358C 4-bit CMOS microcontrollers that integrate single chip functions required system controller, including ROM, RAM, ports, serial interface, comparator inputs, three-value inputs, timers, interrupt functions. These three microcontrollers available 42-pin package. These products differ from earlier LC66358A Series LC66358B Series power-supply voltage range, operating speed, other points. Evaluation LSIs LC66599 (evaluation chip) EVA85/800-TB6630X LC66E308 (on-chip EPROM microcontroller) used together.
Package Dimensions
unit: 3025B-DIP42S
[LC66354C/66356C/66358C]
Features Functions
15.24
On-chip capacities kilobytes, on-chip capacity bits. Fully supports LC66000 Series common instruction (128 instructions). ports: pins 8-bit serial interface: circuits (can connected cascade form 16-bit interface) Instruction cycle time: 0.92 earlier LC66358A Series: 1.96 3.92 earlier LC66358B Series: 0.92 Powerful timer functions prescalers Time limit timer, event counter, pulse width measurement, square wave output using 12-bit timer. Time limit timer, event counter, output, square wave output using 8-bit timer. Time base function using 12-bit prescaler. Powerful interrupt system with interrupt factors interrupt vector locations. External interrupts: factors/3 vector locations Internal interrupts: factors/5 vector locations Flexible functions Comparator inputs, three-value inputs, 20-mA drive outputs, 15-V high-voltage pins, pull-up/open-drain options. Optional runaway detection function (watchdog timer) 8-bit functions Power saving functions using halt hold modes. Packages: DIP42S, QIP48E (QFP48E)
13.8
37.9
4.25
0.95
0.48
1.78
0.51
1.15
SANYO: DIP42S
unit: 3156-QFP48E
[LC66354C/66356C/66358C]
17.2 14.0 0.15
17.2 14.0
0.35
2.70 (STAND OFF)
3.0max
15.6
SANYO: QFP48E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
22897HA (OT) 5484-1/21
0.25
LC66354C, 66356C, 66358C Series Organization
Type LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B LC66562B/566B LC66354C/356C/358C LC662304A/2306A/2308A LC662312A/2316A LC665304A/665306A/665308A LC665312A/5316A LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 LC66E2316 LC66E5316 LC66P2316* LC66P5316 Note: Under development pins 52/48 capacity K/12 K/16 K/12 K/16 K/16 K/16 K/16 EPROM OTPROM EPROM OTPROM EPROM OTPROM EPROM EPROM OTPROM OTPROM capacity DIP64S DIP42S DIP64S DIP64S DIP42S DIP42S DIP42S DIP48S DIP48S DIC42S with window DIP42S DIC42S with window DIP42S DIC64S with window DIP64S DIC42S with window DIC52S with window DIP42S DIP48S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP64E QFP48E QFP48E QFP48E QFP48E QFP48E QFC48 with window QFP48E QFC48 with window QFP48E QFC64 with window QFP64E QFC48 with window QFC48 with window QFP48E QFP48E Window evaluation versions V/0.92 Low-voltage high-speed versions V/0.92 V/0.92 On-chip DTMF generator versions V/0.95 Dual oscillator support V/0.95 Low-voltage versions V/3.92 Normal versions V/0.92 Features
V/0.95
V/0.95
5484-2/21
LC66354C, 66356C, 66358C Assignments
DIP42S SI0/P20 SO0/P21 SCK0/P22 INT0/P23 INT1/P30 POUT0/P31 POUT1/P32 HOLD/P33 TEST OSC1 PE1/TRB PE0/TRA PD3/CMP3 PD2/CMP2 PD1/CMP1 PD0/CMP0 PC3/VREF1 PC2/VREF0 P63/PIN1 P62/SCK1 P61/SO1 P60/SI1 P53/INT2 OSC2
LC66354C 356C 358C
QFP48E
CMP2/PD2 CMP3/PD3 TRA/PE0 TRB/PE1 OSC2 OSC1 TEST
S10/P20 S00/P21 SCK0/P22 INT0/P23 INT1/P30 POUT0/P31 POUT1/P32 HOLD/P33
PD1/CMP1 PD0/CMP0 PC3/VREF1 PC2/VREF0 P63/PIN1 P62/SCK1 P61/S01 P60/S11 P53/INT2
LC66354C 356C 358C
view
recommend reflow-soldering techniques solder-mount packages. Please consult with your Sanyo representative details process conditions package itself directly immersed dip-soldering bath (dip-soldering techniques).
5484-3/21
LC66354C, 66356C, 66358C System Block Diagram
STACK (512W) SYSTEM CONTROL FLAG (4K/6K/8K)
TEST OSC1 OSC2 HOLD
CMP0 CMP1 CMP2 CMP3
PRESCALER
TIMER0
SERIAL
POUT0 SCK0 INT0 INT1. INT2 SCK1 PIN1. POUT1
INTERRUPT CONTROL
TIMER1
SERIAL
Differences between LC66354C, LC66356C, LC66358C LC6630X Series
Item System differences Hardware wait time (number cycles) when hold mode cleared Value timer after reset (Including value after hold mode cleared) LC6630X Series (Including LC66599 evaluation chip) 65536 cycles About (Tcyc LC6635XC Series 16384 cycles About (Tcyc
FF0.
FFC. V/0.92 LC6635XA V/3.92 V/1.96 LC6635XB V/0.92
Difference major features Operating power-supply voltage operating speed (cycle time)
LC66304A/306A/308A V/0.92 LC66E308/P308 V/0.92
Note: oscillator cannot used with LC66354C, LC66356C, LC66358C. There other differences, including differences output currents port input voltages. details, data sheets LC66308A, LC66E308, LC66P308. close attention differences listed here when using LC66E308 LC66P308 evaluation.
5484-4/21
LC66354C, 66356C, 66358C Function Overview
Overview ports Input output 4-bit 1-bit units support halt mode control function Output driver type Options State after reset
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
High (option)
ports Input output 4-bit 1-bit units
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
High (option)
P20/SI0 P21/SO0 P22/SCK0 P23/INT0
ports Input output 4-bit 1-bit units also used serial input pin. also used serial output pin. also used serial clock SCK0 pin. also used INT0 interrupt request pin, also timer event counting pulse width measurement input.
Pch: CMOS type Nch: Intermediate sink current type Nch: +15-V handling when option selected
CMOS output
P30/INT1 P31/POUT0 P32/POUT1
ports Input output 3-bit 1-bit units also used INT1 interrupt request. also used square wave output from timer also used square wave output from timer
Pch: CMOS type Nch: Intermediate sink current type Nch: +15-V handling when option selected
CMOS output
P33/HOLD
Hold mode control input Hold mode HOLD instruction when HOLD low. hold mode, restarted setting HOLD high level. This used input port along with P32. When P33/HOLD level, will reset level pin. Therefore, applications must P33/HOLD when power first applied.
ports Input output 4-bit 1-bit units Input output 8-bit units when used conjunction with P53. used output 8-bit data when used conjunction with P53.
Pch: Pull-up type Nch: Intermediate sink current type Nch: +15-V handling when option selected
Pull-up output
P53/INT2
ports Input output 4-bit 1-bit units Input output 8-bit units when used conjunction with P43. used output 8-bit data when used conjunction with P43. also used INT2 interrupt request.
Pch: Pull-up type Nch: Intermediate sink current type Nch: +15-V handling when option selected
Pull-up output
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LC66354C, 66356C, 66358C
Continued from preceding page. Overview ports Input output 4-bit 1-bit units also used serial input pin. also used serial output pin. also used serial clock SCK1 pin. also used event count input timer Output driver type Options State after reset
P60/SI0 P61/SO1 P62/SCK1 P63/PIN1
Pch: CMOS type Nch: Intermediate sink current type Nch: +15-V handling when option selected
CMOS output
PC2/VREF0 PC3/VREF1
ports Input output 2-bit 1-bit units also used VREF0 comparator comparison voltage pin. also used VREF1 comparator comparison voltage pin.
Pch: CMOS type Nch: Intermediate sink current type
CMOS output
PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3
Dedicated input ports These pins switched software function comparator inputs. comparison voltage provided VREF0. comparison voltage provided VREF1. Pins comparator function individually, pins together. Dedicated input ports These pins switched software function three-value inputs. System clock oscillator connections When external clock used, leave OSC2 open connect clock signal OSC1. System reset input When P33/HOLD high level, level input will initialize CPU. test This must connected during normal operation. Power supply pins either ceramic oscillator external clock selected.
Normal input
PE0/TRA PE1/TRB
Normal input
OSC1 OSC2
TEST
Note: Pull-up type: output circuit includes transistor that pulls VDD. CMOS output: Complementary output. output: Open-drain output.
5484-6/21
LC66354C, 66356C, 66358C User Options Port output level reset option output levels reset ports independent 4-bit groups, selected from following options.
Option Output high reset Output reset Conditions notes four bits ports group four bits ports group
Oscillator circuit options
Option Circuit Conditions notes
External clock
OSC1
input Schmitt characteristics
Ceramic oscillator
OSC1
Ceramic oscillator
OSC2
Note: There oscillator option.
Watchdog timer option runaway detection function (watchdog timer) selected option. Port output type options output type each (pin) ports (except P33/HOLD pin), selected individually from following options.
Option Circuit Conditions notes
Output data
Open-drain output
Input data Output data
port inputs have Schmitt characteristics.
port inputs have Schmitt characteristics. CMOS outputs (ports pull-up outputs (P0, distinguished drive capacity p-channel transistor.
Output with built-in pull-up resistor
Input data
port comparator input port three-value input selected software.
5484-7/21
LC66354C, 66356C, 66358C
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Symbol VIN1 VIN2 Output voltage VOUT1 VOUT2 Output current -IOP1 -IOP2 ION1 Total current ION2 IOP1 IOP2 Allowable power dissipation Operating temperature Storage temperature Topr Tstg (except P33/HOLD pin), other inputs (except P33/HOLD pin), other inputs (except P33/HOLD pin), (except P33/HOLD pin), (except P33/HOLD pin), P40, P42, P43, (except P33/HOLD pin), P40, P42, P43, +70°C DIP42S QFP48E Conditions Ratings -0.3 +7.0 -0.3 +15.0 -0.3 -0.3 +15.0 -0.3 +125 Unit Note
Note: Applies pins with open-drain output specifications. pins with other than open-drain output specifications, ratings column that apply. oscillator input output pins, levels free-running oscillation level allowed. Sink current Source current (Applies pins with pull-up output CMOS output specifications.) recommend reflow soldering techniques solder mount packages. Please consult with your Sanyo representative details process conditions package itself directly immersed dip-soldering bath (dip-soldering techniques).
5484-8/21
LC66354C, 66356C, 66358C Allowable Operating Ranges +70°C, unless otherwise specified.
Parameter Operating supply voltage Memory retention supply voltage Symbol VDDH VIH1 VIH2 VIH3 VIH4 Mid-level input voltage Common-mode input voltage range VCMM1 VCMM2 VIL1 Input low-level voltage VIL2 VIL3 VIL4 Operating frequency (instruction cycle time) [External clock input conditions] OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) (Tcyc) Conditions VDD: 0.92 Tcyc VDD: During hold mode (except P33/HOLD pin), N-channel output transistor P33/HOLD, RES, OSC1: N-channel output transistor N-channel output transistor With 3-value input used, With 3-value input used, PD0, PC2: When comparator input used, PD1, PD2, PD3, PC3: When comparator input used, (except P33/HOLD pin), RES, OSC1: N-channel output transistor P33/HOLD: TEST: N-channel output transistor With 3-value input used, (10) +13.5 4.35 (0.92) Unit (µs) Note
Input high-level voltage
Frequency
fext
4.35
Pulse width
textH, textL
Rise fall times
textR, textF
Note: Applies pins with open-drain specifications. However, VIH2 applies P33/HOLD pin. When ports have CMOS output specifications they cannot used input pins. Applies pins with open-drain specifications. When used three-value input, VIH4, VIM, VIL4 apply. When ports pins have CMOS output specifications they cannot used input pins.
5484-9/21
LC66354C, 66356C, 66358C Electrical Characteristics +70°C, unless otherwise specified.
Parameter Symbol IIH1 Input high-level current Conditions (except P33/HOLD pin), 13.5 with output transistor OSC1, RES, P33/HOLD: VDD, with output transistor PC2, PC3: VDD, with output transistor Input ports other than PC2, PC3: VSS, with output transistor PC2, PC3, VSS, with output transistor (except P33/HOLD pin), (except P33/HOLD pin), -0.1 VSS, (except P33/HOLD pin): (except P33/HOLD pin): 13.5 PD3: PD0: VDD, -1.0 -1.0 -1.6 ±300 ±300 Unit Note
IIH2 IIH3 IIL1
Input low-level current IIL2
VOH1 Output high-level voltage VOH2 Output pull-up current VOL1 Output low-level voltage VOL2 Output leakage current IOFF1 IOFF2 VOFF1 VOFF2 [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF fCFS VHIS
Comparator offset voltage
OSC1 (EXT), OSC1, OSC2: Figure Figure
SCK0, SCK1: With timing Figure test load Figure
Tcyc Tcyc
Low-level high-level Input pulse widths Output Rise fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time Output
tICK tCKI
SI0, SI1: With timing Figure Stipulated with respect rising edge SCK0 SCK1.
tCKO
SO0, SO1: With timing Figure test load Figure Stipulated with respect falling edge SCK0 SCK1.
Continued next page. 5484-10/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Parameter [Pulse conditions] INT0: Figure conditions under which INT0 interrupt accepted, conditions under which timer event counter pulse width measurement input accepted INT1, INT2: Figure conditions under which corresponding interrupt accepted PIN1: Figure conditions under which timer event counter input accepted RES: Figure conditions under which reset applied. Symbol Conditions Unit Note
INT0 high low-level
tIOH, tIOL
Tcyc
High low-level pulse widths interrupt inputs other than INT0 PIN1 high low-level pulse widths high low-level pulse widths
tIIH, tIIL tPINH, tPINL tRSH, tRSL
Tcyc Tcyc Tcyc
Comparator response speed Operating current drain
IDDHALT IDDHOLD
Figure VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: 0.01
Halt mode current drain Hold mode current drain
Note: With output transistor shared ports with open-drain output specifications. These pins cannot used input pins CMOS output specifications selected. With output transistor shared ports with open-drain output specifications. rating pull-up output specification pins stipulated terms output pull-up current IPO. These pins cannot used input pins CMOS output specifications selected. With output transistor CMOS output specification pins. With output transistor pull-up output specification pins. With output transistor open-drain output specification pins. Reset state
0.8VDD 0.2VDD External clock OPEN textF textL textR 1/fext textH
OSC1
(OSC2)
Figure External Clock Input Waveform
Operating minimum value Stable oscillation Ceramic oscillator Oscillator unstable period
OSC1
OSC2
Figure Ceramic Oscillator Circuit Table Guaranteed Ceramic Oscillator Constants
(Murata Mfg. Co., Ltd.) CSA4.00MG (Kyocera Corporation) KBR4.0MS
Figure Oscillator Stabilization Period
5484-11/21
LC66354C, 66356C, 66358C
tCKCY tCKL SCK0 SCK1 0.2VDD (input) 0.4VDD (output) tCK0 VDD-1 0.4VDD tCKR tCKH tCKF 0.8VDD (input) VDD-1V (output) tICK tCKI 0.8VDD 0.2VDD R=1k TEST point C=50pF
Figure Serial Timing
tI0H tI1H tPINH tRSH 0.8VDD 0.2VDD tI0L tI1L tPINL tRSL
Figure Timing Load
Figure Input Timing INT0, INT1, INT2, PIN1, pins
VOFF VOFF
Comparator output data
Figure Comparator Response Speed Timing
5484-12/21
LC66354C, 66356C, 66358C LC66XXX Series Instruction Table function) Abbreviations: Accumulator register Carry flag Zero flag Data pointer DPH, Data pointer DPX, Data memory (HL): Data memory pointed DPH, data pointer (XY): Data memory pointed DPX, auxiliary data pointer (HL): words data memory (starting even address) pointed DPH, data pointer Stack pointer (SP): words data memory pointed stack pointer (SP): Four words data memory pointed stack pointer bits immediate data specification
PCh: PCm: PCl: TIMER0: TIMER1: SIO: (i4): INT:
Bits Bits Bits User flag, Timer Timer Serial register Port Port indicated bits immediate data Interrupt enable flag Indicates contents location Transfer direction, result Exclusive Logical Logical Addition Subtraction Taking one's complement
5484-13/21
LC66354C, 66356C, 66358C
Instruction code Mnemonic [Accumulator manipulation instructions] Clear Decimal adjust addition Decimal adjust subtraction Clear Complement Increment Decrement Rotate right through Rotate left through Transfer Transfer Exchange with Clear (Equivalent (AC) (Equivalent (AC) (Equivalent 0AH.) (AC) (AC) (AC) (CF), (ACn (AC0) (CF), (ACn), (AC3) (AC) (AC) Clear Take one's complement Increment Decrement Shift (including right. vertical skip function. Number bytes Number cycles Affected status bits
Operation
Description
Note
Shift (including left. Transfer contents Transfer contents Exchange contents
[Memory manipulation instructions] IMDR Increment Decrement Increment direct (HL) (HL)] (HL) (HL)] (i8) (i8)] (i8) (i8)] (HL), (HL), Increment (HL). Decrement (HL). Increment (i8). Decrement (i8). (HL) specified Clear (HL) specified
DMDR Decrement direct data Reset data
[Arithmetic, logic comparison instructions] (AC) (HL)] contents (HL) two's complement values store result
ADDR direct
contents (i8) two's complement (AC) (i8)] values store result (AC) (HL)] (CF) contents (HL) two's complement values store result contents immediate data two's complement values store result Subtract contents from (HL) two's complement values store result Take logical (HL) store result Take logical (HL) store result
with
immediate data
(AC)
SUBC
Subtract from with
(HL)] (AC) (CF) (AC) (HL)] (AC) (HL)]
will zero there borrow otherwise.
ANDA
with then store with then store
Continued next page. 5484-14/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code Mnemonic [Arithmetic, logic comparison instructions] Exclusive with then store with then store with then store (AC) (HL)] (HL) (AC) (HL)] (HL) (AC) (HL)] Take logical exclusive (HL) store result Take logical (HL) store result (HL). Take logical (HL) store result (HL). Compare contents (HL) clear according result. Compare with (HL)] (AC) Magnitude comparison (HL)] (AC) (HL)] (AC) (HL)] (AC) Number bytes Number cycles Affected status bits
Operation
Description
Note
ANDM
Compare contents immediate data clear according result. Compare with immediate data (AC) Magnitude comparison (DPL) (DPL) (AC, (HL), (AC, (HL), (HL), (i8)] (HL) (AC) (HL) (AC)
Compare with immediate data
Compare contents with immediate data. identical clear not. Compare corresponding bits specified (HL). identical clear not.
Compare with data
[Load store instructions] LADR Load from (HL) Load with immediate data Load from direct Store Store (HL) Load contents (HL) into Load immediate data into Load contents (i8) into Store contents into (HL). Store contents into (HL). Load contents (reg) into either depending vertical skip function
Load from (reg)
(reg)]
Continued next page. 5484-15/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code Mnemonic [Load store instructions] Load contents (reg) into (The either XY.) Then increment contents either DPY. relationship between same that instruction. Load contents (reg) into (The either XY.) Then decrement contents either DPY. relationship between same that instruction. Exchange contents (reg) either depending according result incrementing DPY. Number bytes Number cycles Affected status bits
Operation
Description
Note
reg,
Load from (reg) then increment
(reg)] (DPL) (DPY)
Load from (reg) reg, then decrement
(reg)] (DPL) (DPY)
according result decrementing DPY.
Exchange with (reg)
(AC) (reg)]
Exchange with reg, (reg) then increment
(AC) (reg)] (DPL) (DPY)
Exchange contents (reg) (The either XY.) Then increment contents either DPY. relationship between same that instruction. Exchange contents (reg) (The either XY.) Then decrement contents either DPY. relationship between same that instruction. Exchange contents (i8). Load immediate data into Load into data location determined replacing lower bits with Output from ports data location determined replacing lower bits with
according result incrementing DPY.
Exchange with reg, (reg) then decrement
(AC) (reg)] (DPL) (DPY)
according result decrementing DPY.
XADR LEAI
Exchange with direct Load with immediate data
(AC) (i8)] [ROM (PCh, AC)]
RTBL
Read table data from program
RTBLP
Read table data from program then output
Port [ROM (PCh, AC)]
[Data pointer manipulation instructions] Load with zero with immediate data respectively Load with immediate data Load with immediate data Load DPH, with immediate data Load DPX, with immediate data Load zero into immediate data into DPL. Load immediate data into DPH. Load immediate data into DPL. Load immediate data into DLH, DPL. Load immediate data into DLX, DPY.
LHLI LXYI
Continued next page. 5484-16/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code Mnemonic [Data pointer manipulation instructions] Increment Decrement Increment Decrement Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with (DPL) (DPL) (DPY) (DPY) (AC) (DPH) (AC) (DPH) (AC) (DPL) (AC) (DPL) (AC) (DPX) (AC) (DPX) (AC) (DPY) (AC) (DPY) Increment contents DPL. Decrement contents DPL. Increment contents DPY. Decrement contents DPY. Transfer contents DPH. Transfer contents Exchange contents DPH. Transfer contents DPL. Transfer contents Exchange contents DPL. Transfer contents DPX. Transfer contents Exchange contents DPX. Transfer contents DPY. Transfer contents Exchange contents DPY. flag specified Reset flag specified Number bytes Number cycles Affected status bits
Operation
Description
Note
[Flag manipulation instructions] flag Reset flag
[Jump subroutine instructions] PC13, PC13, PC11 PC13 PC13 (E), (AC) PC13 PC10 (SP) (CF, PC13 (SP)-4 Jump location same bank specified immediate data P12. Jump location determined replacing lower bits This becomes PC12 (PC12) immediately following BANK instruction.
addr
Jump current bank
P11P10P9
JPEA
Jump address stored current page
addr
Call subroutine
Call subroutine.
addr
Call subroutine zero page
PC13 PC10 Call subroutine page (SP) bank (CF, PC12 SP-4 Change memory bank register bank.
BANK
Change bank
Continued next page. 5484-17/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code Mnemonic [Jump subroutine instructions] Store contents (SP). Subtract from after store. PUSH Push (SP) (SP) (reg) (SP) Illegal value Number bytes Number cycles Affected status bits
Operation
Description
Note
(SP)
(SP) (SP)]
then load contents M2(SP) into reg. relation between i1i0 same that PUSH instruction. Return from subroutine interrupt handling routine. restored. Return from subroutine interrupt handling routine. restored.
Return from subroutine Return from interrupt routine
(SP) (SP)] (SP) (SP)] (SP)] (AC, (AC, (HL),t2] (HL),t2]
[Branch instructions] BAt2 addr Branch location same page specified specified immediate data one. Branch location same page specified specified immediate data zero. Branch location same page specified (HL) specified immediate data one. Branch location same page specified (HL) specified immediate data zero. Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out. Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out.
Branch
BNAt2 addr
Branch
BMt2 addr
Branch
BNMt2 addr
Branch
BPt2 addr
Branch Port
(DPL),
Branch location same page specified port (DPL) specified immediate data one.
BNPt2 addr
Branch Port
(DPL),
Branch location same page specified port (DPL) specified immediate data zero.
Continued next page. 5484-18/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code Mnemonic [Branch instructions] (CF) (CF) (ZF) (ZF) (Fn) (Fn) Branch location same page specified one. Branch location same page specified zero. Branch location same page specified one. Branch location same page specified zero. Branch location same page specified flag user flags) specified one. Branch location same page specified flag user flags) specified zero. Number bytes Number cycles Affected status bits
Operation
Description
Note
addr
Branch
addr
Branch
addr
Branch
addr
Branch
BFn4 addr
Branch flag
BNFn4 addr
Branch flag
[I/O instructions] IPDR Input port Input port Input port Input port direct Input port respectively Output port Output port Output port direct Output port respectively (P0) (DPL)] (HL) (DPL)] (i4)] (4)] (5)] (DPL) (AC) (DPL) (HL)] (i4) (AC) (AC) (DPL), Input contents port Input contents port (DPL) Input contents port (DPL) (HL). Input contents (i4) Input contents ports respectively. Output contents port (DPL). Output contents (HL) port (DPL). Output contents (i4). Output contents ports respectively. port (DPL) specified immediate data Clear zero port (DPL) specified immediate data
IP45
OPDR
OP45
port
Reset port
(DPL), P0)] P0)]
port with ANDPDR immediate data then output port with immediate data then output
Take logical immediate data output result P0). Take logical immediate data output result P0).
ORPDR
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LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code Mnemonic [Timer control instructions] WTTM0 Write timer Write contents (HL), TIMER0 (HL)], into timer reload (AC) register. Write contents TIMER1 (E), (AC) into timer reload register (HL), (TIMER0) (TIMER1) Start timer counter Start timer counter Stop timer counter Stop timer counter Read contents timer counter into (HL), Read contents timer counter into Start timer counter. Start timer counter. Stop timer counter. Stop timer counter. Number bytes Number cycles Affected status bits
Operation
Description
Note
WTTM1
Write timer
RTIM0
Read timer
RTIM1
Read timer
START0 Start timer START1 Start timer STOP0 STOP1 Stop timer Stop timer
[Interrupt control instructions] MSET MRESET WTSP interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt Disable interrupt high Disable interrupt Write Read EDIH (EDIH) EDIL (EDIL) EDIH (EDIH) EDIL (EDIL) (E), (AC) (SP) interrupt master enable flag one. Clear interrupt master enable flag zero. interrupt enable flag one. interrupt enable flag one. Clear interrupt enable flag zero. Clear interrupt enable flag zero. Transfer contents Transfer contents
[Standby control instructions] HALT HOLD HALT HOLD HALT HOLD Enter halt mode. Enter hold mode.
[Serial control instructions] STARTS Start serial WTSIO RSIO Write serial Read serial START (E), (AC) (SIO) Start operation. Write contents SIO. Read contents into
[Other instructions] operation operation PC12 Consume machine cycle without performing operation. Specify memory bank.
Select bank
Note: range instruction varies according device. Refer User's Manual that.
5484-20/21
LC66354C, 66356C, 66358C
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information February, 1997. Specifications information herein subject change without notice. 5484-21/21
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