LC66354B, 66356B, 66358B Four-bit Single-Chip Microcontrollers On

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LC66354B, 66356B, 66358B Four-bit Single-Chip Microcontrollers On

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Ordering number EN4677
LC66354B, 66356B, 66358B
Four-bit Single-Chip Microcontrollers On-Chip K-byte
Overview
LC66354B, LC66356B LC66358B 42-pin package four-bit CMOS microcontrollers that integrate single chip functions required control microcontroller, including ROM, RAM, ports, serial interfaces, comparator inputs, three-value inputs, timers interrupt system. These products differ from earlier LC66358A series their power supply voltage range operating speed specifications.
Features Functions
(with K-byte capacities) (512 4-bit digits) chip LC66000 series compatible instruction (128 instructions) total port pins eight-bit serial interfaces that connected cascade form 16-bit interface Instruction cycle time: 0.92 earlier LC66358A series instruction cycle times from 1.96 from 3.92 Powerful timer prescaler functions
Time limit timer, event counter, pulse width measurement square wave output using 12-bit timer. Time limit timer, event counter, output square wave output using 8-bit timer. Time base function using 12-bit prescaler. Powerful interrupt system with eight interrupts eight vector locations External interrupts: three interrupts three vector locations Internal interrupts: five interrupts five vector locations Flexible functions Comparator inputs, three-value inputs, drive outputs, withstand voltage, pull-up open-drain option switching Runaway detection function (watchdog timer) option Eight-bit function Power reduction functions using halt hold modes Packages: DIP42S, QIP48E (QFP48E) Evaluation LSI: used together LC66599 (evaluation chip) EVA850/800TB6630X LC66E308 (on-chip EPROM microcontroller)
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
93098HA (OT) 83194TH (OT) B8-0696 4677-1/23
LC66354B, 66356B, 66358B
Series Structure
Product name LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S* LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B* LC66562B/566B LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 Note: Under development Pins capacity bytes bytes K/12 K/16 bytes bytes bytes K/12 K/16 bytes bytes bytes K/16 bytes EPROM, bytes OTPROM, bytes EPROM, bytes OTPROM, bytes EPROM bytes OTPROM bytes capacity DIP64S DIP42S DIP64S DIP64S DIC42S (window) DIP42S DIC42S (window) DIP42S DIC64S (window) DIP64S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP64E QFC48 (window) QFP48E QFC48 (window) QFP48E QFC64 (window) QFP64E Evaluation window versions V/0.92 Low-voltage, high-speed version V/0.92 Low-voltage version V/3.92 Normal version V/0.92 Features
Assignments
view
recommend using reflow soldering methods mount package version. Contact your Sanyo sales representative discuss process conditions techniques which whole package immersed solder bath (solder spray techniques) used.
4677-2/23
LC66354B, 66356B, 66358B System Block Diagram
Differences between LC66354B, LC66356B LC66358B LC6630X Series
Parameter System Differences Hardware wait time (number cycles) when HOLD mode cleared LC6630X series (including LC66599 evaluation chip) 65536 cycles (Tcyc µs): About LC6635XB series 16384 cycles (Tcyc µs): About value loaded. V/0.92 LC6635XA, V/3.92 V/1.96
Value timer reset value loaded. (including value after HOLD mode cleared) LC66304A, 66306A, 66308A Main differences product characteristics V/0.92 Operating power supply voltage/operating speed LC66E308, 66P308 (cycle time) V/0.92
Note: oscillator cannot used with LC66354B, LC66356B LC66358B. addition, there differences output currents, comparator input voltages other aspects. details, refer individual catalogs LC66308A, LC66E308 LC66P308. These points require care when using LC66E308 LC66P308 evaluation purposes.
Package Dimensions
unit: 3025B-DIP42S
[LC66354B, 66356B, 66358B]
unit: 3156-QFP48E
[LC66354B, 66356B, 66358B]
SANYO: DIP42S SANYO: QFP48E 4677-3/23
LC66354B, 66356B, 66358B Function Overview
Overview ports Input output 4-bit 1-bit units have control functions HALT mode. Output drive type Option Value reset
P-channel: pull-up type N-channel: intermediate sink current type
Either with pull-up n-channel output Reset output level
High level (option)
ports Input output 4-bit 1-bit units
P-channel: pull-up type N-channel: intermediate sink current type
Either with pull-up n-channel output Reset output level
High level (option)
ports Input output 4-bit 1-bit units also used serial input pin. P20/SI0 P21/SO0 P22/SCK0 P23/INT0 also used serial output pin. also used serial clock SCK0 pin. also used INT0 interrupt request, timer event counter pulse width measurement input. ports Input output 3-bit 1-bit units P30/INT1 P31/POUT0 P32/POUT1 also used INT1 interrupt request. also used square wave output from timer also used square wave output from timer output. P-channel: CMOS type N-channel: intermediate sink current type (+15 withstand voltage Either CMOS n-channel output P-channel: CMOS type N-channel: intermediate sink current type (+15 withstand voltage Either CMOS n-channel output
Hold mode control input Hold mode entered HOLD instruction executed when HOLD low. When hold mode, reactivated setting HOLD high level. P33/HOLD also used input port along with P32. When P33/HOLD low, will reset level RES. Therefore, cannot used applications that P33/HOLD when power first applied.
ports Input output 3-bit 1-bit units 8-bit units when used conjunction with Output 8-bit data when used conjunction with P-channel: pull-up type N-channel: intermediate sink current type (+15 withstand voltage Either with pull-up n-channel output
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LC66354B, 66356B, 66358B
Continued from preceding page.
Overview ports Input output 4-bit 1-bit units P53/INT2 8-bit units when used conjunction with Output 8-bit data when used conjunction with also used INT2 interrupt request. ports Input output 4-bit 1-bit units P60/SI1 P61/SO1 P62/SCK1 P63/PIN1 also used serial input pin. also used serial output pin. also used serial clock SCK1 pin. also used timer event counter input. P-channel: CMOS type N-channel: intermediate sink current type (+15 withstand voltage Either CMOS n-channel output P-channel: pull-up type N-channel: intermediate sink current type (+15 withstand voltage Output drive type Option Value reset
Either with pull-up n-channel output
ports Output 4-bit 1-bit units PC2/VREF0 PC3/VREF1 also used VREF0 comparator comparison voltage pin. also used VREF1 comparator comparison voltage pin. P-channel: CMOS type N-channel: intermediate sink current type Either CMOS n-channel output
Dedicated input ports switched comparator inputs under program control. PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3 comparison voltage VREF0. comparison voltage VREF1. Comparisons specified units PD0, PD2, together. PE0/TRA PE1/TRB Dedicated input ports switched function threevalue inputs under program control. System clock oscillator external connection When external clock used, leave OSC2 open input clock signal OSC1. System reset input initialized level input when P33/HOLD high. test TEST This must connected during normal operation. Power supply connections Normal input
Normal input
OSC1 OSC2
Selection either ceramic oscillator external clock input.
Note: Pull-up output:.A pull-up transistor connected output circuit. CMOS output: .Complementary output output:.Open drain output
4677-5/23
LC66354B, 66356B, 66358B User Option Types Port reset time output level option output levels ports selected from following options 4-bit units.
Option High level output reset time level output reset time Conditions notes Ports and/or 4-bit sets Ports and/or 4-bit sets
Oscillator circuit option
Option Circuit Conditions notes
External clock
This input Schmitt specification input.
Ceramic oscillator
Note: There oscillator option.
Watchdog timer option presence absence watchdog timer selected option. Port output type option following output circuit options selected each ports (except P33/HOLD pin),
Option Circuit Conditions notes
Open drain output
Schmitt inputs.
Schmitt inputs. Built-in pull-up resistor output CMOS outputs (P2, pull-up outputs (P0, differentiated according drive capacity p-channel transistor.
comparator inputs three-value inputs selected software.
4677-6/23
LC66354B, 66356B, 66358B
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Symbol VOUT VOUT Output current -IOP -IOP Total current Allowable power dissipation Operating temperature Storage temperature Topr Tstg (except P33/HOLD pin), Other inputs (except P33/HOLD pin), Other outputs (except P33/HOLD pin), (except P33/HOLD pin), (except P33/HOLD pin), P40, P42, P43, (except P33/HOLD pin), P40, P42, P43, +70°C DIP42S QFP48E Applicable pins, notes Conditions Ratings -0.3 +7.0 -0.3 +15.0 -0.3 -0.3 +15.0 -0.3 +125 Unit Note
Output voltage
Note: Applies open drain output specification pins. rating from "other pin" entry applies specifications other than open drain output specification. Levels free-running oscillation level allowed oscillator input output pins. Inflow current Outflow current (Applies pull-up output specification CMOS output specification pins.) recommend using reflow soldering methods mount package version. Contact your Sanyo sales representative discuss process conditions techniques which whole package immersed solder bath (solder spray techniques) used.
Allowable Operating Ranges 70°C, unless otherwise specified
Parameter Operating supply voltage Memory hold supply voltage Symbol (except P33/HOLD pin), P33/HOLD, RES, OSC1 PD0, PD1, PD2, PD3, (except P33/HOLD pin), RES, OSC1 P33/HOLD TEST Applicable pins Conditions 0.92 Tcyc HOLD mode With output n-channel transistor With output n-channel transistor With output n-channel transistor Using three-value input Using three-value input Using comparator input With output n-channel transistor With output n-channel transistor Using comparator input (10) Ratings 13.5 Unit Note
Input high level Voltage
0.75
0.25 4.35 (0.92)
(µs)
Middle level input voltage Common mode input voltage range
VCMM VCMM
Input level voltage
Operating frequency (instruction cycle time)
(TCYC)
Note: Applies open drain specification pins. However, rating applies P33/HOLD pin. Ports cannot used input pins when CMOS output specifications used. Applies open drain specification pins. When used three-value input, (4), apply. Port cannot used input pins when CMOS output specifications used.
Continued next page. 4677-7/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Ratings
Parameter
Symbol
Applicable pins
Conditions Figure With signal input OSC1 with OSC2 open (with external clock input selected oscillator circuit option) Figure With signal input OSC1 with OSC2 open (with external clock input selected oscillator circuit option) Figure With signal input OSC1 with OSC2 open (with external clock input selected oscillator circuit option)
Unit
Note
Frequency
fext
4.35
External clock input conditions
Pulse width
textH textL
OSC1
Rise/fall times
textR textF
Electrical Characteristics 70°C, unless otherwise specified
Parameter Symbol Applicable pins (except P33/HOLD pin), OSC1, RES, P33/HOLD Conditions 13.5, With output n-channel transistor VDD, With output n-channel transistor VDD, With output n-channel transistor -1.0 Ratings Unit Note
Input high level current
PC2,
Input level current
VSS, Inputs other than With output n-channel transistor PC2, PC3, (except P33/HOLD pin) (except P33/HOLD pin) (except P33/HOLD pin) PD1, PD2, VSS, With output n-channel transistor -0.1 VSS,
-1.0 -1.6
Output high level voltage Output pull-up current Output level voltage IOFF IOFF VOFF VOFF VHIS
13.5
±300 ±300
Output leakage current
Comparator offset voltage Hysteresis voltage Schmitt characteristics High level thresHOLD voltage level thresHOLD voltage
OSC1 (EXT),
Continued next page. 4677-8/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Ratings
Parameter Oscillator frequency Oscillator stabilization time Cycle time Input Output
Symbol fCFS
Applicable pins OSC1, OSC2
Conditions Figure
Unit
Note
Ceramic oscillator
Figure SCK0, SCK1 timing from Figure test load from Figure
Tcyc
tCKCY
Serial clock
level/ Input high level pulse Output widths Rise/ fall times Output
tCKL
tCKH
Tcyc
tCKR tCKF tICK SI0, tCKI Stipulated with respect rising edge timing SCK0 SCK1 from Figure Stipulated with respect rising edge timing SCK0 SCK1 from Figure test load shown Figure Conditions such that INT0 interrupt accepted Conditions such that timer event counter pulse width measurement inputs accepted. Figure INT1, INT2 Conditions such that interrupts accepted Conditions such that timer event counter inputs accepted. Conditions such that reset occurs Figure Using ceramic oscillator Using external clock Using ceramic oscillator Using external clock 0.01
Data setup time Serial input Data hold time
Serial output
Output delay time
tCKO
SO0,
INT0 high/low level pulse widths
tIOH tIOL
INT0
Tcyc
Pulse conditions
High/low level pulse widths interrupt inputs other than INT0 PIN1 high/low level pulse widths high/low level pulse widths
tIIH tIIL
Tcyc
tPINH tPINL tRSH tRSL
PIN1
Tcyc
Tcyc
Comparator response speed
Operating mode current drain
HALT mode current drain
IDDHALT
Hold-mode current drain
IDDHOLD
Note: Common input output ports with open-drain output specifications specified state with output n-channel transistor turned off. These pins cannot used input when CMOS output specification option selected. Common input output ports with open-drain output specifications specified state with output n-channel transistor turned off. Ratings pull-up output specification pins stipulated output pull-up current IPO. These pins cannot used input when CMOS output specification option selected. Stipulated CMOS output specifications with output n-channel transistor state. Stipulated pull-up output specifications with output n-channel transistor state. Stipulated open-drain output specifications with output n-channel transistor state. reset state
4677-9/23
LC66354B, 66356B, 66358B
Figure External Clock Input Waveform
Figure Ceramic Oscillator Circuit
Figure Oscillator Stabilization Time Table Ceramic Oscillator Guaranteed Constants
(Murata) CSA2.00MG External capacitance type (Murata) CSA4.00MG (Kyocera) KBR4.0MS (Kyocera) KBR2.0MS
Figure Serial Timing
4677-10/23
LC66354B, 66356B, 66358B
Figure Timing Load
Figure Input Timing INT0, INT1, INT2, PIN1
Figure Comparator Response Speed Timing
4677-11/23
LC66354B, 66356B, 66358B Application Development Tools Programs LC66354B, LC66356B LC66358B microcontrollers developed IBM-PC compatible personal computer running MS-DOS operating system. cross assembler other tools available. make application development more convenient, Sanyo also provides program debugging unit (EVA800/850), evaluation board (EVA800/850-TB6630X), evaluation chip (LC66599) on-chip EPROM microprocessor (LC66E308).
Structure Application Development Tools Program debugging unit (EVA800/850) This emulator that provides functions EPROM writing serial data communications with external equipment (such host computer). supports application development machine language program modification. main debugging functions include breaking, stepping tracing. (The MPM6630X used EVA800/850 monitor ROM.) Evaluation chip board (EVA800/850-TB6630X) evaluation chip signals ports output 42-pin connector when output cable connected, evaluation chip board converts these signals same assignments those mass production chip. evaluation chip board includes jumpers setting options other states, these jumper settings allow evaluation chip implement same circuit types functions mass production chip. However, there differences HOLD mode clear timing electrical characteristics. Jumper
Type Jumper Jumper setting mode Jumper (J1) External oscillator (external clock) oscillator Reset method Jumper (J2: RES) Reset instruction from host computer. Power supply user application board Jumper (J3: VDD) supplied user application printed circuit board through evaluation chip board.
oscillator
Reset reset circuit user application printed circuit board.
Separate power supplies user application printed circuit board evaluation chip board.
Switches (SW9, SW10 SW11)
Type Switch Switch setting mode Port output levels reset SW11: P0HL Port high Port SW10: P1HL Port highPort Watchdog timer presence absence setting SW9: Watchdog timer present Watchdog timer absent
Switches SW8: Pull-up resistor option settings corresponding switch position built-in pull-up resistors, switch position open drain output. These settings specified individual pins.
4677-12/23
LC66354B, 66356B, 66358B Cross Assembler
Cross assembler (file name) Object microprocessors LC66354B, 66356B, 66358B (LC66E308, 66P308) (LC66599) Limitations program creation instruction limitations LC66354B Only used. LC66356B, 66358B Only used. (LC66E308, 66P308) LC66599 SB0, SB1, used.
LC66S.
Simulation chip (See LC66E308 individual product catalog more details.) LC66E308 simulation chip on-chip EPROM microprocessor. Mounted configuration operation confirmed application product using dedicated conversion board (the W66EP308D/408D products W66EP308Q/408Q products) writing programs with commercial PROM writer. Form LC66E308 arrangement functions identical those LC66354B, LC66356B LC66358B. However, there differences HOLD mode clear timing electrical characteristics. figure below shows assignment. Options options (the port level reset, watchdog timer port output circuit types) microprocessor evaluated specified EPROM data. (The next item describes option data area definitions.) This allows evaluation with same peripheral circuits those that will used mass production product. Assignment
4677-13/23
LC66354B, 66356B, 66358B Option Data Area Definitions
area 2000H 2001H 2002H 2003H 2004H 2005H 2006H 2007H Unused Level reset Unused Option item Relation between option data Must zeros. ceramic oscillator external clock Must zero. high level level present, absent
Oscillator option
Watchdog timer option Unused Unused Unused Unused Unused Unused Output circuit type Output circuit type Output circuit type Output circuit type Output circuit type
Must zero.
Must zero. Must zero. Must zero. Must zero.
4677-14/23
LC66354B, 66356B, 66358B LC663XX Series Instruction Table function) Abbreviations: Accumulator register Carry flag Zero flag Data pointer DPH, Data pointer DPX, Data memory (HL): Data memory pointed DPH, data pointer (XY): Data memory pointed DPX, data pointer (HL): words data memory (starting even address) pointed DPH, data pointer Stack pointer (SP): words data memory pointed stack pointer (SP): Four words data memory pointed stack pointer bits immediate data specification
PCh: PCm: PCl: TIMER0: TIMER1: SIO: (i4): INT:
Bits Bits Bits User flag, Timer Timer Serial register Port Port indicated bits immediate data Interrupt enable flag Indicates contents location Transfer direction, result Exclusive Logical Logical Addition Subtraction Taking one's complement
4677-15/23
LC66354B, 66356B, 66358B Instructions
Instruction group Number bytes Instruction code Mnemonic Clear Decimal adjust addition Decimal adjust subtraction Clear Complement Increment Decrement Rotate right through Rotate left through Transfer Transfer Exchange with Increment Decrement Increment direct Decrement direct data Reset data Number cycles Affected status bits Note
Operation (Equivalent LAI0.)
Description
Clear
(AC) (Equivalent ADI6.) (AC) (Equivalent ADIOAH.) (AC) (AC) (AC) (CF), (ACn (AC0) (CF), (ACn), (AC3) (AC) (AC) (HL) (HL)] (HL) (HL)] (i8) (i8)] (i8) (i8)] (HL), (HL), Clear Take one's complement Increment Decrement Shift (including right.
Accumulator manipulation instructions
IMDR DMDR
Shift (including left. Move contents
Move contents Exchange contents Increment (HL). Decrement (HL). Increment (i8). Decrement (i8). (HL) specified Clear (HL) specified
Memory manipulation instruction
contents (HL) two's complement (AC) (HL)] values store result (AC) (i8)] contents (i8) two's complement values store result
Arithmetic, logic comparison instructions
ADDR
direct
with
contents (AC) (HL)] (HL) two's (CF) complement values store result (AC) contents immediate data two's complement values store result
immediate data
SUBC
Subtract from with with then store
Subtract contents (HL)] (AC) from (HL) two's (CF) complement values store result (AC) (HL)] Take logical (HL) store result
ANDA
Note: vertical skip function. will zero there borrow otherwise.
Continued next page. 4677-16/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic with then store Exclusive with then store with then store with then store Number cycles
Operation
Description
Affected status bits Note
(AC) (HL)] (AC) (HL)] (HL) (AC) (HL)] (HL) (AC) (HL)]
Take logical (HL) store result Take logical exclusive (HL) store result Take logical (HL) store result (HL).
ANDM
Take logical (HL) store result (HL). Compare contents (HL) clear according result.
Arithmetic, logic comparison instructions
Compare with
(HL)] (AC)
Magnitude comparison (HL)] (AC) (HL)] (AC) (HL)] (AC)
Compare contents immediate data clear according result. Compare wiht immediate data (AC) Magnitude comparison (DPL) (DPL) (AC, (HL), (AC, (HL), (HL) (i8)] (HL) (AC) (HL) (AC)
Compare with immediate data
Compare contents with immediate data. identical clear not. Compare corresponding bits specified M(HL). identical clear not. Load contents (HL) into Load immediate data into Load contents (i8) into Store contents into (HL). Store contents into M2(HL). Load contents (reg) into either depending
Compare with data
Load store instructions LADR
Load from (HL) Load with immediate data Load from direct Store Store (HL)
Load from (reg)
(reg)]
Note: vertical skip function.
Continued next page. 4677-17/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic Number cycles
Operation
Description
Affected status bits Note
reg,
Load from (reg) then increment
(reg)] (DPL) (DPY)
Load contents (reg) into (The either XY.) Then increment contents either DPY. relationship between same that instruction. Load contents (reg) into (The either XY.) Then decrement contents either DPY. relationship between same that instruction. Exchange contents (reg) either depending
reg,
Load from (reg) then decrement
(reg)] (DPL) (DPY)
Exchange with (reg)
(AC) (reg)]
Load store instructions
reg,
Exchange with (reg) then increment
(AC) (reg)] (DPL) (DPY)
Exchange contents (reg) (The either XY.) Then increment contents either DPY. relationship between that instruction. Exchange contents (reg) (The either XY.) Then decrement contents either DPY. relationship between that instruction. Exchange contents with (i8). Load immediate data into Load into data location determined replacing lower bits with Output from ports data location determined replacing lower bits with
reg,
Exchange with (reg) then decrement
(AC) (reg)] (DPL) (DPY)
XADR LEAI
Exchange with direct Load with immediate data Read table data from program
(AC) (i8)] [ROM (PCh, AC)]
RTBL
RTBLP
Read table data from program then output
Port [ROM (PCh, AC)]
Note:
according result incrementing DPY. according result decrementing DPY. according result incrementing DPY. according result decrementing DPY.
Continued next page. 4677-18/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic Load with zero with immediate data respectively Load with immediate data Load with immediate data Load DPH, with immediate data Load DPX, with immediate data Increment Decrement Increment Decrement Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with Number cycles
Operation
Description
Affected status bits Note
(DPL) (DPL) (DPY) (DPY) (AC) (DPH) (AC) (DPH) (AC) (DPL) (AC) (DPL) (AC) (DPX) (AC) (DPX) (AC) (DPY) (AC) (DPY)
Load zero into immediate data into DPL. Load immediate data into DPH. Load immediate data into DPL. Load immediate data into DLH, DPL. Load immediate data into DLX, DPY. Increment contents Decrement contents DPL. Increment contents DPY. Decrement contents DPY. Transfer contents DPH. Transfer contents Exchange contents DPH. Transfer contents DPL. Transfer contents Exchange contents DPL. Transfer contents DPX. Transfer contents Exchange contents DPX. Transfer contents DPY. Transfer contents Exchange contents flag specified
LHLI
LXYI
Data pointer manipulation instructions
Flag manipulation instructions
flag
Reset flag
Clear flag specified
Continued next page. 4677-19/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic addr Jump current bank Jump address stored current page Number cycles
Operation PC12 PC12 PC11 PC12 PC12 (AC) PC12, PC10 (SP) (CF, PC12 (SP) PC12 (SP) (CF, PC12
Description Jump location same bank specified immediate data P12. Jump location determined replacing lower bits
Affected status bits Note
JPEA
addr
Call subroutine
Call subroutine.
Jump subroutine instructions
addr
Call subroutine zero page
Call subroutine page bank
BANK
Change bank
Change memory bank register bank. Store contents (SP). Subtract from after store.
PUSH
Push (SP)
(SP) (reg) (SP)
Illegal setting
(SP)
(SP) (SP)]
then load contents (SP) into reg. relation between same that PUSH instruction. Return from subroutine interrupt handling routine. restored. Return from subroutine interrupt handling routine. restored. Branch location same page specified specified immediate data one. Branch location same page specified specified immediate data zero. Branch location same page specified (HL) specified immediate data one. Branch location same page specified (HL) specified immediate data zero.
Return from subroutine Return from interrupt routine
(SP) (SP)] (SP) (SP)] (SP)] (AC, (AC, (HL), (HL),
BAt2 addr
Branch
Branch instructions
MNAt2 addr
Branch
BMt2 addr Branch
BNMt2 addr
Branch
Note: This becomes PC12 (PC12) immediately following BANK instruction.
Continued next page. 4677-20/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic Number cycles
Operation (DPL), (DPL),
Description
Affected status bits Note
BPt2 addr
Branch port
Branch location same page specified port (DPL) specified immediate data one. Branch location same page specified port (DPL) specified immediate data zero.
BNPt2 addr
Branch port
addr
Branch
Branch location same page specified (CF) one. Branch location same page specified (CF) zero. Branch location same page specified (ZF) one. Branch location same page specified (ZF) zero. (Fn) (Fn) (P0) (DPL)] (HL) (DPL)] (i4)] (4)] (5)] (DPL) (AC) (DPL) (HL)] (i4) (AC) (AC) Branch location same page specified flag user flags) specified one. Branch location same page specified flag user flags) specified zero. Input contents port Input contents port (DPL) Input contents port (DPL) (HL). Input contents (i4) Input contents ports respectively. Output contents port (DPL). Output contents (HL) port (DPL). Output contents (i4). Output contents ports respectively.
Branch instructions
addr
Branch
addr
Branch
addr
Branch
BFn4 addr Branch flag
BNFn4 addr
Branch flag
IPDR instructions
Input port Input port Input port Input port direct Input port respectively Output port Output port Output port direct Output port respectively
IP45
OPDR
OP45
Note: Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out.
Continued next page. 4677-21/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic port Number cycles
Operation
Description port (DPL) specified immediate data Clear zero port (DPL) specified immediate data Take logical immediate data output result P0).
Affected status bits Note
(DPL),
instructions
Reset port
(DPL),
ANDPDR
port with immediate data then output port with immediate data then output
ORPDR
Take logical immediate data output result P0).
WTTM0
Write timer
Write contents (HL), TIMER0 (HL)], into timer reload (AC) register. Write contents TIMER1 (E), (AC) into timer reload register (HL), (TIMER0) (TIMER1) Start timer counter Start timer counter Stop timer counter Stop timer counter EDIH (EDIH) EDIL (EDIL) EDIH (EDIL) EDIL (EDIL) (E), (AC) (SP) Read contents timer counter into (HL), Read contents timer counter into Start timer counter. Start timer counter. Stop timer counter. Stop timer counter. interrupt master enable flag one. Clear interrupt master enable flag zero. interrupt enable flag one. interrupt enable flag one. Clear interrupt enable flag zero. Clear interrupt enable flag zero. Transfer contents Transfer contents Enter halt mode.
WTTM1 Timer control instructions
Write timer
RTIM0
Read timer
RTIM1 START0 START1 STOP1 STOP1 MSET MRESET
Read timer1 Start timer Start timer Stop timer Stop timer interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt Disable interrupt high Disable interrupt Write Read
Interrupt control instructions
WTSP
Standby control instructions
HALT
HALT
HALT
HOLD
HOLD
HOLD
Enter HOLD mode.
Continued next page. 4677-22/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number bytes Instruction code Mnemonic STARTS WTSIO RSIO Start serial Write serial Read serial Number cycles
Operation
Description
Affected status bits Note
Serial control instructions
START (E), (AC) (SIO)
Start operation. Write contents SIO. Read contents into Consume machine cycle without performing operation. Specify memory bank.
Other instructions
operation
operation PC12
Select bank
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information September, 1998. Specifications information herein subject change without notice. 4677-23/23

LC66354B, 66356B, 66358B Four-bit Single-Chip Microcontrollers On

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