LC573104A, 573102A 4-bit Single Chip Microcontroller Prelimi

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LC573104A, 573102A 4-bit Single Chip Microcontroller Prelimi

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Ordering number:ENN 4144
LC573104A, 573102A
4-bit Single Chip Microcontroller
Preliminary Overview
LC573104A LC573102A CMOS 4-bit microcontrollers featuring low-voltage operation power dissipation. Both LC573104A LC573102A incorporate 4-bit parallel processing ALU, bytes/2K bytes ROM, RAM, 16-bit timer, infrared remote control transmission carrier output circuit.
Package Dimensions
unit:mm 3112A-MFP24S
[LC573104A, 573102A]
Applications
12.5 0.15
0.63
Features
bits (LC573104A) bits (LC573102A) bits Cycle time
Cycle time 17.6µs System clock generator Ceramic oscillation circuit Oscillation frequency 455kHz Supply voltage 6.0V
0.35
(0.75)
1.7max
Remote controller. Control small measuring instruments.
SANYO MFP24S
Assignment
Current Drain normal operation
Current drain 150µA 400µA System clock generator oscillation oscillation Oscillation frequency 455kHz 455kHz Supply voltage 3.0V 5.0V
HALT mode
Current drain 80µA 300µA System clock generator oscillation oscillation Oscillation frequency 455kHz 455kHz Supply voltage 3.0V 5.0V
HOLD mode
Leakage current 0.1µA Condition When oscillation STOP mode Oscillation frequency 455kHz Supply voltage 5.0V
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges,or other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1501TN (KT)/13195JN/5252JN No.4144-1/16
LC573104A, 573102A
Port Input port port, port) Input/Ouput port port, port port 2-port pins) [Key scan input port] 3-port pins) 2-port pins) [Key scan output port] 1-port pins) [Key scan expansion port] [LED direct drivable port] Infrared remote control carrier generation circuit. Software-controllable remote control carrier output ON/OFF. Software-controllable carrier frequency duty ratio. <38kHz-1/3 duty, 38kHz-1/2 duty, 57kHz-1/2 duty> (When fixed carrier signal output, specified mask option) 1kHz 200kHz infrared remote control transmission carrier frequency. (When carrier output selected timer mask option, when 455kHz oscillator used) Infrared carrier output-dedicated terminal built-in terminal). 108ms HALT-mode cancel signal output. Timer 16-bit software-controllable Timer Timer input clock Ceramic (CR) oscillation frequency (455kHz). 108ms HALT release request signal generation timer (Free running timer). Watchdog timer (changed over between USED/UNUSED mask option) Sub-routine stack level levels Oscillation circuit Ceramic (CR) oscillation circuit 455kHz (for System clock generation), Feedback resistor built-in. Standby function HALT mode HALT mode used reduce current drain. HALT mode suspends program execution. Following shows release HALT mode. System reset HALT mode release request signal. HOLD mode HOLD mode stops ceramic resonator (CR). HOLD mold released ways. System reset Apply level input port port pin. (However, necessary port port HOLD mode release permission flag beforehand.) From shipment MFP-24S (1.0mm pitch) chip. NOTE When dipping solder mount package board, contact SANYO instructions.
No.4144-2/16
LC573104A, 573102A
Application Development System LC573100 Series. Manual Users Manual LC573100 Series Users Manual. Development Tool Manual LC573100 Series Development Tool Manual. Development Tools Tools application development LC573100 Series. Personal computer (MS-DOS based). Cross assembler (LC573100.EXE). Mask option generator (SU573100.EXE). Tools evaluate application development LC573100 Series. chip (LC5797). NOTE capacity differs between chip (LC5797) LC573100 Series, always check before programming debugging. LC573100 bits LC5797 bits NOTE Always keep value mind when programming. Only used address. other than used address when programming, SANYO will liable trouble caused. chip board (TB5730). NOTE) application evaluation board evaluation board made user. Evaluation board [EVA420 (Monitor ER-573000)] Display mask option data control board [DCB-1A (REV3.6)]
Development Support System Outline
cross twist these cables.
No.4144-3/16
LC573104A, 573102A
Block Diagram (LC573104A)
No.4144-4/16
LC573104A, 573102A
Specifications Chip size Chip thickness size Layout
480µm
coordinates
MFP24S assignment Name (µm) 1465 1155 1485 1485 1485 1485 1485 1485 1485 1485 1485 (µm) 1365 1365 1365 1365 1110 1395 1395 MFP24S assignment Name (µm) TEST 1140 TEST 1560 1560 1560 1560 1465 1465 1465 1465 (µm) 1395 1395 1395 1395 1395 1395 1155
chip center origin above coordinates. values represent coordinate center. When dipping MFP24S package solder mount boards, contact SANYO instructions, etc. Chip substrate should connected left open.
No.4144-5/16
LC573104A, 573102A
Function
MFP24S name Input/ Input/ Input/ Input/output port. Output output data from accumulator. (P-ch Open Drain Output) Input/output port. Output output data from accumulator. (P-ch Open Drain Output) Input/output port. Output output data from accumulator. (P-ch Open Drain Output) direct drivable pin. Output Remote control carrier output. Fixed carrier output/ Carrier output timer Input Reset input. Internal pull-up resistor. reset level. fixed carrier output 38kHz-1/3 duty. Output Data loaded accumulator. Output Data loaded accumulator. Output Data loaded accumulator. Input Input/ Function description Output Supply voltage. Input Ground. User system clock oscillation. 455kHz ceramic resonator connected between Output oscillation. Stops oscillation when receiving oscillation stop command. Input Input port system reset charging simultaneously (Mask option). Data loaded accumulator. Input port Data loaded accumulator. level HOLD YES/NO Pull-down resistor level HOLD YES/NO Reset Pull-down resistor Reset signal ENABLE. Option Reset status
No.4144-6/16
LC573104A, 573102A
Supply connections
Fig. Supply connections
No.4144-7/16
LC573104A, 573102A
Mask Option Input port option
Option level Hold selection Circuit sequence. Input signal level Hold selection level Hold used. level Hold used. Remarks Next port switches over
Reset signal option port
Option Resetting port Circuit Remarks Selects signal resetting system simultaneously charging level Allow Prohibit
Carrier standard clock generation circuit option remote control
Option 38/57kHz Circuit Remarks Software-controllable carrier frequency duty. Following carrier frequency duty selected setting control register 38kHz-1/3 Duty 38kHz-1/2 Duty 57kHz-1/2 Duty
Timer overflow
Timer 8-bit overflow signal generates carrier signal infrared remote control.
No.4144-8/16
LC573104A, 573102A
Watchdog timer circuit option
Option Watchdog timer selection Circuit selection Remarks Watchdog timer used/unused
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD1 VDD2 Input voltage Output voltage VOUT IOUT1 Output current (Per pin) IOUT2 IOUT3 IOUT4 Total output current pins except Operating temperature Storage temperature IALL Topr Tstg RES, P03, P13, P20, P21, (P00 P03, P13, P20, input mode) P03, P13, P20, P21, (P00 P03, P13, P20, output mode) (per pin) P03, (per pin) P20, (Per pin) Output pins other than listed above (per pin) pins totaled (except pin) Conditions Ratings -0.3 +7.0 -0.3 -0.3 -0.3 VDD+0.3 -0.3 VDD+0.3 +125 Unit
Recommended Operating Ranges =-30 +70°C, VSS=0V
Parameter Supply voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Operation frequency Symbol VIH1 VIL1 VIH2 VIL2 fOPG Conditions Ratings P03, P13, P20, (P0, ports input mode) oscillation, Fig.
0.7VDD
0.3VDD
Unit
0.75VDD
0.25VDD
Fig. Oscillation Circuit
No.4144-9/16
LC573104A, 573102A
Electrical Characteristics =-30 +70°C, VSS=0V
Parameter Symbol RIN1A Input impedance RIN1B RIN2 VOH1 IOFF IOFF VOH2 IOFF IOFF IOH1 IOL1 IDD1 IDD2 ILEAK1 ILEAK2 VSUS Conditions VDD=2.9V, VIL=0.4V, level Hold Fig. VDD=2.9V, VIL=0.4V, level pull-down Fig. VDD=2.9V, VDD=2.9V, IOH=-450µA, P03, VIN=VSS VDD=2.9V, P03, VIN=VDD VDD=2.9V, IOH=-10mA, P20, VDD=2.9V, P20, VDD=3.0V, VOH=VDD-1.5V, VDD=3.0V, VOH=0.9V, VDD=3.0V, 455kHz oscillation, Ccd=Ccg=150pF, Ta50°C, Fig.5 VDD=3.0V, 455=kHz oscillation, Ccd=Ccg=150pF, Ta50°C, Fig.5 VDD=3.0V Ta=25°C Ta=50°C VIN=VSS VIN=VDD -1.0 Ratings
VDD-0.45
1000
Unit
Output high-level voltage Output off-leak current Output high-level voltage Output off-leak current Output current Output current HALT-mode supply current Operating current Supply leak current Supply leak current Oscillator start-up voltage Oscillator sustaining voltage Oscillator start-up time
-1.0 VDD-0.5
Ccd=Ccg=150pF, 455kHz oscillation, Fig. VDD=2.3V, Ccd=Ccg=150pF, 455kHz oscillation, Fig.
Recommended Oscillators.
Oscillator Manufacturer Part number KBR-455BK/Y CSB455E POE-455 150pF 150pF 150pF 150pF 150pF 150pF 455kHz ceramic Kyocera oscillator Murata Fuji Ceramics
Electrical Characteristics =-30 +70°C, VSS=0V
Parameter Symbol RIN1A Input impedance RIN1B RIN2 VOH1 IOFF IOFF VOH2 IOFF IOFF IOH1 IOL1 IDD1 IDD2 ILEAK1 ILEAK2 VSUS Conditions VDD=5.0V, VIL=0.4V, level Hold Fig. VDD=5.0V, level pull-down Fig. VDD=5.0V, VDD=5.0V, IOH=-750µA, P03, VIN=VSS VDD=5.0V, P03, VIN=VDD VDD=5.0V, IOH=-10mA, P20, VDD=5.0V, P20, VDD=5.0V, VOH=VDD-2.5V, VDD=5.0V, VOL=0.9V, VDD=5.0V, 455kHz oscillation, Ccd=Ccg=150pF, Ta50°C, Fig.5 VDD=5.0V, 455kHz oscillation, Ccd=Ccg=150pF, Ta50°C, Fig.5 VDD=5.0V Ta=25°C Ta=50°C VIN=VSS VIN=VDD -1.0 Ratings
VDD-0.75
Unit
Output high-level voltage Output off-leak current Output high-level voltage Output off-leak current Output current Output current HALT-mode supply current Operating current Supply leak current Supply leak current Oscillator start-up voltage Oscillator sustaining voltage Oscillator start-up time
-1.0 VDD-0.5
Ccd=Ccg=150pF, 455kHz oscillation, Fig. VDD=2.3V, Ccd=Ccg=150pF, 455kHz oscillation, Fig.
No.4144-10/16
LC573104A, 573102A
Fig. input structure Fig. Oscillator start-up voltage, Oscillator sustaining voltage, Oscillator start-up time measuring circuit.
Note 455kHz, S-PORT M-PORT Input lead terminal resistor built-in OPEN. I/O-PORT Output Mode data `H'.
Fig. Supply current measuring circuit
LC573100 Series Instruction instruction uses following abbreviations symbols. EDPL EDPH TREG SCFn CTLn HEFn CFCF Accumulator Accumulator Carry flag Data pointer Data pointer nibble Data pointer high nibble Data pointer save register Data pointer save register nibble Data pointer save register high nibble Strobe pointer Temporary register Start conditioning flag Control register Hold enable flag data Ceramic resonator oscillator control flag Contents Contents Logical Logical exclusive-OR Logical Transfer direction, result (DP) (DP)] PAGE STSn (STSm) (SFR) CSTF Memory Memory addressed Contents memory addressed Program counter Program counter Page latch Status register Status register content Contents port Immediate data Immediate data Input port pull-down flag Special function register Contents special function register Chrono start flag Strobe pointer control Carrier output control flag Complement contents Complement contents Output from stage 15-stage divider Watchdog timer
special function registers abbreviated follows. TCON Timer control register TLOW Timer/counter register byte THIGH Timer/counter register high byte CTL4 Control register Port Port Port
No.4144-11/16
LC573104A, 573102A
LC573100 Series Instructions
Instruction
Mnemonic TAAT ASR0 ASR1 ASL0 ASL1 ADC* ADCI SBC* SBCI Instruction code 0000 0001 0001 0001 0001 0001 1001 1001 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- SUB* SUBI ADN* ADNI AND* ANDI EOR* 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- 0001 0010 1000 1001 1010 1011 1000 1001 0000 1000 Function TRGE (DP) TREG ACn+1, ACn+1, ACn-1, ACn-1, (DP) (DP)+1 (DP) (DP)-1 (AC)+[M (DP)]+CF (DP) (AC)+[M (DP)]+CF
Cycles
Bytes
Status Function description Contents current page, addressed whose low-orderd bits replaced with contents (DP), loaded TREG Stores conternts TREG memory location pointed Shifts contents right enter into MSB. Shifts contents right enter into MSB. Shifts contents left enter into LSB. Shifts contents left enter into LSB. Memory (DP) contents incremented loaded (DP). Memory (DP) contents decremented loaded (DP). memory (DP) contents binary-added result loaded memory (DP) contents binary-added result loaded (DP). immediate data contents binary-added, result loaded memory (DP) contents binary-subtracted, result loaded memory (DP) contents binary-subtracted, result loaded (DP). immediate data contents binary-subtracted result loaded memory (DP) contents binary-added result loaded memory (DP) contents binary-added result loaded (DP). immediate data contents binary-added result loaded memory (DP) contents binary-subtracted result loaded memory (DP) contents binary-subtracted result loaded (DP). flag affected
Accumulator
0000 (AC)+X+CF X3X2X1X0 0001 1001 (AC)+[M (DP)]+CF (DP) (AC)+[M (DP)]+CF
0001 (AC)+X+CF X3X2X1X0 0010 1010 0010 X3X2X1X0 0011 1011 0011 X3X2X1X0 0100 1100 0100 X3X2X1X0 0101 1101 (AC) (DP)] (DP) (AC) (DP)] (AC)+[M (DP)] (DP) (AC)+[M (DP)] (AC)+X (AC)+[M (DP)]+1 (DP) (AC)+[M (DP)]+1 (AC)+X+1 (AC)+[M (DP)] (DP) (AC)+[M (DP)] (AC)+X
Arithmetic
ADD* ADDI
immediate data contents binary-subtracted result loaded memory (DP) contents binary-added result loaded memory (DP) contents binary-added result loaded (DP). immediate data contents binary-added result loaded memory (DP) contents ANDed result loaded memory (DP) contents ANDed result loaded (DP). immediate data contents ANDed result loaded memory (DP) exclusive ORed result loaded memory (DP) exclusive ORed, result loaded (DP). immediate data exclusive ORed result loaded memory (DP) ORed result loaded memory (DP) ORed result loaded (DP). immediate data ORed result loaded
0101 (AC) X3X2X1X0 0110 1110 (AC) (DP)] (DP) (AC) (DP)]
Logical
EORI
0110 (AC) X3X2X1X0 0111 1111 (AC) (DP)] (DP) (AC) (DP)]
0111 (AC) X3X2X1X0
Continued next page.
No.4144-12/16
LC573104A, 573102A
Continued from preceding page.
Instruction
Mnemonic SDPL SDPH LDPL LDPH MDPL MDPH EDPL EDPH IDPL IDPH DDPL DDPH LHLT L500 Instruction code 0001 0001 1111 1111 1011 1100 0001 0001 1001 1001 1001 1001 1010 1010 1110 1001 1001 1010 1010 0000 0000 0000 0000 1111 1111 1010 1010 0011 0010 1100 1101 1101 1110 (AC) (AC) (DPL) (DPH) Function
Cycles
Bytes
Status Function description contents loaded DPL. contents loaded DPH. contents loaded contents loaded Immediate data loaded DPL. Immediate data loaded DPH. EDPL contents exchanged. EDPH contents exchanged. contents incremented contents incremented contents decremented contents decremented contents loaded contents loaded Immediate data loaded contents incremented contents decremented STS2 contents loaded STS2 reset. STS1 contents loaded SCF0 reset. CSTF reset. CSTF set. HEF0 reset inhibit Halt mode release overflow from divider circuit. HEF0 enabling overflow from divider circuit release Halt mode. reset. set. Memory (DP) contents transferred contents stored memory (DP). Immediate data loaded Immediate data loaded memory (DP). SCF1 SCF4 SCF0 CSTF CSTF HEF0 HEF0 flag affected
X3X2X1X0 X3X2X1X0 1110 1111 1010 1100 1011 1101 1110 1010 (DPL) (EDPL) (DPH) (EDPH) (DPL)+1 (DPH)+1 (DPL)-1 (DPH)-1 (AC) (SP)
Data Pointer
X3X2X1X0 1110 1111 1011 1100 0100 0101 0110 0111 0000 0001 1001 1101 (SP)+1 (SP)-1 (STS2), STS2 (STS1), SCF0 CSTF CSTF HEF0 HEF0 (DP)] (DP) (AC)
Flag Data transfer
X3X2X1X0 X3X2X1X0 (DP)
Continued next page.
No.4144-13/16
LC573104A, 573102A
Continued from preceding page.
Instruction Mnemonic HALT Instruction code 0000 1101 0000 Function operation halts Function description Halts operation. HALT mode released under following conditions. HALT mode cancelled interaction commands. Operation. control SPDR 1111 1010 1010 1111 1111 1111 1000 operation (S)] (M)] HFE1 enable release HALT mode overflow signal from divider circuit following oscillation circuit. HFE2 enabling signal rise input port release HALT mode. HFE3 enabling signal rise input port release HALT mode. HFE4 enabling 1/10 second pulse release HALT. HEF1 HEF4 Status flag affected Cycles operation. Input data input port loaded Input data input port loaded Pull-down resister MOS-Tr corresponding input port turned ON/OFF. content X0=0 X0=1 X1=0 X1=1 Input/Output 1111 1100 Cannot used when =0&SP=0H When SP=0&SP=D CTL3 (AC) When SPC=1 (AC) TWRT 0000 0010 Cannot used when =0&SP=0H When SPC=0&SP=D CTL3 When SPC=1 Operation S-Terminal Pull down OFF. S-Terminal Pull down M-Terminal Pull down OFF. M-Terminal Pull down Bytes
X3X2X1X0 CTL2
Cannnot used. (Causes error when executed SPC=0&SP=0H FH.) contents transferred CTL3. contents transferred special function register SFR. Cannnot used. (Causes error when TWRT executed SPC=0&SP=0H FH.) High-order bits data ROM, current page, addressed whose loworder bits replaced (DP) contents, transferred CTL3. High-order bits bits data ROM, current page, addressed whose low-order bits replaced (DP) contents transferred special function register CFCF CFCF
0001
0111
Cannot used =0&SP=0H When SPC=0&SP=D (STS3) When SPC=1 (SFR)
Cannnot used. (Causes error when executed SPC=0&SP=0H FH.) STS3 contents transferred Special function register contents transferred
Continued next page.
No.4144-14/16
LC573104A, 573102A
Continued from preceding page.
Instruction
Mnemonic BAB0 BAB1 BAB2 BAB3 BANZ BCNH PAGE JMP* Instruction code 0000 X10X9X8 Function (PC10 PC0) AC0=1 then AC1=1 then AC2=1 then AC3=1 then AC=0 then (PC10 PC0) then (PC10 PC0) then (PC10 PC0) CF=1 then (PC10 PC0) PAGE (DP)] PC10 PC08 (PAGE) PC07 PC04 (AC) PC11 PC11 STACK (PC)+2 (PC10 PC0) (STACK) (WDT)
Cycles
Bytes
Status Function description Loads data specified jumps unconditionally. When '1', data specified loaded jumps. '0', incremented When '1', data specified loaded jumps. '0', incremented When '1', data specified loaded jumps. '0', incremented When '1', data specified loaded jumps. '0', incremented When '0', data specified loaded jumps. When '0', incremented When '0', data specified loaded jumps. When '0', incremented When '0', data specified loaded jumps. When '1', incremented When '1', data specified loaded jumps. When '0', incremented Memory (DP) contents loaded PAGE latch. Unconditionally jumps page specified PAGE address whose loworder bits specified contents memory (DP). Select bank Select bank Current PC+2 contents saved STACK, data specified loaded sub-routine called. Returns contents saved STACK returns from sub-routine. Resets strobe pointer control (SPC) '0'. Sets strobe pointer control (SPC) '1'. Resets high-order bits divider circuit. Resets Watchdog Timer counter. SCF0 SCF4 flag affected
X7X6X5X4 X3X2X1X0 0100 X10X9X8 X7X6X5X4 X3X2X1X0 0101 X10X9X8 X7X6X5X4 X3X2X1X0 0110 X10X9X8 X7X6X5X4 X3X2X1X0 0111 X10X9X8 X7X6X5X4 X3X2X1X0 0100 X10X9X8 X7X6X5X4 X3X2X1X0 0101 X10X9X8 X7X6X5X4 X3X2X1X0 0110 X10X9X8 X7X6X5X4 X3X2X1X0 0111 X10X9X8 X7X6X5X4 X3X2X1X0 0001 0001 0001 0000
(PC10 PC0) (PC10 PC0) (PC10 PC0) (PC10 PC0)
Branching/subroutine
PC03 PC00 (DP)]
ROM0 ROM1 SPC0
1100 0010 1100 0010
1000 0000 1000 0001
1010 X10X9X8 X7X6X5X4 X3X2X1X0 0001 0011 1100 0010 1100 0010 1111 1111 1001 0000 1001 0001 1011 1001
Miscellaneous
SPC1 CSEC RWDT
No.4144-15/16
LC573104A, 573102A
LC573100 Series Instructions
Lower Uppwer SPDR MDPH ADCI SBCI ADDI BCNH BCNH SUBI ADNI ANDI EORI ADC* MDPL ROMX SPCX RWDT CSEC LDPL LDPH SBC* ADD* IDPL HALT JMP* TAAT PAGE TWRT ASR0 BAB0 BAB1 BAB2 BAB3 SUB* DDPL LHLT ADN* IDPH L500 AND* DDPH EOR* ASR1 ASL0 ASL1 SDPL SDPH EDPL EDPH
Byte-1 Cycle instruction Byte-2 Cycle instruction
ROMX ROM0 instruction (C820H), ROM1 instruction (C821H) SPCX SPC0 instruction (C920H), SPC1 instruction (C921H)
Byte-2 Cycle instruction
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products(including technical data,services) described contained herein controlled under applicable local export control laws regulations, such products must expor without obtaining expor license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information October, 2001. Specifications information herein subject change without notice.
No.4144-16/16

LC573104A, 573102A 4-bit Single Chip Microcontroller Prelimi

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