SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT SPEED CAN-TRANSCEIVER

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SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT SPEED CAN-TRANSCEIVER

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L4969
SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT SPEED CAN-TRANSCEIVER
OPERATING SUPPLY VOLTAGE 28V, TRANSIENT QUIESCENT CURRENT CONSUMPTION, LESS THAN 100µ SLEEP MODE VERY DROP VOLTAGE REGULATORS 5V/100mA 5V/200mA SEPARATE VOLTAGE REGULATOR CAN-TRANSCEIVER SUPPLY WITH POWER SLEEP MODE RESET LOGIC SERIAL INTERFACE TRANSCEIVER (LOW SPEED, DOUBLE WIRE) WITH FAULT TOLERANCE VOLTAGE SENSE COMPARATOR
SO20 PowerSO20
ORDERING NUMBERS: L4969MD (SO20) L4969 (PowerSO20)
pendent Voltage Regulators standard fault tolerant speed line interface multipower BCD3S process. integrates main local functions automotive body electronic applications connected bus.
DESCRIPTION
L4969 integrated circuit containing inde-
Figure Block Diagram
VREG
VREG
Watchdog adjustable RC-Oscillator
NRESET
IdentifierFilter VREG
WAKE CANH CANL Fault tolerant speed CAN-transceiver SCLK SOUT Control Status Memory NINT
September 2000
This preliminary information product development. Details subject change without notice.
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Figure Connection
CANH CANL
WAKE NINT NRES
SCLK NRES NINT WAKE
SOUT
PSO20
SCLK SOUT
SO20
CANL CANH
Table FunctionPin (PSO20) (SO20) 5,6, Name CANH CANL SOUT SCLK NRES NINT WAKE Power Ground Microcontroller Supply Voltage Peripheral Supply Voltage Internal Supply Power Supply CANH Line Driver Output CANL Termination Source CANL Line Driver Output CANH Termination Source Act. Receive Dominant Data Output Act. Transmit Dominant Data Input Serial Data Output Serial Data Input Serial Clock Act. Reset Output Act. Interrupt Request Dual Edge Triggerable Wakeup Input Function
Table Thermal Data
Symbol Rthj-a Rthj-c Parameter Thermal resistance junction-ambient Thermal resistance junction-case Value 401) Unit
Note: Typical value soldered board with copper ground plane (35µ thick).
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Table Absolute Maximum RatingSymbol VVSDC VSTR IVOUT1. IVOUT3 TSTG OUT1 OUT2 OUT3 Vinli VinliW Vcanh Vcanht Vcanl Vcanlt Parameter operating supply voltage Transient operating supply voltage 400ms) Output currents Value -0.3 -0.3 Internally limited Unit
Storage temperature Operating junction temperature Externally forced output voltage OUT1 Externally forced output voltage OUT2 Externally forced output voltage OUT3 Input voltage Logic inputs: SIN, SOUT, RxD, SCLK Input voltage WAKE Voltage CANH line Voltage CANH line 0.1ms Voltage CANL line Voltage CANL line 0.1m
+150 +150 -0.3 +6.3 -0.3 VS+0.3 -0.3 +6.3 -0.3 -0.3 VS+0.3
Notes: circuit protected according MIL-STD-883C. Current forced means voltage unlimited current limited specified value. Voltage forced means voltage limited specified values while current limi ted.
Table Electrical Characteristcs 14V, -40°C 150°C unless otherwise specified.
Values Item 1.1.1 Symbol Supply Current ISSL ISSLWK ISSB Regulators off, (CAN Standby) off, off, (CAN only) only (CAN Standby) Regulators (CAN active, high) IOUT1 -100mA IOUT2 -10mA load. Parameter Test Conditions Min. Typ. Max. Unit
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Table Electrical Characteristcs (continued)
Values Item Symbol Voltage Regulator output voltage -400µA< <-100mA 125°C <-IO <-400µA Dropout voltage 4.8V IOUT1 -10mA IOUT1 -100mA VOL01 ILIM1 VOLI1 TOVT1 TOTKL1 Vres Load regulation Current limit Line regulation -1mA <-IO <-100mA 0.8V 4.5V -1mA RTCR RTCR Voltage Regulator VOLO ILIM TOVT TOTKL Output voltage -1mA <-IO <-200mA 200mA 4.8V -1mA -200mA 0.8V 4.5V IOUT -5mA Parameter Test Conditions Min. Typ. Max. Unit
2.10
Overtemp flag Thermal shutdown reset threshold voltage
Dropout voltage
Load regulation Current limit Line regulation
Overtemp flag Thermal shutdown
Reset Watchdog tRDnom tWDstart Reset pulse duration Reset pulse pause (startup watchdog) 47.5
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Table Electrical Characteristcs (continued)
Values Item 4.2.1 Symbol tWDswS Parameter Watchdog window start (Software window Watchdog) Test Conditions Min. SWDC SWDC SWDC SWDC 4.2.2 tWDswE Watchdog window (Software window watchdog) SWDC SWDC SWDC SWDC tWD1C System Watchdog WD1C WD1C WD1C WD1C WD1C tWD2C System Watchdog WD2C WD2C WD2C WD2C WD2C VRESL Reset output voltage resV1 1.5V 0.75 Typ. Max. 1.25 Unit
Line Interface VDropH VDropL CANH voltage drop (dominant state) CANL voltage drop (dominant state) Propagation delay (rec state) output slew rate ICANH 40mA ICANL -40mA load 3.3n Load 3.3n 2.75
µV/µs
RTH, RRTL Termination resistance VCCFS VHRXD Force Standby mode (fail safe) High level output voltage
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Table Electrical Characteristcs (continued)
Values Item Symbol VLRXD Vd_r Parameter level output voltage Differential receiver threshold VCANH CANL Differential receiver threshold VCANH CANL Differential receiver threshold VCANH CANL CANH recessive output voltage failures (common mode range failures (common mode range failures (common mode range ICANH 40mA ICANL -40mA CANH CANL Sleep mode. CANH Sleep mode. CANL Sleep/ standby mode Sleep/ standby mode Normal mode. CANL Normal mode. CANH< Normal mode. CANL Normal mode. CANH
1.4V
Test Conditions Min. -3.25 Typ. Max. -2.65
Unit
5.10
Vr_d
-3.25
-2.65
5.11
Vd_rF
5.12
VCANHr CANHd VCANLr VCANLd ICANH ICANL ILCANH ILCANL
5.13
CANH dominant output voltage
5.14
CANL recessive output voltage
0.2V
5.15
CANL dominant output voltage
5.16
CANH dominant output current
-130
5.17
CANL dominant output current
5.18
CANH Sleep mode leakage current CANL Sleep mode leakage current
5.19
5.20 5.21 5.22
VWakeH VWakeL Vcanhs Vcanls VOVH VOVL
CANH wakeup voltage CANL wakeup voltage CANH single ended receiver threshold CANL single ended receiver threshold CANH overvoltage detection threshold CANL overvoltage detection threshold
1.82
2.15
5.23
5.24
5.25
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Table Electrical Characteristcs (continued)
Values Item 5.26 5.27 Symbol SOVH RTRTH Parameter CANH overvoltage detection threshold internal termination resistance Test Conditions Min. Sleep/ standby mode Normal mode. failures. VRTH Normal mode. (failure EIII) VRTH Normal mode. failures. Normal mode. (failure EIV, EVI, EVII) VRTH Standby/ sleep mode. failures. VRTL Typ. Max. Unit
5.28
ITRTHF
internal termination current internal termination resistance internal termination current internal termination resistance
5.29
RTRTL
5.30
RTRTLF
5.31
RTRTLS
6.10 6.11 6.12 6.13 6.14 6.15 6.16
Digital SINL VSINH VSCLKL VSCLKH VTXL VTXH VWakeL VWakeH SoutH VSoutL RXDH VRXDL IohRXD IolRXD IohSOUT IolSOUT level input voltage High level input voltage level input voltage High level input voltage level input voltage High level input voltage level input voltage High level input voltage High level output voltage level output voltage High level output voltage level output voltage High level output current level output current High level output current level output current SOUT SOUT
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Table Electrical Characteristcs (continued)
Values Item 6.17 6.18 6.19 6.20 Symbol IohReset IolReset Parameter High level output current level output current High level output current level output current Test Conditions Min. RESET RESET Typ. Max. Unit
Serial Data Interface tStart tSetup tHold tCKmax tGAP SCLK setup time (frame start) SCLK setup time (write) SCLK hold time (write) SCLK SOUT delay time (read) SCLK maximum cycle time (timeout) Interframe
Diagnostic Functio VSmin GSCANH Sense comparator detection threshold CANH groundshift detection threshold
Error Detection NEdgeH NEdgeHR NEdgeL EdgeLR tEIII edges CANL detect permanent CANH edges detect recovery CANH edges CANH detect permanent CANL edges detect recovery CANL CANH short circuit detection time Operating mode (EI_V) Operating mode (EI_V) Operating mode (EII_IX) Operating mode (EII_IX) Operating mode (EIII) Sleep/ standby mode (EIII) Edges Edges Edges Edge
tEIIIR
CANH short circuit recovery time
Operating mode (EIII) Sleep/ standby mode (EIII)
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Table Electrical Characteristcs (continued)
Values Item Symbol tEIV Parameter CANL short circuit detection time Test Conditions Min. Operating mode (EIV) Sleep/ standby mode (EIV) tEIVR CANL short circuit recovery time Operating mode (EIV) Sleep/ standby mode (EIV) 9.10 9.11 9.12 9.13 tEVI tEVIR tEVII tEVIIR tEVIII CANL short circuit detection time CANL short circuit recovery time CANL CANH short circuit detection time CANL CANH short circuit recovery time CANH short circuit detection time Operating mode (EVI) Operating mode (EVI) Operating mode (EVII) Operating mode (EVII) Operating mode (EVIII) Sleep/ standby mode (EVIII) 9.14 tEVIIIR CANH short circuit recovery time Operating mode (EVIII) Sleep/ standby mode (EVIII) 9.15 9.16 tFailTX tFailTXR permanent dominant detection time (Fail safe) permanent dominant recovery time (Fail safe) Operating mode (EX) Operating mode (EX) Typ. Max. Unit
FUNCTIONAL DESCRIPTION General Features U435 monolithic integrated circuit which provides main functions automotive body network. features independent regulated voltage supplies interrupt reset logic with internal clock generator, Serial Interface speed CAN-bus transceiver which supplied separate third voltage regulator (V3). device guarantees clearly defined behavior case failure, avoid permanent errors. device operates three different modes: Sleep mode: CAN-Transceiver: active with reduced performance Watchdog active
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total current consumption 100µA. Standby mode: stop mode) CAN-Transceiver: active with reduced performance total current consumption 200µA. Operating mode:
Output Voltage regulator uses DMOS transistor output stage. With this structure very dropout voltage currents 100mA obtained. dropout operation standby regulator maintained down input supply voltage. output voltage regulated transient input supply voltage 40V. With this feature functional interruption overvoltage pulses generated. output regulator switched sleep mode. Through metal option output voltage 3.3V. Output Voltage regulator uses same output structure output regulator except being short circuit proof rated output current 200mA. output switched through dedicated enable control register. addition tracking option enabled allow follow with constant offset. This feature allows consistent conversion inside (supplied when converted signals referenced Output Voltage third voltage regulator device generates supply voltage internal logic CAN-transceiver. operating mode capable supplying 200mA order guarantee required short circuit current CAN_H driver. sleep operating modes switched through dedicated enable bit. Internal Supply Voltage power sleep mode regulator supplies internal logic sleep mode. Transceiver Supports double wire unshielded busses Baud rate 125KBaud Short circuit protection (battery, ground, wires shorted) Single wire operation possible (automatic switching single wire upon failures) loaded case unpowered transceiver
transceiver stage able transfer serial data independent communication wires either deferentially (normal operation) case single wire fault remaining line. physical bitcoding done using dominant (transmitter active) overwritable recessive states. long dominant phases detected internally further transmission automatically disabled (malfunction protocol unit does affect communication bus, "fail-safe" mechanism). current consumption during inactivity sleep mode available. operating mode entered from sleep mode either local wake (µC) upon detection dominant CAN-bus (external wake up). different errors physical buslines distinguished:
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Detectable Physical Busline FailureType Errors Condition
Errors caused damage datalines isolation CANH wire interrupted (tied Ground termination) CANL wire interrupted (floating tied termination) CANH short circuit VBAT (overvoltage condition) CANL short circuit (permanently dominant) CANH short circuit (permanently recessive) CANL short circuit (overvoltage condition) CANL shorted CANH Edgecount difference Edgecount difference V(CANH) 7.2V after 32us V(CANL) 3.1V V(CANH)-V(CANL) -3.25V after 1.3ms Edgecount difference V(CANL) 7.2V after 32us V(CANH) V(CANL) -3.25V after 1.3m
Errors caused misbehavior transceiver stage VIII CANH short circuit (permanently dominant) CANL short circuit (permanently recessive) V(CANH) 1.8V V(CANH) V(CANL) -3.25V after 1.3ms Edgecount difference
Errors caused defective protocol unit CANH, CANL driven dominant more than 1.3m
different errors lead breakdown whole communication. errors categorized into 'negligible', 'problematic' 'severe':
Negligible ErrorTransmitter Error (CANH CANL interrupted still tied termination) Error VIII (CANH CANL permanently dominant short circuit)
cases above data still transmitted differential mode.
Receiver Error (CANH CANL interrupted still tied termination) Error (CANH CANL permanently recessive short circuit)
cases above data still received differential mode.
Problematic ErrorTransmitter Error (CANH CANL show overvoltage condition short circuit)
Data transmitted using remaining dataline (single wire)
Receiver Error (CANH CANL show overvoltage condition short circuit)
Data received using remaining dataline (single wire)
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Severe ErrorTransmitter Error (CANH CANL permanently recessive short circuit)
Data transmitted remaining dataline after short circuit detection
Error (CANH shorted CANL) Data transmitted CANH CANL after overcurrent detected Error (attempt transmit more than successive dominant bits lowest bitrate specified) Transmission terminated (fail safe)
Receiver Error (CANH shorted CANL)
Data received CANH CANL after detection permanent dominant state
Error VIII (CANH CANL permanently dominant short circuit) Data received CANH CANL after short circuit detected Error (reception sequence dominant bits, violating protocol rules) Data received normally, error detected protocol-unit error conditions signaled issuing error flag inside dedicated register which readable through serial interface. information error type through also stored into this register.
Oscillator power oscillator provides internal clock. sleep mode (Watchdog active) output frequency 250kHz, Watchdog function requested, internal Oscillator switched off. standby operating mode oscillator running 1MHz, calibrated range from -16% +16% using C-XTAL reference. Watchdog triple function programmable watchdog integrated perform following tasks: Wakeup Watchdog: When sleep standby mode watchdog generate wakeup condition after programmable period time ranging from 80ms minutes Startup Watchdog: Upon power-up failure during supervision (see SW-Watchdog) reset pulse generated periodically every 50ms 2.5ms until activity detected (SPI sequence) acknowledge received within cycles (350ms). this condition device forced into Sleep mode until Wakeup detected startup cycle reinitialized. Window Watchdog: After passing startup sequence, this watchdog request acknowledge within programmable timing frame, ranging from 40ms. Upon missing misplaced acknowledge Startup Watchdog initialized. Identifier Filter 12-Bit CAN-ID-filter implemented allowing wakeup specific CAN-messages thus aiding implementation power partial communication networks like standby diagnostics without need power-up whole network. guarantee detection programmed Identifiers, local RC-oscillator calibrated allow programmable Bittime logic extract incoming stream with maximum tolerance over temperature deviation.
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Power-on Reset Upon Power-on 3.5V), internal reset forces device into predefined power-on state: CAN-Standby mode ID-Filter disabled Startup Watchdog active With below regulator will follow with minimum drop. retrieves reset dropping below programmable voltage level either 4.5V (default) 4.0V. programmed state U435 remains unchanged. Ground Shift Detection case single wire communication CANH signal noise ratio low. Detecting local ground shift used additional indicator current signal quality. information integrated ground shift detector will refreshed upon every falling edge read from Transceiver Status Register (CTSR). will set, V(CANH) -1V, reset V(CANH -1V) falling edge Thermal Protection device features three independent thermal warning circuits which monitor temperature output, output CAN_H CAN_L drivers together with voltage regulator Each circuit sets separate overtemperature flag register which read writable serial interface. overtemperature flags cause interrupt able switch drivers through dedicated enable registers. enhance system security following strategy chosen thermal warning shutdown: independent warning flags 140°C V3/CAN-Transceiver 170°C switched 200°C switched switched again through switched again wake-up (Watchdog wake-up, wake-up, external wake-up) Note, that wakeup source 1sec watchdog timeout will established enable proper retry cycle. 1.10 Serial Interface (SPI) standard serial peripheral interface (SPI) implemented allow access internal registers U435. total Registers with different datalengths directly read from written providing requested address beginning dataframe. Upon every access this interface, content register currently accessed shifted SOUT. operations performed rising edge SCLK. frame completed, interface automatically reset after 1.5ms SCLK idle time (auto timeout detection). limited count this device chip select programmed explicitly (see Tristate SOUT) will return normal output mode after fixed period 1.5ms after last foreign interaction. dataframe format used described below:
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General Dataframe Format:
ADR/CMD
Datafield (W/R)
Datafield 2/CRC (W/R)
SOUT
ADR/CMD
Datafield
Datafield 2/CRC
SCLK
99AT0015
Data sampled rising edge clock SOUT will change upon SCLK falling. SOUT will show copy Address/ Command field initial data path checks. Independent command state, SOUT will show content register addressed. contains either data written arbitrary data other operations. transaction will terminated with four data followed 4-Bit wide (Cyclic Redundancy Check) result either related data calculated automatically data returned SOUT. Here provide correct sequence order write command activated inside. CRC-failure signalled NINT. returned data also used verify successful transfer.
Address/ Command Field ADR3 ADR2 ADR1 ADR0
Frame start sequence always transmitted
Addressfield specifying Control/Status word accessed
command: Read register Clear register1) Tristate SOUT2) Write register
Clear register only performed with Interrupt Flag Register ADR6 Tristate SOUT performed Address
99AT0016
Address/Command field starts with 2-Bit start sequence consisting `01'. other sequence will lead protocol error signalled NINT. addressfield specifying register accessed. command flags allow addition normal read/write operation either clear register after read (operating only IFR) disable SOUT allow communication between other peripherals using same SPI. SOUT function automatically reestablished after 1.5ms following last transaction will signalled NINT.
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Datafield
Lower data SIN: Data write SOUT: Data currently selected register
99AT0017
Datafield contains either lower bits 12-Bit frame complete byte 8-Bit transfer. Note, that SOUT always showing content register currently accessed copy during Address/ Command field.
Datafield #2/CRC
CRC3
CRC2
CRC1
CRC0
Upper data (Zero data)
SIN: Data write SOUT: Data currently selected register
99AT0018
Check sequence appended tranferred data Note that upon check failure write operation will performed SIN: sequence SOUT: SOUT sequence
Datafield contains either upper four bits 12-Bit frame zeros case 8-Bit transfer. This field followed four sequence that calculated based upon polynom 0x11h decimal). This sequence simply remainder polynomial division performed data previously transferred. appended sequence fails, writing will disabled error signalled NINT. Another remainder calculated SOUT stream appended accordingly allow application software validate correctness incoming data. evaluation, checking turned writing arbitrary data with valid address CRC-checking will reenabled upon another operation this kind (Toggled information).
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1.11 Memory Table
U435 Memory
EUV3 Undefined Register Memory ISET ESPI PS23 ISET PS22 IRES PS21 UV23 PS20 UVVS PS13 EUV2 TXEN IRES OVT3 EVIII PS12 RTC0 PGEN SWT1 OVT2 EVII PS11 SIGN SWT0 EOVT OVT1 PS10 ADJ3 WDT3 ENV3 ADJ2 WDT2 EIII ENV2 TMUX ADJ1 WDT1 DISAR ADJ0 WDT0 EIFW WKIF
Group
VRCR CTCR GPTR RCADJ GIEN CTSR ID01 ID23 TEST
WDEN SWEN
Undefined Register Memory WNDF WAKE NPOR
Undefined Register Memory
memory space divided into different registers each being directly accessible using SPI. Each register contains specific information functional group. general reserved bitpositions (`RES') have written with `0'. Undefined bits read cannot overwritten. addition there register (CTSR) being read only, thus write attempt will leave register content unchanged. Certain interlock mechanism exist prevent unwanted overwriting important functions i.e. voltage regulators oscillator adjustments. These mechanisms described with functions these registers.
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CONTROL STATUS REGISTERS
functionality device observed controlled through registers which read writable serial interface.
VRCR Voltage Regulator Control Register EUV3 EUV2 RTC0 ENV3 ENV2 DISAR
Enable undervoltage detection Regulator
reset threshold value 4.0V Default value (4.5V) Enable Regulator tracking option have following with constant offset Default value (disabled)
Disable Regulators Sleep) Note, that least Wakeup Source required enable access. This will automatically upon Overtemperatue Regulator reset upon wakeup Power wakeupsource specified, watchdog timer activated. Default vaue Enable Regulator Default value (disabled) This will automatically reset upon Overtemperature Regulator
Enable Regulator This function will automatically activated upon enabling Lineinterface Default value (disabled) This will automatically reset upon Overtemperature from CANIF Regulator
Reserved bits (`RES') have written `0'. DISAR
DISAR ENV2
DISAR ENV3 NSTB OTKL3
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CTCR CAN-Transceiver Control Register
TXEN
CAN-Transceiver application control Standby Sleep Receive only mode (Readback Normal Operation Note, that TXEN automatically reset upon occurence permanent dominant) reprogrammed after problem correction enter normal mode.
Reserved bits (`RES') have written `0'.
Three basic operating modes available using different logic combinations TXEN. Each these modes conjunction with other inputs unique combination parameters inside specification:
Table
Operating Modes Lineinterface
Inpu Signals Output Signals CANL VDD*1 VS*1 CANL*1 GND*1 CANH Mode Standby RXonly RXonly RXonly Normal Normal Normal Normal Error Error VII, VIII Error EIII, VII, VIII Error EI_V Error EII_IX Error Error EVII, Error EVII VBAT ISRC ISRC ISRC ISRC ISRC CANH CANL CANH CANH CANH CANL CANL
TXEN
CANH
"shorted
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GPTR Global Parameter Test Register
TMUX
This register used testpurpose only, bits have remain `zero'
RCADJ RC-Oscillator Adjust register PGEN ADJ4 ADJ3 ADJ2 ADJ1 ADJ0
+16%
Program enable (read only) will after test cycle completion, reset after register write Test cycle request pulse NINT fixed period time requested XTAL synchronization
99AT0022
Oscillator Frequency Adjust default value 10000 Note, that programming only enabled with PGEN
request (Adjustment disabled) 2.5ms cycle NINT (repetitive) Finish cycle measurement request (Adjustment disabled)
During normal operation `01' force 200Hz rectangular waveform NINT with duty cycle. Note, that other pending interrupts have cleared before. After XTAL driven timer calculated relative cycle time corresponding deviation, have `10' disable adjustment cycle NINT. From deviation calculated correction factor RC-oscillator -16% reprogrammed with `00' `11'. (`11' used indicate that calibration already been performed). Note, that overwriting this register only valid, cycle measurement started terminated properly. This tested evaluating PGEN either prior during correction (Read back SOUT).
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ADR4: Watchdog Control Register WDEN SWT1 SWT0 WDT3 WDT2 WDT1 WDT0
Enable Wakeup Watchdog, Window Watchdog will automatically deactivated until wakeup watchdog expire
Software Window Watchdog timing configuration 10ms 20ms
Reserved bits (`RES') have written `0'.
Wakeup Watchdog timing configuration 0000 80ms 0001 160ms 0010 320ms 0011 640ms 0100 800ms 1000 1sec 1001 2sec 1010 4sec 1011 8sec 1100 45min
Startup Watchdog programmable will always generate 2.5ms cycle NRESET followed 47.5ms high cycle until Acknowledgment will occur. Acknowldege received after cycle, device will automatically forced into Sleep mode. Acknowledgment Reset Startup Window Watchdog automatically performed overwriting rewriting) this register.
Watchdog configuration: NRESET forced externally Wakeup Prog Sleep ExtWake CAN-Wake Startup missing Forced Sleep (after 350ms) missing
Timeout Window Wakeup WDEN Timer
After power-on-reset wakeup from Sleep NRESET being forced externally, Startup Watchdog active, supervising proper startup supplied Upon missing write operation register after reset cycles (2.5ms active, 47.5ms high) Sleep mode entered. Leaving forced Sleep mode will automatically performed upon wakeup CAN, edge WAKE upon device powerup. After successful startup, Window Watchdog supervision activated, meaning, that send acknowledge within predefined, programmable window. Upon failure, reset generated Startup Watchdog reactivated. Timer function requested, window watchdog deactivated until expiry wakeup time.
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Startup 2.5ms NRESET Startup Acknowledgement within 50ms NRESET Startup Acknowledgement within 100ms NRESET Startup Acknowledgement within 350ms (Device will enter Sleep mode)
After powerup, U435 expecting send acknowledgement within predefined segmented timing frame 50ms. missing acknowledgement until after 350ms will force device into sleep mode until either external wakeup cause restart sequence above.
Window Watchdog 20ms Early (late) Acknowlede supervision 40ms Early (late) Acknowlede supervision Acknowledge restarting Window
After successful acknowledgement Startup sequence, Window watchdog automatically activated controlling proper activity supervising incoming acknowledge within predefined programmable window. Upon every acknowledge watchdog restarting window.
Wakeup Watchdog Window Timer (80ms 45min) Window
Window Start Timer NINT
Timeout resume Window
Interrupt active upon timeout (via GIEN)
Timer activated during Normal mode setting WDEN WDC, "acknowledge-free" sequence started predefied programmable time. Window Watchdog activity resumed after expiry timer. able detect timeout, corresponding interrupt enable must GIEN. This mode also used allow bootstrap loader mode with longer execution times than maximum specified window. Correct startup this loader safely detected upon missing response following timeout.
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ADR5: GIEN Global Interrupt Enable Register
ISET IRES EOVT
EIFW Enable Identifier based wakeup Interrupt Enable Wakeup,/ Interrupt Watchdog Enable dominant state error wakeup Interrupt Enable Wakeup Interrupt edge WAKE Enable Interrupt upon Overtemp. Warning
Enable Interrupt upon error detection
Enable Interrupt upon error recovery Enable Interrupt upon VREG Undervoltage
ADR6: Interrupt Flag Register
ESPI ISET IRES UV23 UVVS OVT3 OVT2 OVT1
WKIF
Linefailure detected (ISET) removed (IRES)
7.2V detected Undervoltage
Signal edge WAKE detected Wakeup condition detected Watchdog timeout detected Identifier passed ID-Filter
CRC- Format Error SCLKTimeout detected (non maskable)
Overtemperature Warning level reached OVT1 T(V1) 140degC OVT2 T(V2) 140degC OVT3 T(V3) 140degC
Reserved (`RES') written `0'.
Except ESPI bits this register maskable GIEN. masked will force NINT until register content reset (either explicitly `clear register).
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ADR7: CTSR Transceiver Status Register
EVIII EVII EIII EII_IX
EI_V
CANH falling edge permanent dominant detected (TXD `0', 1.3ms) CANH permanent dominant detected (CANH 1.8V, 1.3ms)
CANL short circuit detected (CANL 7.2V, 32us) CANL permanent dominant detected (CANL 3.1V, 1.3ms)
Single wire communication detected (edge count difference EI_V CANH EII_IX CANL
Short circuit CANH CANL detected (CANH CANL -3.25V, 1.3ms)
CANH short circuit detected (CANH 7.2V, 32us)
Reserved bits (`RES') always read
Note, that this register read only only provides unlatched information current buserrors. Identifier Frame divided into segments numbered from `F'. each segment filter register implemented, enabling different pass functions every wide block. Segments through (ID01) located with `C11' Segments through (ID23) located with `F11' Note, that clearing complete segment disables whole filter.
SEGE SEGD SEGF Examples: Identifiers pass:
SEGA SEGC SEGB
Valid sequence each segment SEGA: A10, SEGB: SEGC: C01, SEGD: D10, SEGE: E11, E01, SEGF: F10,
bits 0101 0010 ID01: 0011 0010 0101 0011 0110 1011 ID01: 0110 1011 0110 0011
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Identifier Filter Bittimelogic Control Register
PS23 PS22 PS21 PS13 PS12 PS11 PS10
Phasesegment length configuration tPSEG2 PS2)
Phasesegment length configuration tPSEG1 PS1)
Dominant Rezessive bitlength difference control tDOM tREZ TD[µs]
Bittime synchronization mechanism
PSEG1 Sample Point
99AT0030
PSEG2
total bitlength equals PSEG1 PSEG2 units location sampling point determined length PSEG1. start frame (initial recessive dominant edge) bitlength counter reset. Upon every signal edge counter will lengthened shortened according location transition within programmed boundaries PSEG1 PSEG2. edge lies within PSEG1 additional cycles inserted order shift sampling point safe location after settling input signal. signal transition located within PSEG2, this segment will shortened accordingly with goal next edge beginning PSEG1. amount cycles segment lengthened shortened determined type edge (rec rec) programming resynchronization jump width will either (dom edge) (rec edge). Note, that length timequanta depends offset chip RC-oscillator therefore accuracy calibration (see register RCADJ (ADR details frequency correction)
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System Status Register
WNDF
WAKE NPOR
CRC-Checking enabled Tristate SOUT activated (test only) Warm start after failure Window watchdog
Cold Start after Warm start after leaving prog. Sleep mode
Warm start after Overtemp failure
Warm start after missing during Startup
Warm start after missing during Startup
lower this register used analyze reason startup (after NRESET low). This information valid until first Watchdog-Acknowldge, will then reinitialized 000001.
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INTERRUPT MANAGEMENT
ESPI ISET IRES
UV23 UVVS OVT3 OVT2 OVT1
WKIF
ISET
IRES
EOVT GIEN
EIFW
NINT
Interrupt flags IFR) except ESPI masked global interrupt enable register (GIEN). Interrupt will signalled NINT going until either corresponding mask flag itself will reset application software. autoreset function available IFR, allowing remove interrupt flags after reading their state (see SPI).
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REMARKS APPLICATION
General circuit connection diagram
Thermal Supervision
Peripheral Supply
Standby Supply Adjustable RC-Oscillator
Programmable Timer
NRES
NINT Wakeup Interrupt Detection WAKE SCLK SOUT
33µF
Transceiver Groundshift Detection
CANH CANL
Other Peripheral
ID-Filter
99AT0032
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DIM. MIN. 0.25 2.35 0.33 0.23 12.6
TYP. MAX. 2.65 0.51 0.32 1.27 10.65 0.75 1.27 0.394 0.010 0.016 MIN. 0.093 0.004 0.013 0.009 0.496 0.291
inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050
OUTLINE MECHANICAL DATA
SO20
(min.)8° (max.)
SO20MEC
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L4969
TYP. inch TYP.
DIM.
MIN. 0.23 15.8 13.9
MAX. 0.53 0.32 14.5
MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547
MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
OUTLINE MECHANICAL DATA
1.27 11.43 10.9 15.5 11.1 0.429 0.228 0.000 15.9 0.610 0.031 (max.) (max.)
0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043
JEDEC MO-166
0.394
include mold flash protrusions. Mold flash protrusions shall exceed 0.15 (0.006"). Critical dimensions: "E", "a3"
PowerSO20
DETAIL DETAIL
DETAIL
lead
DETAIL
Gage Plane 0.35
slug
BOTTOM VIEW
SEATING PLANE
(COPLANARITY)
PSO20MEC
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L4969
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SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT SPEED CAN-TRANSCEIVER

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