Universal Interrupt Controller This document contains errata desi

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PPC405CR (IBM25PPC405CR-3xCxxxCx)
Universal Interrupt Controller
This document contains errata design notes that affect designs using PPC405CR (PVR 0x40110145). Each erratum includes overview, description system impact description possible work-around(s). Design notes cover items that considered errata need description beyond what provided published documentation. Refer Tables list errata design notes. Errata organized item designator alphabetical order. item designator consists acronym affected functional unit numeric value. numeric values assigned errata design notes necessarily consecutive. List Functional Unit Acronyms: CHIP Errata particular chip implementation PPC405B3V5 processor core controller Decompression Controller (CodePackTM) External Peripheral Controller GPIO General Purpose controller controller Chip Memory controller OPBA Chip Peripheral Arbiter Processor Local Arbiter Chip Peripheral Bridge SDRAM SDRAM controller UART UART controller
Category definitions: Errata classified according system impact availability work-around. Major impact, work-around available. problem said have major impact results system crash, hard failure, unrecoverable soft failure, significant performance degradation, storage incorrect data. Major impact, work-around impractical implement, substantial risk encountering same additional problems, including performance issues, exist after work-around implemented. Major impact, work-around available. Application work-around either eliminates problem, reduces minor impact issue. Minor impact, work-around available. Minor impact problems result slight moderate performance degradation, functional variance from specification. Minor impact, work-around available. Minor impact problems result slight moderate performance degradation, functional variance from specification. Design enhancement.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
Errata Summary
Table Errata Summary
Item Category Description PPC405CR (IBM25PPC405CR-3BCxxxC) same number (0x40110145) PPC405GP (IBM25PPC405GP-3xExxxC). When controller operating slave with 10-bit addressing, controller incorrectly detect Slave Write Needs Service. iccci instruction errantly cause Data Exception. Virtual memory marked non-executable storage (storage attribute EX=0) loaded into instruction cache using icbt instruction. When real mode, core errantly make speculative instruction fetches from guarded storage. incorrect exception vector offset generated when alignment exception Data Miss exception occur same time. Incorrect real mode attributes used when accessing last instruction region. Multiply accumulate (MAC) instructions having same target register (RT) immediately preceding multiply accumulate instruction multiply instruction yield incorrect results. Switching between virtual real address modes result execution instructions fetched from wrong real address. icbt instructions executed with data relocation enabled cause incorrect instruction execution icbt misses UTLB does have permission access page. lwarx, stwcx. instruction sequence cause branch link register (bclr) branch count register (bcctr) instruction execute incorrectly. Interrupted stwcx. instructions errantly write data memory under certain conditions. Incorrect data flushed from data cache. Writing decompression controller (DCP) registers corrupt contents decompression controller error status register, DCP0_ESR. Executing instructions from memory region configured uncompressed after executing instructions from memory region configured compressed cause Decompression Controller (DCP) generate machine check exception hang PLB. Compressed instruction blocks that cross boundary external memory cause Decompression Controller (DCP) return incorrect instructions processor core Peripheral bank external controller cannot programmed "Write Only" bank. parity generated during memory peripheral write. Slave Transfer Count cleared correctly. controller temporarily placed invalid state. Date First Documented 1/4/01 5/22/00 4/19/99 8/12/99 1/7/00 5/11/00 11/17/00
Date Last Updated 1/4/01 5/22/00 4/19/99 4/27/00 2/24/00 5/11/00 11/17/00
CHIP_3 CHIP_11 CPU_121 CPU_147 CPU_162 CPU_190 CPU_197
CPU_200
2/9/01
4/24/02
CPU_201
2/16/01
7/26/01
CPU_208
8/21/01
8/21/01
CPU_209 CPU_210 CPU_213 DCP_2
8/28/01 8/30/01 2/21/03 3/06/00
8/28/01 8/30/01 5/15/03 3/06/00
DCP_6
7/13/01
7/13/01
DCP_9
7/13/01
7/24/01
EBC_5 EBC_20 IIC_6 IIC_7
11/3/99 4/3/03 1/19/00 1/19/00
11/3/99 5/15/03 1/19/00 1/19/00
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Table Errata Summary
Item Category Description Loss Arbitration while sending address byte(s) causes auto-retry transfer. loss Arbitration while sending address cause Controller malfunction. Controller when operating slave correctly decode 10-bit address. Controller does automatically awaken when slave transfer detected. hang multi-master environment during address byte 10-bit read operation. Incomplete transfer status incorrectly after loss arbitration. Received data slave mode lost. Incorrect data stored PLB0_ACR during read after write sequence. Command leadoff settings (SDRAM0_TR[LDF]) more MemClkOut cycles always generate expected minimum delay. SDRAM controller issue unexpected mode register command. Reading UARTx_IIR cause interrupt lost incorrect status read. Date First Documented 1/19/00 1/19/00 1/19/00 1/19/00 3/29/00 3/29/00 5/10/02 8/21/01 9/5/01 11/1/02 5/16/00 Date Last Updated 2/24/99 1/19/00 3/13/00 1/19/00 3/29/00 3/29/00 5/10/02 8/21/01 9/5/01 5/7/03 5/16/00
IIC_9 IIC_10 IIC_11 IIC_12 IIC_13 IIC_14 IIC_16 PLB_4 SDRAM_10 SDRAM_12 UART_1
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
Design Note Summary
Table Design Note Summary
Item Description When processor powered (i.e., OVdd additional precautions needed powered. SDRAM controller specification does support mixing non-ECC memory banks. default, control signals PPC405CR (DMAReqn, DMAAckn, EOTn/TCn) active high, whereas these signals were active PPC403 series processors. Additional steps must taken awaken UIC. Tune bits should modified Spread Spectrum clocking. Date First Documented 12/10/99 12/10/99 Date Last Updated 12/10/99 12/10/99
12/10/99 1/12/00 1/18/00
12/10/99 1/12/00 1/18/00
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
PPC405CR (IBM25PPC405CR-3BCxxxC) same number (0x40110145) PPC405GP (IBM25PPC405GP3xExxxC).
CHIP_3
Category: Overview: Processor Version Register (PVR) number used software uniquely identify part containing PowerPC processor. However, PPC405CR (IBM25PPC405CR-3BCxxxC) incorrectly assigned number (0x40110145) belonging PPC405GP (IBM25PPC405GP-3xExxxC). Impact: Using number (0x40110145), software cannot differentiate between PPC405CR PPC405GP Work-around: uniquely identify PPC405CR software must reference JTAG register (CPC0_JTAGID). following list JTAG numbers PPC405CR PPC405GP PPC405CR (IBM25PPC405CR-3BCxxxC) 0x42051049 PPC405GP (IBM25PPC405GP-3xExxxC) 0x42050049 work-around needed identify core. PPC405CR PPC405GP both contain PPC405B3V5 core.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CHIP_11
Category: Overview:
When controller operating slave with 10-bit addressing, controller incorrectly detect Slave Write Needs Service.
When Slave Data Buffer (IIC0_SDBUFF) full, i.e. contains bytes data Master does 10-bit write operation, slave (IIC controller) after receiving address byte incorrectly sets Slave Write Needs Service (IIC0_XTCNTLSS[SWS]). controller should wait until after receives second address byte before setting IIC0_XTCNTLSS[SWS]. Both address bytes needed 10-bit addressing. types failures possible slave sets IIC0_XTCNTLSS[SWS] response 10-bit address when IIC0_SDBUFF full: slave (IIC controller) device being addressed, prematurely sets IIC0_XTCNTLSS[SWS] while still decoding address. slave (IIC controller) device being addressed, incorrectly sets IIC0_XTCNTLSS[SWS]. Note this case possible when IIC0_SDBUFF filled with bytes data anticipation slave read operation. Note: Setting Slave Write Needs Service (IIC0_XTCNTLSS[SWS]) will generate interrupt Enable Slave Write Needs Service (IIC0_INTRMSK[EIWS]=1), Enable Interrupt (IIC0_MDCNTL[EINT]=1) Interrupt Enable (UIC0_ER[ITCIE]=1) enabled. Impact: controller hang when 10-bit addressing used. Work-around: following work-arounds: Prevent Slave Data Buffer (IIC0_SDBUFF) from being full ensuring contains less than bytes data. 10-bit addressing PPC405xx/NPe405x controller used slave.
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Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
iccci instruction errantly cause Data Exception.
CPU_121
Category: Overview:
When data-side relocation (data address translation) enabled (MSR[DR] iccci instruction errantly attempts access check associated page. Since iccci invalidates entire instruction cache, effective address generates unnecessary. Impact: When data-side relocation (data address translation) enabled, execution iccci cause Data miss exception. Work-around: There possible work-arounds. Work-around avoids this erratum temporarily disabling data address translation. Work-around describes handle this erratum without disabling data address translation. Before executing iccci instruction, make sure MSR[DR] disabled. This done using following pseudo code:
mfmsr andi mtmsr isync iccci mtmsr isync Ry,Rx,DR_MASK 0,Rx scratch clear MSR[DR] scratch
address does matter.
When data-side relocation enabled, ensure that virtual address generated iccci (virtual address {PID, effective address RB)}) corresponding page TLB.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_147
Virtual memory marked non-executable storage (storage attribute EX=0) loaded into instruction cache using icbt instruction.
Category: Overview: icbt instruction should execute operation) when effective address corresponds memory page marked non-executable. Instead, instruction cache line fill occurs when effective address icbt instruction maps memory region having following three characteristics: Marked non-executable storage (storage attribute Marked cacheable (storage attribute Access prohibited zone fault (The access control field ZSEL references field that does prohibit access). Impact: Touching data belonging page marked non-executable storage into instruction cache with icbt instruction result unnecessary memory accesses. Note that: Memory marked non-executable cannot executed even loaded into instruction cache. icbt instructions compiler generated; they isolated assembly routines. Work-around: work-around necessary either: translation from virtual real does change. There occurrences where icbt instruction causes cache line fill data from page marked non-executable storage. Invalidate cache blocks (lines) loaded with data belonging page marked non-executable storage. either icbi iccci instruction.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
When real mode, core errantly make speculative instruction fetches from guarded storage.
CPU_162
Category: Overview:
real mode, instructions (guarded storage not) memory mapped (guarded storage) within each other, possible speculatively accessed when instructions executed. Impact: Memory mapped (MMIO) speculatively accessed. unintentional access MMIO could result loss data. Work-around: Maintain least separation between instructions memory mapped I/O.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_190
Category: Overview:
incorrect exception vector offset generated when alignment exception Data Miss exception occur same time.
alignment exception (vector offset 0x0600) Data Miss exception (vector offset 0x1100) occur same time, interrupt vector offsets exceptions logically OR'd together produce vector offset 0x1700. unaligned access lwarx, stwcx. dcread instruction will cause alignment exception also generate Data Miss exception. core+ASICs that include attached device, there four additional events that apply this erratum: unaligned load, unaligned store, trap Endian load/store trap Little Endian load/store. Note: dcbz instruction does apply this erratum. This instruction cause alignment exception generate both alignment exception Data Miss exception. unaligned access using lwarx, stwcx. dcread instruction considered programming error. Impact: incorrect exception vector address generated. Work-around: None needed data relocation disabled (MSR[DR] exception vector offset 0x1700 place unconditional branch vector offset 0x1100 (the Data Miss vector).
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Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Incorrect real mode attributes used when accessing last instruction region.
CPU_197
Category: Overview:
When executing instructions real mode (MSR[IR] access last instruction region uses real mode attributes next consecutive region under following conditions: last instruction region contains branch target that non-cacheable causes cache miss. address restored rfci last instruction region this address non-cacheable causes cache miss. next last instruction non-cacheable region contains branch which predicted taken taken. next last instruction non-cacheable region contains isync instruction. Note: Real mode attributes specified ICCR, SU0R, SLER registers. regions have same storage attributes after reset. Therefore, branch instruction reset vector 0xFFFFFFFC affected this erratum after core, chip, system reset. real mode, storage regions wrap making last storage region (0xF8000000 0xFFFFFFFF) first storage region (0x00000000 0x07FFFFFF) consecutive. Impact: table below lists impact encountering conditions listed above. first column contains real mode storage attribute region being accessed second column contains real mode storage attribute next consecutive region. Table Description Impact Item CPU_197 Request from First Region
Non-cacheable Cacheable Endian
Request assumes attribute Second Region
Cacheable Non-cacheable Little Endian
Impact
instruction cache line fill from non-cacheable storage region occur. desired instruction cache line fill from cacheable storage region occur. request from endian storage region treated little endian storage. program exception generated, incorrect instruction executed. request from little endian storage region treated endian storage. program exception machine check exception generated. request from non-compressed storage region treated compressed storage. program exception generated. request from compressed storage region treated non-compressed storage. program exception generated.
Little Endian
Endian
Non-compressed Storage Region Compressed Storage Region
Compressed Storage Region Non-compressed Storage Region
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_197 Continued
Work-around: work-around required following apply: Code does exist last word locations region. real mode storage attributes region containing executable code identical attributes next contiguous region. last words region only accessed while virtual mode (MSR[IR] place code last word locations region. When performing soft reset, branch directly entry point application code. branch reset vector (0xFFFFFFFC). Unlike core, chip system reset, soft reset does guarantee that aligned regions have same storage attributes. branch reset vector last storage region (0xF8000000 0xFFFFFFFF) will obtain storage attributes first storage region (0x00000000 0x07FFFFFF). these storage attributes differ, unexpected results possible.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Multiply accumulate (MAC) instructions having same target register (RT) immediately preceding multiply accumulate instruction multiply instruction yield incorrect results.
CPU_200
Category: Overview: This erratum affects multiply accumulate (MAC) instructions having same target register (RT) immediately preceding multiply accumulate instruction multiply instruction. result stored correct. examples below, target register (r9) instruction address receive incorrect result. instruction preceded MAC:
address address address address A+12 maclhw machhwu machhwu r9,r11,r12 r9,r8,r13 r3,r6,r4 r11,r1,r2
instruction preceded multiply:
address address address address A+12 mulhw machhwu machhwu r9,r11,r12 r9,r8,r13 r3,r6,r4 r11,r1,r2
Note: This erratum affects multiply accumulate instructions multiply instructions. Impact: instructions having same target register (RT) immediately preceding instruction multiply instruction cannot reliably executed. Work-around: Insert instruction between instruction pairs multiply/MAC pairs both instructions same target register. rearranging example code, instructions targeting separated ways. Method separates instruction pair with instruction. instruction preceded MAC:
address address address address A+12 maclhw machhwu machhwu r9,r11,r12 r3,r6,r4 r9,r8,r13 r11,r1,r2
instruction preceded multiply:
address address address address A+12 mulhw machhwu machhwu r9,r11,r12 r3,r6,r4 r9,r8,r13 r11,r1,r2
Method separates instructions with instruction that targets r11. instruction preceded MAC:
address address address address A+12 maclhw machhwu machhwu r9,r11,r12 r11,r1,r2 r9,r8,r13 r3,r6,r4
instruction preceded multiply:
address address address address A+12 mulhw machhwu machhwu r9,r11,r12 r11,r1,r2 r9,r8,r13 r3,r6,r4
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_201
Category: Overview:
Switching between virtual real address modes result execution instructions fetched from wrong real address.
PPC405 processor pre-fetches instructions ahead which currently being executed. address these pre-fetched instructions which cause problem, rather than address instruction being executed. Commonly, addresses being fetched those directly following instruction being executed, although there branch instruction processor fetch instructions from target branch. Most time, distinction between instructions being pre-fetched instruction being executed does matter this erratum description workarounds, although mentioned where relevant. This problem triggered scenarios A-D, detailed below. They each share common property that there change from virtual real instruction address mode, vice versa, typically means interrupt rfci instruction (MSR[IR] changed). each case, virtual address virtual-mode instruction similar real address real mode instruction. Similar means that bits 0:26 each instruction's effective address identical, that they within range cache line, although target code does have cacheable. Taking Interrupt: When switching from virtual address space real address space means interrupt, virtual address interrupted instruction similar real address first instruction interrupt handler, instructions from virtual address space executed instead interrupt handler instructions real address space. example, consider application executing code from virtual addresses 0x500-0x51C, which real addresses 0x42500-0x4251C, when external interrupt occurs. EVPR 0x0000, processor should switch real mode (MSR[IR]=0) start executing interrupt handler instructions from real address 0x500. When this erratum occurs, processor does switch real mode, erroneously executes instructions from virtual address 0x500, real address 0x42500. Returning from Interrupt: When switching from real address space virtual address space means rfci instruction, real address rfi/rfci instruction similar virtual address instruction that target rfi/rfci, instructions from real address space executed instead instructions from virtual address space. Using rfi/rfci Switch from Virtual Real: When switching from virtual address space real address space means rfci instruction, virtual address rfi/rfci instruction similar real address instruction that target rfi/rfci, instructions from virtual address space executed instead instructions from real address space. This nonstandard rfi/rfci, will only occur special circumstances (not normal interrupt handlers). Using mtmsr Transition from Virtual Real vice versa: This usually only done (virtual address equals real address) space, which does trigger this erratum. This case mentioned completeness discussed further here. Impact: When problem occurs, instead executing instructions address space, processor executes instructions from address space.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Continued
CPU_201
Work-around:
problem does occur work-around required each following cases: Instruction relocation used: MSR[IR]=0. Instruction relocation used (MSR[IR]=1) instruction translations V=R. Instruction relocation used there non-V=R instruction translations, there virtual addresses which match addresses instructions executed real mode. Otherwise, perform following: avoid condition above, ensure that, except entries, there entry which cacheable virtual instruction address space where virtual addresses same real addresses used exception vectors ("the EVPR page"). other words, entry exists where TLBHI[EPN[0:15]] EVPR[0:15] TLBLO[EX]=1 TLBLO[I]=0. practice, this subset work-around avoid condition ensure that rfi/rfci executed cached real mode where real address rfi/rfci similar virtual address rfi/rfci target SRR0/2), instruction relocation will turned (SRR1/3[IR]=1), except V=R. This accomplished implementing following: create entries (except V=R) where virtual address same real address code which will execute real mode TLBLO[EX]=1. This restriction hard accomplish many systems, where code resides real memory which typically located address (starting 0x0), virtual addresses typically have some their high bits set, virtual addresses will equal real addresses. other cases, however, operating system must ensure that there instruction virtual addresses which same real address space containing code which execute rfci instruction. Ensure that code that executes real mode non-cacheable setting ICCR=0x00000000. This have significant performance impact real-mode code, thus overall system performance. Ensure that rfci instructions which execute real mode non-cacheable. This achieved saving value ICCR known area memory, setting ICCR=0x00000000 immediately before performing rfci. start interrupt handlers saved ICCR value loaded from memory restored ICCR before continuing. Only small portion realmode code executes with instruction caching which should have little performance impact. However, this requires modification source code interrupt handlers.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_201 Continued
Only execute rfci instructions from byte area defined EVPR ("the EVPR page"). Work-around above ensures that there overlap between virtual addresses real address EVPR page. implement this work-around, necessary place both rfci instruction free memory locations EVPR page. rfci instructions EVPR page should aligned cache-line boundary followed seven instructions, ensure that when processor pre-fetches instructions does find branch instruction, which cause pre-fetch from page outside EVPR. Then, locate other rfi/rfci instructions replace them with branch rfci instruction EVPR page. This made easier value EVPR known before run-time. This work-around requires that either: rfi/rfci instructions which will replaced within range branch instruction (32MB) from target EVPR page, branch relative instruction used replace rfi/rfci; EVPR page placed location where reached 'branch absolute' instruction, that EVPR[0:6]=0b0000000 0b1111111, branch absolute instruction used replace rfi/rfci. iii. contents SRR0/1 saved, SRR0 address target EVPR page, SRR1 current contents MSR, executed perform 32-bit "branch" EVPR page. This avoids address restrictions ii), means that additional code must inserted both before original save SRR0/1) target EVPR page, restore saved SRR0/1 values before executing rfi. avoid condition ensure that rfi/rfci executed virtual mode, except V=R, where virtual address rfi/rfci similar real address rfi/rfci target SRR0/2), instruction relocation will turned (SRR1/3[IR]=0). practice this subset work-around
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
icbt instructions executed with data relocation enabled cause incorrect instruction execution icbt misses UTLB does have permission access page.
CPU_208
Category: Overview: icbt instructions executed with data relocation enabled (MSR[DR] cause incorrect instruction execution icbt misses UTLB does have permission access page. icbt cause instruction cache deliver incorrect instructions fetcher number events must line Conditions: Data relocation enabled (MSR[DR] Either condition true. page referenced icbt instruction found UTLB. page referenced icbt instruction marked protected settings. cache line fill completes while execute logic requesting instruction cache unit perform icbt. fetcher requesting address cache line followed request previous cache line. This condition occurs when fetcher re-requests data thrown away because there room fetch queue. same cycle conditions icbt must presented instruction cache. instruction cache must accept fetch request this cycle, does accept icbt. Impact: incorrect instruction executed after execution icbt instruction. Note, this erratum does affect compiler generated code. icbt instruction compiler generated instruction. Work-around: Perform following: Ensure data relocation disabled (MSR[DR] when executing icbt instruction. When data relocation enabled, ensure page referenced icbt instruction UTLB protected access control settings. When data relocation enabled, execute isync instruction after every icbt instruction.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_209
lwarx, stwcx. instruction sequence cause branch link register (bclr) branch count register (bcctr) instruction execute incorrectly.
Category: Overview: branch conditions branch link register (bclr) branch count register (bcctr) instruction incorrectly evaluated executed following lwarx, stwcx. instruction sequences given Code Sequence Code Sequence address address address address A+12 Code Sequence address address lwarx mtlr stwcx. bclr Code Sequence address address address address A+12 Code Sequence address address lwarx mtctr stwcx. bcctr
address address address Impact:
lwarx form branch link instruction that taken target Instruction stwcx. bclr
address address address
lwarx form branch decrement instruction that taken target Instruction stwcx. bcctr
Branch link register (bclr) branch count register (bcctr) instructions branch correct direction following lwarx, stwcx. instruction pair Code Sequence Note: lwarx stwcx instructions compiler generated. Work-around: Avoid executing Code Sequence performing following work-arounds: Perform Place more instructions between lwarx stwcx. instructions. Place instructions between lwarx stwcx. instructions. lwarx stwcx. separated instruction, make sure this instruction mtctr mtlr instruction. Avoid placing branch link branch decrement instruction immediately after lwarx instruction.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Interrupted stwcx. instructions errantly write data memory under certain conditions.
CPU_210
Category:
Overview: There three resources that aligned stwcx. instruction with write permission alter: storage location data-side effective address reservation set. field (CR0) indicate success failure store data-side effective address. reservation cleared. PPC405 core breaks stwcx. into pieces execute (EXE) stage. first piece moves writeback (WB) stage performs access check store operation reservation set. first piece does cause storage exception second piece updates moves stage clears reservation when stage. Under certain data cache unit (DCU) conditions first piece stwcx. become immune interrupts leaving stage while second piece stwcx. remains susceptible interrupts because stalled stage. second piece then interrupted asynchronous interrupt, reservation field updated data errantly written memory reservation were set. Impact: Cannot reliably stwcx. instructions presence asynchronous interrupts under certain conditions. Note that compilers generate stwcx. instructions. Work-around: Perform following: work-around required stwcx. instruction used. work-around required asynchronous interrupt handlers guaranteed return interrupted stwcx. without having executed other lwarx stwcx. instructions. However, operating systems which asynchronous interrupts perform task switching usually cannot relied upon exhibit such behavior. stwcx. instructions that executed supervisor mode (MSR[PR]=0), mask asynchronous interrupts (MSR[CE,EE,ME,DE]) before executing stwcx. unmask asynchronous interrupts immediately after executing stwcx. stwcx. instructions that executed user mode (MSR[PR]=1), perform following sequence mask asynchronous interrupts before executing stwcx. unmask asynchronous interrupts after executing stwcx. (MSR[CE,EE,ME,DE]):
(with parameter mask asynchronous interrupts) stwcx. (with parameter unmask asynchronous interrupts)
Note that system call handler have updated support parameters mask unmask asynchronous interrupts.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_210 Continued
Perform following: Insert sync dcbt instruction before stwcx. instruction. dcbt used, same stwcx. instruction. dcbt instruction result better performance than sync instruction.
dcbt RA,RB (The same used stwcx. instruction.) stwcx. RS,RA,RB
interrupt handlers execute sync dcbt instruction just before executing rfci. dcbt used, ensure that effective address will result machine check. Note that dcbt non-cacheable address dcbt page that UTLB page without read permission still provides intended effect. (dcbt instructions generate DTLB Miss interrupts they generate Data Storage Interrupts.)
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Incorrect data flushed from data cache.
CPU_213
Category: Overview:
CoreConnectarchitecture based PPC405CR consists masters slaves interconnected Processor Local (PLB). PPC405 features separate master interfaces instruction cache unit (ICU) data cache unit (DCU). load, store, data cache control instruction result issuing more transactions through interface. Whether given data operation results transaction depends factors including cacheability referenced address and, case cacheable access, state data cache. Once initiates read write request transaction proceeds with timing that dependent both slave responsible servicing given address activity that occurring between other masters slaves. PPC405 interface performs following specific sequence operations incorrect data flushed from data cache: Data cache flush line1 (line write): This flush pre-conditioning operation tightly coupled with sequence operations defined steps 2-5. only required that this flush last data side write prior steps 2-5. Data cache fill line2 (line read): This fill replaces dirty line causes flush step Data cache fill line3 (line read): This fill different congruence class than line2 data cache fill. cause data replaced flushed. Non-cacheable write-through write word4 (word, halfword byte write): timing request this write must occur within narrow window immediately after receives last data item from data cache fill line3. Data cache flush line2 (line write): This flush data cache fill line2 step data written memory incorrect. this erratum occur slave servicing data cache fill line3 must return cache line data four consecutive cycles. Since data buses 64-bits wide slaves PPC405CR feature 32-bit external buses, line fill data most cases returned every other cycle. data returned consecutive cycles slave must have accepted line fill request from pipelined transfer, read buffered line contents from external memory while same time another transaction between different master slave maintained ownership on-chip read data bus. instruction sequence that cause above series data side operations follows: load store instruction that misses data cache causes fill line with Least Recently Used (LRU) pointing valid dirty line, dcbf line with valid dirty data: This instruction causes flush line1. load store instruction that misses data cache causes line fill line with pointing valid dirty line: This instruction causes both fill line2 subsequent flush dirty contents line2 that were replaced fill. store instruction that misses data cache causes line fill: This instruction causes fill line3 result line flush. store instruction memory address designated either non-cacheable write-through: This instruction causes non-cacheable write word4. load instruction requiring data from either both last 64-bit doublewords returned cache line fill line3. This load does cause operation, required create conditions necessary cause this erratum.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
CPU_213 Continued
These instructions need execute with particular timing relative each other. Rather, they separated other unrelated instructions operations including branches, interrupts, instruction cache misses, additional loads stores that data cache. Impact: Incorrect data flushed (written) memory from data cache. Work-around: Perform following work-arounds: CCR0 reserved bits When these bits there line fill pending progress data cache miss data cache prevented from servicing other load store requests. Because this work-around blocks data cache accesses during line fills affect performance. Mark data memory write-through using DCWR register storage attribute each entry.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Writing decompression controller (DCP) registers corrupt contents decompression controller error status register, DCP0_ESR.
DCP_2
Category: Overview: This erratum applies when operating with decompression controller enabled. decompression controller enabled when ignore k-bit decompression controller configure register disabled, DCP0_DFG[IK]=0. Writing decompression controller registers corrupt contents decompression controller error status register, DCP0_ESR. Impact: contents DCP0_ESR reliable. Work-around: After writing decompression controller registers, clear DCP0_ESR register writing 0xFFFFFFFF example code below template implementing this work-around.
Function: ppcMtdcp0_cfg Description: Move DCP0_CFG register Input: value DCP0_CFG. Output: none define decompression DCRs #define dcp0_cfgaddr 0x014 #define dcp0_cfgdata 0x015 define decompression register offsets #define dcp0_cfg 0x00 #define dcp0_esr 0x52 .text .align .globl ppcMtdcp0_cfg ppcMtdcp0_cfg: addi %r4,%r0,dcp0_cfg mtdcr dcp0_cfgaddr,%r4 mtdcr dcp0_cfgdata,%r3 addi %r3,%r0,0xFFFF addi %r4,%r0,dcp0_esr mtdcr dcp0_cfgaddr,%r4 mtdcr dcp0_cfgdata,%r3
write DCP0_CFG with 0xFFFFFFFF, value clear DCP0_ESR
.type ppcMtdcp0_cfg,@function .size ppcMtdcp0_cfg,.-ppcMtdcp0_cfg
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
DCP_6
Executing instructions from memory region configured uncompressed after executing instructions from memory region configured compressed cause Decompression Controller (DCP) generate machine check exception hang PLB.
Category: Overview: decompression controller (DCP) hang generate incorrect error condition following sequence events occurs: fetches instruction from target instruction address (TIA1). TIA1 located memory region that configured compressed fetch does instruction cache. reads begins decompressing block instructions from external memory that contains instruction TIA1. fetches instruction from target instruction address (TIA2). TIA2 located memory region that configured uncompressed. This fetch misses I-cache step still progress. instruction execution flow such that aborts request made step step still progress. core fetches instruction from target instruction address (TIA3). TIA3 located memory region that configured compressed. This fetch misses I-cache step still progress. acknowledges request made step same time read from step completes. events occur: other transfer present next clock cycles, causes instruction machine check. This results DCP0_ESR register indicating that error time-out occurred during index table entry (ITE) compressed block fetch. another transfer present next clock cycle, hangs. Note, memory region configured compressed either: MSR[IR] corresponding SU0R register MSR[IR] corresponding entry memory region configured uncompressed either: MSR[IR] corresponding SU0R register MSR[IR] corresponding entry Impact: Once decompression controller enabled begins execute instructions from compressed memory region, instructions from uncompressed region cannot reliably executed. only instructions from compressed memory regions executed once decompression controller enabled, there impact. Work-around: execute instructions from uncompressed memory region once instructions have been executed from compressed memory region.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Compressed instruction blocks that cross boundary external memory cause Decompression Controller (DCP) return incorrect instructions processor core.
DCP_9
Category: Overview: decompression controller uses burst read transfers read compressed instruction blocks from external memory into internal byte buffer. compressed instruction block crosses boundary, SDRAM controller External Controller (EBC) terminates burst boundary. Under certain conditions, when restarts burst, will return invalid instructions processor core. Incorrect program results, program exception (ESR[PIL]=1) occur. Impact: Compressed code blocks cannot cross boundary external memory. Work-around: Obtain CodePack Code Compression Utility version 2.54 later). utility optional parameter that will take into account specified boundary when placing compressed instruction blocks into target address space. Slightly lower compression results experienced when using this feature because small unused holes left prior specified boundary. compression utility template file, specifying following parameter causes utility avoid boundaries when placing compressed instruction blocks into target address space:
0x00000400
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
EBC_5
Category: Overview:
Peripheral bank external controller cannot programmed "Write Only" bank.
Setting Bank Usage field Peripheral Bank Configuration Register (EBC0_PB4CR[BU]) b'10 does configure bank "Write Only" bank. Impact: Read access peripheral bank cannot removed without disabling both read write access. Work-around: peripheral bank write-only peripheral devices.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
parity generated during memory-to-peripheral write.
EBC_20
Category: Overview:
Setting parity enable controller register does produce expected results during memory-to-peripheral writes. drives PerPar0:3 instead parity. Impact: memory-to-peripheral mode cannot used parity required. Work-around requires bank. Work-around: recommended work-around hardware device paced memory-to-memory transfers. This type transfer still initiated using DMAReq, stated section user's manual, chip select used place DMAAck. unused bank required since chip select needed. bank must properly configured accessing memory perform memory-to-memory transfers bank's parity enable (EBC0_BnAP[PEN]) must set. address pins ignored. only requirement when programmed source/destination address registers match address range configured bank.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
IIC_6
Category: Overview:
Slave Transfer Count cleared correctly.
Slave Transfer Count (IIC0_XFRCNT) cleared when Slave Write Complete (IIC0_XTCNTLSS[SWC]) Slave Read Complete (IIC0_XTCNTLSS[SRC]) status bits cleared. cleared when Slave Write Needs Service (IIC0_XTCNTLSS[SWS]) Slave Read Needs Service (IIC0_XTCNTLSS[SRS]) bits Extended Control Slave Status register (IIC0_XTCNTLSS) cleared. transfers bytes fewer "Needs Service" bits set, only "Complete" bits set. Thus, smaller transfers, Slave Transfer Count (IIC0_XFRCNT) will cleared zero when completed transfer slave been handled (i.e. when slave transfer complete status cleared transfer count cleared). Impact: smaller transfers, Slave Transfer Count (IIC0_XFRCNT) will cleared zero when completed transfer slave been handled (i.e. when slave transfer complete status cleared transfer count cleared). Work-around: Manually write bits Transfer Count register (IIC0_XFRCNT) just prior clearing "Complete" status bit, (IIC0_XTCNTLSS[SWC] IIC0_XTCNTLSS[SRC]).
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
controller temporarily placed invalid state.
IIC_7
Category: Overview:
Loss arbitration address byte during 10-bit read operation temporarily places Controller into invalid state. 10-bit read, transaction proceeds follows: Start, Address Byte with write operation, Address Byte Repeated Start, Address Byte with read Where Address Byte value 0xF0 through 0xF7 transmission Address Byte uses exact same value 1st. Thus, malfunction during transmission address byte (the address byte transaction described above). Controller resumes normal operation once current transfer ends once starts. Impact: controller temporarily placed invalid state. Work-around: None needed.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
IIC_9
Category: Overview:
Loss Arbitration while sending address byte(s) causes auto-retry transfer.
situation described below, Controller will automatically retry transfer. Instead performing automatic retry, Controller should abort transfer. system having masters, Controller (M1) Master (M2), slave, assumed this example that start exactly same time write same address bytes (After sending byte neither master issues STOP because both masters want bus.) then issue repeated STARTS exactly same time. transfer being arbitrated read transfer from transfer being arbitrated write transfer. loses arbitration wins, owns bus. waits until issues STOP then *AUTOMATICALLY* retries failed read. While owns bus, send several bytes data problem occurs when reads bytes set-up information sent prior losing arbitration. This data have been overwritten. overwritten, will unknowingly read incorrect data. Impact: multiple master configuration, Controller read corrupted data from slave there loss arbitration described overview. Work-around: following steps describe work-around: Find illegal unused address that close 0x06 0x07. possible either 0x06 0x07 these reserved addresses. Precede writes reads that must done shared slave using Hold Ownership Control register (i.e. operations that must done slave with exclusive ownership bus) with write bytes zero data, 0x00, address chosen step Wait interrupt from core. error status should along with incomplete transfer aborted bits extended status register. core will indicated Halt/Stop status register extended status register shows that core Master Transfer state (bits 1:3) Perform desired operations using Hold Ownership control register.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
loss Arbitration while sending address cause Controller malfunction.
IIC_10
Category: Overview:
Controller PPC405CR loses arbitration while sending address bit, does properly transition from master state slave state. Therefore, does acknowledge transfer addressed slave another master. This non-acknowledgement will cause master either issue STOP re-do failed transfer. either case, Controller recovers correctly responds master. Note: Controller addressed slave, this problem does occur. Impact: There slight loss performance. Work-around: master that wins arbitration should re-do transfer transfer fails.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
IIC_11
Category: Overview:
Controller when operating slave correctly decode 10-bit address.
Controller when operating slave 10-bit address mode correctly decode 10-bit address. This problem occurs when master addresses Controller slave. Note: Controller when operating slave correctly decodes address 7-bit address mode. Impact: Some addresses cannot used. Work-around: Avoid using following values Slave Address" (IIC0HSADR) Slave Address" (IIC0LSADR) registers: Note that X="don't care" V="a particular value" Address "1111_0xxx" Address, Slave Address should 10-bit addresslike code. Example good settings: setting: Adr= 0xF0 Adr=0xF0 Good setting: Adr= 0xF0 Adr= 0x70 other Slave Address "VVVV_VVVV0" then this Slave Address cannot "VVVV_VVV1", must different more than just least significant bit. example: another slave Address 0x70, then core cannot have Address 0x71. good setting core would 0x73 0x72. other Slave Address "VVVV_VVVV1" then this Slave address cannot "VVVV_VVV0", must different more than just least significant bit. example: another slave Address 0x71, then core cannot have Address 0x70. good setting core would 0x72 0x73.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Controller does automatically awaken when slave transfer detected.
IIC_12
Category: Overview:
slave transfers PPC405CR will acknowledged Controller asleep. Impact: Controller does automatically awaken when slave transfer detected. Work-around: Perform following steps: Awaken Controller clearing field Enable Force (CPC0_ER[IIC]=0 CPC0_FR[IIC]=0) registers. Have master re-send non-acknowledged transfer.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
IIC_13
Category: Overview: controller malfunction multi-master environment under following conditions:
hang multi-master environment during address byte 10-bit read operation.
controller another master believe they bus. controller another master initiate 10-bit read operation same time. controller another master access same slave address. controller operates lower frequency than other master. master uses minimum permissible hold time repeated start operation. controller wins arbitration address that follows repeated start signal least does loose arbitration).
When these conditions occur controller does detect fall therefore sync with address bits sent bus. Impact: controller either hangs does not-Acknowledge transfer. Work-around: work-around described IIC_9.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Incomplete transfer status incorrectly after loss arbitration.
IIC_14
Category: Overview:
When controller does chained write byte followed another write (chained non-chained), core loses arbitration within byte second write, Incomplete Transfer Extended Status register incorrectly logic one. Since arbitration lost during byte, byte still master data buffer. status therefore incorrect. Impact: false error condition recorded Extended Status Register. Work-around: Perform following: work-around described IIC_9. Ignore Incomplete Transfer when Lost Arbitration Master Data Transfer Count 0x0.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
IIC_16
Category: Overview: data received when slave data buffer full (i.e. contains four bytes data) lost. Impact: Data received slave mode lost. Work-around: wait until slave data buffer full before reading Bridge operating Asynchronous Mode. PCIClk ranges affected this erratum typical clock configurations: 100MHz, SyncPCIClock 50MHz, 35MHzPCIClk51MHz 133MHz, SyncPCIClock 66.7MHz, 46.7MHzPCIClk66.7MHz 133MHz, SyncPCIClock 44.4MHz, 31.1MHzPCIClk46MHz
Received data slave mode lost.
Note: SyncPCIClock internal clock derived from PCIClk supplied bus. PCIClk outside failing frequency range such that
Incorrect address write data driven during transfer.When
Bridge Controller initiator (Dual Address Cycle) transfer Asynchronous Mode, drive incorrect address and/or write data values bus. This error occur internal SyncPCIClock externally supplied PCIClk have clock periods within ±2ns another. following PCIClk frequency ranges typical clock configurations that affected this erratum: 100MHz, Sync 33.3MHz, 31MHzPCIClk36MHz 100MHz, Sync 50MHz, 45MHzPCIClk55MHz 133MHz, Sync 66.7MHz, 59MHzPCIClk66.7MHz Note: cycles used address targets address space above Gigabytes. SyncPCIClock internal clock derived from PCIClk supplied bus. following clock configurations: Clk/SyncPCIClock/PCIClk 100MHz/100MHz/66MHz, 100MHz/50MHz/33MHz, 133MHz/44MHz/33MHz.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Incorrect data stored PLB0_ACR during read after write sequence.
PLB_4
Category: Overview:
write operation (mtdcr) Arbiter Control Register (PLB0_ACR) immediately followed read operation (mfdcr) same register, PLB0_ACR will latch instead intended write data. Impact: Incorrect data stored PLB0_ACR. Work-around: read PLB0_ACR register immediately after writing Separate read from write PLB0_ACR with read register other than PLB0_ACR.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
SDRAM_10 Command leadoff settings (SDRAM0_TR[LDF]) more MemClkOut cycles always generate expected minimum delay.
Category: Overview: SDRAM0_TR[LDF] parameter controls number clock cycles from address/command assertion bank select (/BankSeln) assertion. settings more MemClkOut cycles, SDRAM Controller does always generate expected minimum delay. This error occurs when /CAS remains asserted between successive read write commands. these cases, minimum delay MemClkOut cycles instead. Impact: Most systems affected this erratum since SDRAM0_TR[LDF] typically MemClkOut cycles. SDRAM timing cannot with delay MemClkOut cycles, SDRAM controller must lower frequency. Work-arounds: systems affected this erratum, SDRAM Controller must lower frequency. Refer chapter PPC405CR User's Manual select clock ratio generating lower MemClkOut frequency.
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405xx_600_errata_.fm.6.0.0 2003
Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
SDRAM_12 SDRAM controller issue unexpected mode register command.
Category: Overview: This erratum only occur when SDRAM controller Burst Read Prefetch Granularity bytes, SDRAM0_CFG[BRPF]=2'b10. When SDRAM controller PPC405CR initialized issues Mode Register Write (MRW) command SDRAM memory. This command encoded SDRAM address serves configure SDRAM memory device interface parameters including latency, burst order, burst length. Once initialized, SDRAM controller never issues another command SDRAM memory. normal operation, controller auto-refreshes SDRAM memory regular intervals determined setting Refresh Timer Register, SDRAM0_RTR. When refresh scheduled occur, SDRAM controller should wait in-progress SDRAM data transfers complete, precharge open SDRAM memory pages, then issue auto-refresh command memory. SDRAM controller programmed Burst Read Prefetch Granularity bytes, SDRAM0_CFG[BRPF]=2'b10, SDRAM controller wait current SDRAM transaction complete incorrectly superimpose precharge command onto SDRAM address/control bus. this occurs time when /CAS SDRAM will presented with unexpected command. specific mode register value written memory indeterminate corresponds whatever address SDRAM controller driving time unexpected command. After being reprogrammed with incorrect mode register value correct data transfer between SDRAM memory subsystem PPC405CR longer possible. Impact: Incorrect data read and/or written SDRAM memory. Work-arounds: Program SDRAM Burst Read Prefetch Granularity bytes setting SDRAM0_CFG[BRPF]=2'b01. This default, recommended value documented PPC405CR User's Manual. Note that selecting prefetch granularity bytes does improve performance some instances actually result lower throughput extra data unnecessarily read from SDRAM.
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
UART_1
Category: Overview:
Reading UARTx_IIR cause interrupt lost incorrect status read.
interrupt pending status, UARTx_IIR[IP], delayed on-chip processor (OPB) clock cycle relative interrupt priority, UARTx_IIR[IPL], when UARTx_IIR updated. following situations where this error observed: There cycle window where UARTx_IIR[IPL] field holds status interrupt condition while interrupt pending bit, UARTx_IIR[IP], indicates pending interrupt. There cycle window where interrupt priority field been cleared, UARTx_IIR[IPL]=0b000, because interrupt condition longer true interrupt pending UARTx_IIR[IP] indicates interrupt pending. Transmit Hold Register Empty interrupt (THRE) lost UARTx_IIR read during clock cycle when UARTx_IIR[IPL] bits indicate THRE condition UARTx_IIR[IP] indicates interrupt pending. this case, reading UARTx_IIR will clear interrupt condition PPC405 will never UARTx_IIR[IP] indicate that interrupt occurred. Impact: PPC405 read incorrect status detect pending interrupt reading UARTx_IIR. Work-arounds: Perform following: Poll UART transmitter receiver status reading Line Status Register (UARTx_LSR). time PPC405 read UARTx_IIR register after line status register indicates that transmitter empty, interrupt pending cleared. Evaluate UARTx_IIR register value using both interrupt priority level field interrupt pending determine interrupt pending. bits UARTx_IIR[IPL] field UARTx_IIR[IP] cleared, interrupt occurred.
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Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Design Notes:
When processor powered (i.e., OVdd additional precautions needed powered. Under this circumstance, processor high-impedance state damaged and/or experience degradation reliability. (Note: I/Os tolerant which implies that voltage these I/Os high 5.5V.) following critical items must considered: input voltage PPC405xx/NPe405x exceeds protection diode drop supplied with current excess 147mA, I/Os will permanently damaged. (Vsource (4*0.8)/(Rsource) Vsource source voltage 5.5V maximum Rsource source resistance Pull-up Resistor 0.147 (5.5 3.2)/Rsource Rsource 2.3/0.147 15.65 ohms (minimum) Raising value from this minimum 15.65 ohms and/or reducing Vsource from will give added margins safety against being permanently damaged. sustained (i.e. several hours) maximum current greater than will weaken degrade reliability I/Os. improve reliability choose pull-up resistor, Rsource, greater than ohms, 0.0081 (5.5 3.2)/Rsource ohms. (The recommended value Rsource processor data sheet ohms. ohms minimum protection against damaging currents ohms maximum that guarantees logic 1/high with pull-up.) series resistor ensure that voltages applied inputs exceed drop across diodes when OVdd choice series resistor depends pull-up resistor used required voltage levels inputs other devices (Vih, SDRAM controller does support mixing non-ECC memory banks. default, control signals PPC405CR (DMAReqn, DMAAckn, EOTn/TCn) active high, whereas these signals were active PPC403 series processors. polarity each these signals individually programmable through Polarity Control Register (DMA0_POL). avoid generating extraneous interrupts when waking Universal Interrupt Controller (UIC), perform following steps before enabling sleep mode, CPC0_ER[UIC]=1, after disabling sleep mode, CPC0_ER[UIC]=0. Prior enabling sleep mode: Save contents Masked Status Register (UIC0_MSR). Save contents Enable Register (UIC0_ER). UIC0_ER zero. (Disable interrupts.) After exiting sleep mode: Write ones complement saved contents UIC0_MSR UIC0_SR. Restore state UIC0_ER. application note, "Using Spread Spectrum Clock Generator with PowerPC 405GP"
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PPC405CR (IBM25PPC405CR-3xCxxxCx)
Revision
Contents Modification Errata document version 3.0.0 Items added: design note IIC_13, IIC_14, IIC_16, UART_1 Items Removed because they apply: Changed item numbers following items: Item Number 1_CHIP Errata document version 4.0.0 Modified introduction (page Errata document version 6.0.0 Items added: CPU_213, EBC_20, SDRAM_12 Item Number EBC_5 CPU_147 CPU_162 CPU_121 IIC_6 IIC_7 IIC_9 IIC_10 IIC_11 IIC_12 DCP_2 CPU_190 CHIP_11 CPU_197 CHIP_3 CPU_200 CPU_201 DCP_6 DCP_9 CPU_208 CPU_209 CPU_210 SDRAM_10 PLB_4
August 2002
November 2002 2003
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Errata
PPC405CR (IBM25PPC405CR-3xCxxxCx)
Copyright International Business Machines Corporation 2003
Rights Reserved Printed United States America 2003 following trademarks International Business Machines Corporation United States, other countries, both. Logo PowerPC CodePack CoreConnect
Other company, product, service names trademarks service marks others. information contained this document subject change without notice. products described this document intended implantation, life support, space, nuclear, military applications where malfunction result injury death persons. information contained this document does affect change product specifications warranties. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. information contained this document obtained specific environments, presented illustration. results obtained other operating environments vary. This document intended hardware system manufacturers developers applications, operating systems, tools, firmware, other software. provided describe conditions under which errata occur hardware enable conduct your investigation into your system software impacted integrate workarounds needed. This document lists errata that characterized 2003. does represent warrant that this errata list complete. errata this list future. Please check with your sales representative regularly verify that have most current version this document. INFORMATION CONTAINED THIS DOCUMENT PROVIDED BASIS. event will liable damages arising directly indirectly from information contained this document. Microelectronics Division 1580 Route Bldg. Hopewell Junction, 12533-6351 home page found http://www.ibm.com Microelectronics Division home page found http://www.ibm.com/chips 405xx_600_errata_.fm.6.0.0 2003
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Universal Interrupt Controller This document contains errata desi

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