Gigabit ethernet eXtender Sublayer (XGXS) Intellectual Property (IP) C

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Gigabit ethernet eXtender Sublayer (XGXS) Intellectual Property (IP) C

Datasheet Thumbnail

Top Searches for this datasheet

Gigabit Ethernet XGXS Intellectual Property Core
Gigabit ethernet eXtender Sublayer (XGXS) Intellectual Property (IP) Core enables creation system solutions Gigabit Ethernet applications defined IEEE 802.3ae. This Core targets programmable array section ORCA® ORT82G5 FPSC provides bridging function between Media Independent Interface (XGMII) Attachment Unit Interface (XAUI) devices. implemented soft core flexibility. XGMII interface block provides interface Gbits/s Ethernet MACs. XGMII double data rate, parallel short-reach (typically less than inches) interconnect interface. XAUI high-speed interconnect that offers reduced count ability drive inches trace standard FR-4 material. Each XAUI interface comprised self-timed 8b10b encoded serial lanes, each operating 3.125 Gbits/s. core from Lattice Semiconductor provided with implementation scripts, test benches, documentation allow customers integrate functions 10GbE LAN/WAN applications also modification core meet differing application needs.
Gigabit Ethernet ORT82G5 Core Features
embedded portion ORT82G5 includes: Eight channels 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding Fibre-channel XAUI compliant lane-by-lane synchronization Lane deskew function PRBS generator/checker selftest Microprocessor interface programmable ORCA Series system soft XGXS core implements interface functions needed take data from XAUI lanes XGMII interface device (e.g. MAC) vice-versa. programmable logic implementation allows changes core reflect changes standards definition future. XGMII consists lanes, labeled [0:3], clock both transmit receive directions. Each lane 8-bit data path plus control signal. Double Data Rate (DDR) signaling used transfer 312.5 MBytes/s lane with 156.25 clock. data control lines sampled both rising falling edges clock. XGXS's location 10GbE protocol stack shown Figure following page
www.latticesemi.com
pbxgxsip_02
Lattice Semiconductor
Figure XGXS Location Protocol Stack
Gigabit Ethernet XGXS Intellectual Property Core
Upper Layers Control (Optional) Media Access Control Reconciliation XGMII XGXS* XAUI XGXS* XGMII Physical Coding Sublayer Interface Sublayer XSBI Physical Medium Attachment Physical Medium Dependent Medium
XGMII XGXS XAUI XSBI
Medium Independent Interface XAUI Extended Sublayer Attachment Unit Interface Sixteen Interface Medium Dependent Interface
XGMII XAUI Coding
WAN-Compatible Framing
16-bit Parallel (OIF) Retime, SerDes,
Notes: Adding makes Denotes Optional Sublayer
receive path, shown Figure data path from XAUI XGMII interface. maps 8b10b decoded XAUI data XGMII data optionally transmits data off-chip 36-bit 156Mhz XGMII interface. Figure XGXS Receive Path Dataflow
XAUI Lane Lane Lane Lane
XGXS Receive Function
abcde 1XXX Properly Aligned Columns
10B8B Decoding
XGXS Mapping XGMII Decoding Serial Stream (output)
Octet Octet Octet Octet
transmit path, shown Figure data path from XGMII XAUI. XGXS transmit path maps 36bit XGMII data control 8b10b transmission code. XGMII data control clocked registers blocks. slip buffer performs clock compensation between external clock internal synthesized 156.25 clock. Data control read from buffer then passed into idle generation logic.
Lattice Semiconductor
Figure XGXS Transmit Path Dataflow
Octet Octet
Gigabit Ethernet XGXS Intellectual Property Core
Octet
Octet Serial Stream (input)
XGMII Encoding
XGXS Transmit Function
XGXS Mapping
8B10B Encoding
abcde XAUI Lane
Lane
Lane
Lane
Figure Generator/Checker Interface
xgmii_rx_clk XGMII
xgmii_ref_clk
Backplane
ORT82G5
REFCLK[N,P]_B HDINN_BA
Lane rx_dat Frame Capture Check rx_control bits Lane Receive XGXS Lane Lane
HDINP_BA HDINN_BB HDINP_BB HDINN_BC HDINN_BC HDINN_BD HDINN_BD HDOUTN_BA
rx_clk
tx_dat Frame Generator tx_control bits Transmit XGXS Lane Lane Lane Lane
HDOUTP_BA HDOUTN_BB HDOUTP_BB HDOUTN_BC HDOUTP_BC HDOUTN_BD HDOUTP_BD
tx_clk
XGMII xgmii_tx_clk
Software Register Interface (MDIO)
Figure Interface with External
XAUI 3.125Gbps
ORT82G5 FPSC
XGXS 8B10B Encode/ Decode, ByteAlignment, Deskew XGXS XGMII Transmit Receive Interface
XGMII 36-bit 156.25 36-bit 156.25
3.125Gbps
10Gb Ethernet
XAUI Connector
Lattice Semiconductor
Gigabit Ethernet XGXS Intellectual Property Core
Ethernet, idle generation state machine generates random /A/, characters. Idle signal XGMII mapped random sequence /A/, code groups reduce radiated emissions help designers meet requirements. code-groups included purpose lane alignment and, that end, have guaranteed minimum spacing code-groups. code-groups contain comma sequence used XAUI receive section establish code-group alignment. code-groups used clock-compensation inserted deleted XGXS accommodate differences between transmit receive clocks. ORT82G5 XGXS interfaces XGMII ways: built-in 64-bit 156Mhz XGMII CRPAT/CJPAT packet generator/checker (Figure standard 36-bit interface (e.g. MAC) (Figure Figure ORCAstra Interface
Using ORCAstra® control center, graphical user interface similar shown Figure performs real time modifications monitoring. addition FPSC specific functions shown Figure entries XGXS specific registers, such FIFO threshold, loopback modes control, push buttons specific synchronization algorithms. Control over internal packet generator functions, monitoring internal packet generator error outputs also available.
Other Information
Product briefs, data sheets, application notes other information many products used above system solutions available from Lattice Semiconductor. FPSC solutions also highlighted Lattice Semiconductor website http://www.latticesemi.com.
Ordering Information
Implementing design ORT82G5 requires ispLEVERsoftware ORT82G5 FPSC Design Kit. ordering information, please contact your local Lattice Semiconductor sales representative visit Lattice Semiconductor website.

Gigabit ethernet eXtender Sublayer (XGXS) Intellectual Property (IP) C

Top Searches for this datasheet

Other recent searches