ispPAC30 Introduction ispPAC®30 Imagine designing your multi

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ispPAC30 Introduction ispPAC®30 Imagine designing your multi

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IN-SYSTEM PROGRAMMABLE ANALOG FRONT CIRCUIT
ispPAC30
Introduction ispPAC®30
Imagine designing your multi-channel data acquisition system using analog circuit capable changing gain offset, channel, microseconds digitally! That what with versatile dynamically reconfigurable ispPAC30 device.
Dynamically Reconfigurable Analog Device
Data Acquisition Systems Analog Front Laser Diode Control Voltage Monitoring Linear Signal Processing Sensor Signal Conditioning Medical Scientific Instrumentation Automated Test Equipment
Designing with ispPAC30
ispPAC30 device consists programmable gain instrumentation amplifiers, Multiplying DACs, configurable output amplifiers with rail-to-rail outputs. analog routing pool summation routing between input output sections, along with programmable elements ispPAC30 device both reprogrammable (E2CMOS®) reconfigurable (SRAM). Circuits designed, simulated downloaded into ispPAC30 device with PAC-Designersoftware, intuitive Windows-based design environment.
Features Benefits
Programmable Analog
ispPAC30 Block Diagram
In-System Reprogrammable Reconfigurable Independent Gain Offset Control Data Acquisition System Easily Adapts Design Changes Field Upgradable through Software External Components Needed Configuration SRAM Registers Unlimited Reconfigurability Non-Volatile E2CMOS Cells (10,000 Cycles) IEEE 1149.1 JTAG Programming Input Output Analog Routing Pool Interconnects PACells Allows On-The-Fly Reconfigurability Avoids Parasitic Effects Printed Circuit Routing
Vref1
Filter Amplify Integrate Compare
Summation Routing Pool
Input/Output Routing Pool
MDAC MDAC
Filter Amplify Integrate Compare
Input PACells Output PACells Precision Programmable Gain (±0.01 ±400) Continuous-Time Precision Filters 1.55 MHz) Analog Signal Arithmetic (Sum, Subtraction MDAC) Programmable Integration Time Constant On-Chip Offset Calibration Offset Voltage (<200 Gain Error (<1%) Rail-to-Rail Output Swing Dual Programmable Precision Voltage References Power Down Features 10µA Standby 24-Pin SOIC 28-Pin Single Supply Operation
Vref2
JTAG/SPI Interface Logic Configuration Memory
Auto-Calibration 2.5V Reference
ispPAC30 Specifications
25°C; 5.0V; 0V<VIN<2.8V; Output Load 50pF, IA1, IA2, MDAC1 connected IA3, IA4, MDAC2 connected OA2; Auto-cal initiated prior. (Unless otherwise specified).
SYMBOL
VIN±
PARAMETER
Input Voltage Range Differential Offset Voltage (Input Referred)
CONDITION
MIN.
TYP.
MAX.
UNITS
Analog Input
250µA 250µA Individual Input Amplifier Gain VOUT 0.5V 4.5V Gains Minimum 8-bit Overdrive 10mV Overdrive 100mV 4.95 4.50
4.97 4.65 0.03 0.11
Analog Output
Output Voltage Swing High Output Voltage Swing
0.05 0.15
Static Performance
Programmable Gain Range Gain Error Small Signal Bandwidth Integral Non-linearity Error Propagation Delay
1.57
Multiplying Digital-to-Analog Converter (MDAC) PACell
±0.5
Comparator
Small Signal Bandwidth Gain
Gain Gain Gain Gain 100k
Frequency
Total Harmonic Distortion (dB)
Output Amplitude (dB)
Gain Gain
-100
100k
Frequency (Hz)
Frequency (Hz)
Also Available ispPAC10 Device-In-System Programmable Analog Circuit ispPAC20 Device-Multipurpose Analog with ispPAC80 Device-Programmable Analog 5th-Order Filter PAC-Designer Software ispPAC Evaluation Boards ispPAC System Design Kits
More Information
www.latticesemi.com
Applications Support 1-800-LATTICE (528-8423) (408) 826-6002 ispPACs@latticesemi.com
Copyright 2001 Lattice Semiconductor Corporation. Lattice Semiconductor, (stylized) Lattice Semiconductor Corp., Lattice (design), ISP, ispPAC, PAC-Designer, PACblock, PACell E2CMOS either registered trademarks trademarks Lattice Semiconductor Corporation United States and/ other countries. Other product names used this publication identification purposes only trademarks their respective companies.
September 2001 Order I0127

ispPAC30 Introduction ispPAC®30 Imagine designing your multi

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