Dahn Ngoc APPLICATION NOTE AN-32 INTRODUCTION Tradition
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IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
Dahn Ngoc
APPLICATION NOTE AN-32
INTRODUCTION
Traditionally, signal processing tasks were performed with specialized analog processors. However, well known that digital techniques have some inherent advantages such flexibility, accuracy, reliability over analog techniques. Moreover, because rapid progress digital computer VLSI technology, both digital processing units storage devices becoming less expensive year year. Therefore, digital approach usually preferred over modern signal processing. Digital filtering most important digital signal processing techniques. This technique found many applications variety areas. Perhaps most widely known applications digital filtering have been area speech processing communication. many situations, speech signals degraded ways that limit their effectiveness communication. such cases digital filtering techniques applied improve speech quality remove noise echoes from speech, etc.). Lowpass bandpass digital filters have also been utilized speech analysis synthesis, speech coding, data compression. Digital filtering techniques have also been widely used area image processing: enhancement image make more acceptable human eye; removal effects some degradation mechanism; separation features easier identification measurement human machine. example, two-dimensional digital filters reduce spatial low-frequency components X-ray image, this process will make features with large high-frequency components such fracture lines easier identify.
digital filter said causal realizable output dependent only values input This implies that impulse response h(n) zero most important subset class causal digital filters that where transfer function H(z) described Nth-order rational function
H(z) h(k)z-k (2-1)
FILTERS
digital filter said finite impulse response (FIR) filter number nonzero h(k) finite. Otherwise, said infinite impulse response (IIR) filter. readily seen that filters, denominator H(z) i.e. transfer function becomes H(z) h(0) h(1)z-1 h(2)z-2 h(N)z-N a1z-1 a2z-2 aNz-N
(2-2)
output Nth-order filter calculated from input data follows: y(k) a0µ(k) a1µ(k-1) a2µ(k-2) aNµ(k-N), (2-3) with initial conditions: µ(-1) µ(-2) µ(-N) Therefore, filters nonrecursive implemented using adders, multipliers delay elements without feedback path. canonical form filter illustrated Figure
BASIC THEORY DIGITAL FILTERS
General Form digital filter system device which transforms input sequence {µ(k)} into output sequence {y(k)}. shown Figure digital filter characterized impulse response {h(k)} transfer function H(z).
µ(k)
H(k) h(k)z
µ(k)
µ(k-1)
y(k)
µ(k-2)
y(k)
2585
Figure Block Diagram Digital Filter
µ(k-N+1)
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output sequence calculated from input sequence follows:
y(n) h(k) µ(n-k)
logo registered trademark Integrated Device Technology, Inc. ©1996
µ(k-N)
Figure Block Diagram Canonical Filter
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IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
Filters other hand, filters recursive, i.e., output filters calculated from both input data previous output data follows: y(k) b1y(k-1) b2y(k-2) bNy(k-N) a0µ(k) a1µ(k-1) a2µ(k-2) aNµ(k-N),
y(k) transversal structure simply weighted current input µ(k) delayed inputs µ(k-1), µ(k-2). coefficient determine frequency response particular filter such lowpass, bandpass highpass.
µ(k) µ(k-1) µ(k-2) µ(k-3) µ(k-6) µ(k-7)
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(2-4)
with initial conditions: µ(-1) µ(-2) µ(-N) canonical form filters shown Figure While filters have advantages being unconditionally stable, less sensitive quantization error linear phase, filters have lower order than filters with equivalent performance. Therefore, filters require less memory fewer arithmetic operations than filters.
µ(k)
y(k)
y(k)
µ(k-4)
µ(k-1)
y(k-1)
µ(k-5)
µ(k-2)
y(k-2)
µ(k-N+1)
y(k-N+1)
Figure 8-Tap Transversal Structure
µ(k-N)
y(k-N)
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Figure Block Diagram Canonical Filter
this application note, will discuss various implementations both filters using building block family: IDT7320, 16-bit 8-level pipeline register; IDT7210, 16x16-bit multiplier-accumulator; IDT7216 16x16-bit multiplier IDT7383, 16-bit ALU.
IMPLEMENTATIONS FILTERS
There many filter structures. particular structures universally utilized: transversal structure lattice structure. Transversal Structure transversal structure rather direct realization equation (2-3) terms delays, multiplications, additions. shown Figure 7th-order (8-tap) filter, output
Figure illustrates implementation 8-tap transversal structure using IDT7320s IDT7210. IDT7320 storage input data, other storage filter coefficients. IDT7210 used perform multiplication accumulation. Registers IDT7320s connected input registers IDT7210, respectively. Both IDT7320s shifted every clock cycle. Thus, input data coefficients loaded into input registers IDT7210 sequence shown Figure first clock cycle, input word loaded into pipeline registers A1-G1 shift down. next seven clock cycles, output connected input that pipeline registers A1-G1 shift ring every clock cycle. Similarly, output connected input output unloaded every eight clock cycles. sequence controller generates clock control signals ACC. filter coefficients preloaded into pipeline registers A2-H2. Generally, N-tap transversal structure, filter cycle clock cycles. Therefore, filter cycle time NStMA, where 25ns multiply-accumulate time IDT7210.
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
INPUT µ(k) IDT7320 µ(k-1) µ(k-2) µ(k-3) µ(k-4) µ(k-5) µ(k-6) µ(k-7) CLOCK CLOCK IDT7210 MULTIPLIER ACCUMULATOR OUTPUT y(k)
Figure Implementation Transversal Structure Using IDT7320s IDT7210
IDT7320
SEQUENCE CONTROLLER
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IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
25ns CLOCK
IDT7320
Sample µ(k) Shift
IDT7320
IDT7210
µ(k-7)
µ(k-6)
µ(k-5)
µ(k-4)
µ(k-3)
µ(k-2)
µ(k-1)
µ(k)
IDT7210
FILTER CYCLE (200ns)
2585
Figure Operation Sequence IDT7320s IDT7210 Transversal Structure
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
Lattice Structure lattice structure Nth-order filter shown Figure lattice structure equivalent transversal structure, sense that transfer function which represented transversal structure
STAGE µ(k) STAGE
also represented within multiplicative constant lattice structure. origin utility structure that several advantages over transversal structure field adaptive filtering.
STAGE
y(k)
(k-1)
(k-1)
(k-1)
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Figure Block Diagram Lattice Structure
From Figure that Nth-order lattice structure consists stages, each having inputs outputs. outputs {efm(k), {ebm(k), (1mN) stage called mth-order forward backward prediction errors, respectively, which related inputs stage (the outputs previous stage) follows: efm(k) ef(m-1)(k) km-1 eb(m-1)(k-1) ebm(k) eb(m-1)(k-1) km-1 ef(m-1)(k) where input first stage ef0(k) eb0(k) µ(k) (3-1c) (3-1a) (3-1b)
Equation (3-1) shows that need store {eb0(k-1), eb1(k-1), eb(N-1)(k-1)}, backward prediction errors time k-1, calculating outputs stages time {eb1(k), ef1(k), eb2(k), ef2(k), ebN(k), efN(k)}. implementation 8-stage lattice structure given Figure using IDT7320s, 7216s, 7383s. IDT7320s store previous outputs eb0(k-1), eb1(k-1), eb7(k-1) coefficients multiplications km-1 eb(m-1)(k-1) km-1 ef(m-1)(k) performed IDT7216s. IDT7383s execute subtractions ef(m-1)(k) 1)(k). km-1 eb(m-1)(k-1) eb(m-1)(k-1) km-1ef(m-
filter cycle consists clock cycles. first clock cycle, eb0(k-1) µ(k-1) stored loaded into registers stored loaded into registers input µ(k) f0(k) loaded into registers input µ(k) eb0(k) also loaded into After time delay tMUC 30ns, results multiplication appear output pins IDT7216s which directly connected input IDT7383s. Then, after another time delay tALU 25ns, obtain outputs first stage, eb1(k) ef1(k), output pins IDT7383s. second clock cycle, eb1(k-1) stored stored ef1(k) appeared output port IDT7383 loaded into corresponding input registers IDT7216s 7383s. same time, eb1(k) loaded into After time delay tMUC tALU 55ns, obtain eb2(k) ef2(k), output pins IDT7383s, Finally, eighth cycle, obtain eb8(k) y(k) ef8(k). should noted that each clock cycle, IDT7216s first perform multiplication, then IDT7383s complete subtraction. Therefore, time clock cycle tMUC tALU 55ns. Nth-order lattice filter, filter cycle time nanoseconds (440ns signals I0-3 control which register IDT7320 backward prediction error will written. signals SEL0-2 select eight registers IDT7320s read from output port. sequence controller needed generate clock control signals I0-3 SEL0-3. filter coefficients k0-k7 preloaded into registers A2-H2.
sequence operations shown Figure
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
µ(k)
IDT7320 (k-1) (k-1) (k-1) (k-1) (k-1) (k-1) CLOCK (k-1) (k-1) CLOCK IDT7320 CLOCK SEQUENCE CONTROLLER
IDT7216
IDT7383
IDT7383
IDT7216
MULTIPLIER
MULTIPLIER
b1(k), (k),
(k), (k), y(k)
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Figure Implementation Lattice Structure Using IDT7320s, IDT7216s IDT7383s
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
55ns CLOCK
µ(k)
-X1Y -X2Y
-X1Y -X2Y
A1-H
µ(k) b0(k)
FILTER CYCLE
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Figure Operation Sequence IDT7320s, IDT7216s IDT7383s Lattice Structure
Equation (4-2) written time domain
IMPLEMENTATIONS FILTERS
Since filters have feedback elements, architecture implementing filters more complex than those filters. Moreover, roundoff errors multiplication accumulate amplified through feedback loop that roundoff noise filter output becomes serious problem. However, IDT's flexible high-precision product lines provide unique solution implementing filters. There variety structures implement filters, such direct form structure, cascade structure, parallel structure, lattice structure, ladder structure, state-space structure. Among these, direct form, parallel cascade structures popular many applications. following, will consider implement these filter structures using IDT7320, 7210, 7383. Direct Form Structure direct form structure simplest implementation filters requires fewest multiplication, addition delay elements. This means that achieve higher speed needs less hardware than other structures. disadvantage direct form structure that have multiplication roundoff noise. This overcome using high-precision 16-bit multiplier-accumulator (MAC), where whole 32-bit product preserved used accumulator. U(z) Y(z) z-transforms input {µ(k)}
Y(z) H(z) U(z) U(z) A(z) B(z) (4-1)
Define W(z) U(z), obtain B(z)
w(k) µ(k) b1w(k-1) b2w(k-2) bNw(k-N) (4-3a) y(k) a0w(k) a1w(k-1) a2w(k-2) aNw(k-N)(4-3b) From (4-3), direct form structure filter shown Figure direct form structure
w(k) y(k)
w(k-1)
w(k-2)
w(k-N+1)
U(z).
w(k-N)
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output {y(k)}, respectively, then filter described W(z)B(z) U(z) Y(z) A(z)W(z). (4-2)
Figure Block Diagram Direct Form Structure
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
implemented using single MACs. Implementation Using Single Using single MAC, each input µ(k), first calculate w(k) given (4-3a), then calculate y(k)
INPUT µ(k) IDT7320 w(k-1) w(k-2) w(k-3) w(k-4) w(k-5) w(k-6) w(k-7) w(k-8)
3b). implementation 7th-order filter shown Figure Three IDT7320s used store {w(k)}, coefficients {b1, coefficients {a0, a7}. input µ(k) data {w(k)} stored IDT7320 sent input port IDT7210 through multiplexer, while
IDT7320
IDT7320
CLOCK
IDT7210
CLOCK SEL0-4 SEQUENCE CONTROLLER
MULTIPLIER ACCUMULATOR w(k)
FILTER OUTPUT y(k)
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Figure Direct Implementation Filter Using Single
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
coefficients {a0, sent input port IDT7210 through another multiplexer. shown Figure each filter cycle consists clock cycles. first eight clock cycles calculate w(k) while last eight clock cycles calculate y(k). first clock cycle, input µ(k) content loaded into input registers IDT7210. Since stored result obtained output register IDT7210 µ(k). second clock cycle, contents sent input registers IDT7210,
25ns CLOCK
Then, ninth clock cycle, w(k) obtained output register IDT7210. tenth cycle, load w(k) into which will used sixteenth cycle. Before w(k) loaded, eighth cycle, shift down pipeline registers A1-H1, that ninth cycle, data stored w(k-8) w(k-7) which multiplied stored output y(k) obtained first clock cycle next filter cycle. should noted that this implementation, obtain different data output ports IDT7320s using output selection signal SEL0-2,
IDT7320 µ(k)
HOLD
SHIFT HOLD w(k)
HOLD
IDT7210
IDT7210
P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY P+XY FILTER CYCLE (400ns)
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Figure Sequence Operations IDT7320s IDT7210 Direct Form Implementation Using Single
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
shifting pipeline registers every clock cycle. Implementation Using MACs implementation mentioned above, single calculate w(k) y(k) alternately. MACs, calculating y(k) given y(k) (4-4a)
another simultaneously calculating w(k+1) given w(k+1) (4-4b)
INPUT µ(k) IDT7320 w(k)
then processing speed doubled. implementation 7th-order filter using IDT7210s shown Figure filter cycle clock cycles shown Figure first cycle, µ(k+1) loaded into register multiplied content which one, that result output register still µ(k+1). next seven cycles, w(k- w(k-5), w(k) loaded into register through multiplexer multiplied respectively. eighth cycle, shift down pipeline registers A1-H1 prepare next filter cycle. Then, first clock cycle next filter cycle, obtain w(k+1) output register which loaded into second clock cycle. When IDT7210 calculates w(k+1), another IDT7210
IDT7320
IDT7320
w(k-1) w(k-2) w(k-3) w(k-4) w(k-5) w(k-6) w(k-7)
CLOCK
IDT7210 IDT7210 CLOCK SEQUENCE CONTROLLER
MULTIPLIER ACCUMULATOR w(k+1) MULTIPLIER ACCUMULATOR FILTER OUTPUT y(k)
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Figure Direct Form Implementation Filter Using MACs
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
25ns
CLOCK
IDT7210
µ(k+1)
IDT7210
IDT7210
IDT7210
IDT7210
HOLD FILTER CYCLE (200ns)
SHIFT
HOLD
w(k+1)
2585
Figure Sequence Operations IDT7320s IDT7210 Direct Form Implementation Using MACs
calculates y(k) output unloaded from register every clock cycles. Whether using single MACs, signals control whether pipeline registers shift hold which register IDT7320 result w(k) will written. other hand, signals SEL0-2 select eight registers IDT7320s read from output port. sequence controller generates clock control signals. filter coefficients preloaded into IDT7320s filter case. Parallel Structure parallel structure advantage less multiplication roundoff noise coefficient quantization sensitivity than direct form structure. However, parallel structure uses more hardware. basic principle parallel structure that Nth-order rational transfer function
(4-5)
parallel structure shown Figure minimize roundoff noise coefficient sensitivity, Hi(z) usually first-order filter second-order filter
(4-8)
which implemented direct form structure mentioned before. example, fourth-order filter implemented with parallel sections, each being secondorder filter, shown Figure this particular implementation, each section uses MACs. outputs sections added IDT7383 obtain filter
INPUT DATA {µ(k)}
expanded partial fraction follow H(z) H1(z) HM(z) (4-6)
expansion suggests that filter could implemented
(4-7)
FILTER OUTPUT {y(k)}
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Figure Parallel Structure Filters
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
INPUT µ(k)
IDT7320
IDT7320
IDT7320
IDT7320
IDT7320
IDT7320
7210
7210
7210
7210
SECOND-ORDER SECTION
SECOND-ORDER SECTION
IDT7383
y(k)
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Figure Parallel Implementation Fourth-Order Filter Using Second-Order Sections
output {y(k)}. Cascade Structure Like parallel structure, cascade structure advantage less multiplication roundoff noise coefficient quantization sensitivity disadvantage more hardware than direct form structure. basic principle cascade structure decompose Nth-order rational transfer function given (4-5) into first-order secondorder sections follows: H(z) H1(z)S SHM(z) (4-9)
where Hi(z) given (4-7) (4-8). From decomposition, filter (4-5) implemented direct form structure. example, fourth-order filter implemented with cascade sections, each being second-order filter, shown Figure output first section input second section.
INPUT DATA {µ(k)} FILTER OUTPUT {y(k)}
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Figure Cascade Structure Filters
IMPLEMENTATION DIGITAL FILTERS USING IDT7320, IDT7210, IDT7216, IDT7383
APPLICATION NOTE AN-32
INPUT µ(k)
FIRST SECTION
SECOND SECTION
IDT7320
IDT7320
IDT7320
IDT7320
IDT7320
IDT7320
7210
7210
7210
7210
SECOND-ORDER SECTION
SECOND-ORDER SECTION
y(k)
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Figure Cascade Implementation Fourth-Order Filter Using Second-Order Sections
CONCLUSIONS
this application note, have discussed basic methods implement variety structures both filters using building block family: pipeline registers, MACs, multipliers, ALUs. Which structure implementation should selected particular application decided many factors such available filter design tools, cost, speed, etc. many applications, transversal structures used because simplicity filter design implementation. lattice structure employed application where filter coefficients have adaptively changed fast convergency coefficients required. applications requiring high speed compact hardware, filters usually preferred. Different filter structures have completely different finite wordlength effects (roundoff error, coefficient error limit cycles). direct form structure simplest uses least hardware. However, filter order large bandwidth filter very narrow, then direct
form structure have severe roundoff noise limitcycles that actual input-output characteristic filter dramatically deviates from ideal one. this situation, parallel structure cascade structure should utilized. building block approach discussed this application note achieve times performance some simple filter structures. Table gives comparison between building block approach using IDT's building blocks single chip approach using latest Texas Instruments TMS320C25-50, single chip digital signal processor with instruction cycle time 80ns. IDT's extensive flexible product lines provide various possibilities implement different filter structures. filter implementations filter direct form implementations shown this application note, have using most MACs, multipliers ALUs. number clock cycles filter cycle proportional filter order. more MACs, multipliers ALUs used, filter cycle contain only single clock cycle achieve highest speed.
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