Mapper 16-Channel TXC-04216 TECHNICAL OVERVIEW FEATURES Add/drop

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Mapper 16-Channel TXC-04216 TECHNICAL OVERVIEW FEATURES Add/drop

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E1Mx16 Device
Mapper 16-Channel TXC-04216 TECHNICAL OVERVIEW FEATURES
Add/drop sixteen 2.048 Mbit/s signals from STM-1 VC-4/AU-3, STS-3, STS-1 Independent drop timing modes Selectable HDB3 positive/negative rail interface. Performance counter provided illegal coding violations Digital desynchronizers 16-byte ETSI trail trace comparison Drop buses monitored parity, loss clock, upstream multiframe errors Tandem Connection ETSI message processing generation Performance counters provided TU/VT pointer movements, BIP-2 errors Block Errors (REIs) TU/VTs monitored Loss Pointer, Data Flags (NDFs), AIS, Remote Defect Indication (RDI), size errors (S-bits) Byte Signal Label Mismatch Unequipped detection facility line loopbacks, generation BIP-2 errors, send capability Intel Motorola compatible microprocessor interface with interrupt capability Programmable internal RISC processor implements VT-POH VT-alarm handling Boundary scan capability (IEEE 1149.1) Single +5V, power supply 388-lead plastic ball grid array package
Mapper 16-Channel device designed add/drop multiplexer, terminal multiplexer, dual single unidirectional ring applications. Four field-proven QE1M Quad Mapper chips interconnected single compact package permit higher application board densities. Sixteen 2.048 Mbit/s signals mapped from asynchronous Tributary Unit-12s (TU-12s) Virtual Tributary (VT2s). E1Mx16 interfaces multiple-segment, byte-parallel SDH/SONET-formatted Telecom 19.44 Mbit/s byte rate STM-1/STS-3 operation 6.48 Mbit/s byte rate STS-1 operation. This permits E1Mx16 connect directly other TranSwitch devices application designs. signals either HDB3 positive/negative rail format. E1Mx16 provides performance counters, alarm detection, ability generate errors Alarm Indication Signals (AIS). facility line loopback capabilities also provided.
APPLICATIONS
STM-1/STS-3/STS-1 2.048 Mbit/s add/drop mux/demux Unidirectional bidirectional ring applications STM-1/STS-3/STS-1 termination terminal mode multiplexer STM-1/STS-3/STS-1 test equipment
STM-1/STS-3/STS-1 TELECOM SIDE
External Clock
2.048 Mbit/s TRIBUTARY SIDE
side drop side side drop side
Channel
data clock receive transmit, plus receive data zero-output control
E1Mx16 Mapper 16-Channel TXC-04216
Boundary Scan Microprocessor Controls interface
Channel
U.S. Patents 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218 U.S. and/or foreign patents issued pending Copyright 2000 TranSwitch Corporation E1Mx16 trademark TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
Document Number: PRELIMINARY TXC-04216-MA November 2000
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
PRELIMINARY information documents contain information products sampling, pre-production early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
TABLE CONTENTS
Section Page List Figures Overview Features Application Examples Functional Description Selected Parameter Values Package Information Ordering Information Related Products Documentation Update Registration Form*
Please note that TranSwitch provides documentation products. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
LIST FIGURES
Figure Page Typical Application using E1Mx16 E1Mx16 TXC-04216 Block Diagram 2048 kbit/s Asynchronous Mapping E1Mx16 TXC-04216 388-Lead Plastic Ball Grid Array Package
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
OVERVIEW
E1Mx16 (TXC-04216) provides mapping sixteen 2048 kbit/s asynchronous signals into multiple-segment, byte-parallel, SDH/SONET Telecom STM-1, STS-3, AU-3/STS-1 formats, using sixteen programmed asynchronous mode TU12/VT2 tributary signals. E1Mx16 interfaces SDH/SONET side four segments defined A-side Drop Add, B-side Drop Add. Selected TU-12/VT2 tributaries mapped from either SDH/SONET column format. Using dual architecture, E1Mx16 configured system dropping TU-12/VT2 from either only, adding TU-12/VT2 either only, dropping adding TU-12/VT2 either sides, dropping TU-12/VT2 from either sides, adding TU-12/VT2 opposite (e.g. drop from dropping TU-12/VT2 from either buses adding TU-12/VT2 both buses. timing side derived from either Drop bus, input signals bus. Each drop optional byte detector detecting starting location byte TU-12/VT2. Instead using detector, pulse inputted E1Mx16. Each Drop also equipped with optional H1/H2 bytes detector detecting upstream state. Each selected TU-12/VT2 both and/or drop buses pointer tracking state machine determining location overhead bytes asynchronous frame bits. Each overhead bytes selected TU-12/VT2 monitored control status information. E1Mx16 configured perform 16byte trail trace message comparison, tandem connection message comparison generation with error counters status alarm indications, single-bit enhanced 3-bit RDI, REI, signal label mismatch unequipped detection generation, byte access. E1Mx16 provides desynchronizer/synchronizer each port. 8-bit pointer leak rate register provided. E1Mx16 satisfies various jitter tolerance, jitter transfer, mapping jitter, combined jitter requirements found ANSI documents. Each asynchronous line inputs individually configured provide either interface dual unipolar rail type interface. When configured rail interface, B3ZS CODEC converts rail signals from signal. Coding violations counted 16-bit counter. overhead byte processing, E1Mx16 uses internal SPOT (SDH/SONET Processor Overhead Termination). SPOT divided into four segments corresponding four groups four mappers. SPOT performs many overhead processing functions, such message comparisons. Programming SPOT performed through microprocessor bus. microprocessor access four separate segments SPOT which have individual select leads, corresponding four groups four mappers. SELp microprocessor port select signals. SEL1 selects first group four mappers (channels 1-4) SEL2, SEL3 SEL4 select other three groups four mappers. E1Mx16 compatible with either Intel Motorola split microprocessors. E1Mx16 also provides interrupts microprocessor operational alarm status indications. Detailed information E1Mx16 device provided Data Sheet, document number TXC-04216-MB, which made available customer TranSwitch Internet site www.transwitch.com.
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
FEATURES
following features supported E1Mx16:
SDH/SONET FORMATS: STM-1 AU-4 VC-4 TUG-3 TUG-2 format STM-1 AU-3 TUG-2 STS-3 STS-1 OPERATING MODES: E1Mx16 supports following modes operation which programmable microprocessor. Drop mode only (Add tristated) Drop from mode only Single unidirectional ring Drop from Drop from Multiplexer Drop from Drop from Dual protection ring Drop from Drop from TIMING: E1Mx16 provides following timing modes lead selection with software overwrite: Drop timing timing derived from same named Drop timing timing independent Drop SDH/SONET INTERFACE: STM-1/STS-3 19.44 Mbyte/s parallel interface STS-1 6.48 Mbyte/s parallel interface Drop timing enabled Drop inputs: Clock, SPE, C1J1V1, Data parity outputs: data, parity active indication -4PRELIMINARY TXC-04216-MA November 2000
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
timing enabled Drop inputs: Clock, SPE, C1J1V1, data, parity indication inputs: Clock, C1J1V1 outputs: Data, parity active active indication Stuck clock indications Input parity check with alarm monitoring Odd, even, data only, signals Input loss clock detection Stuck high SDH/SONET interface buses, Output parity generation Odd, even, data only, signals indication (polarity selectable through control bit) Ability High-Z output signals MAPPINGS: E1Mx16 following mapping features: Maximum ports asynchronous mappings TU-12/VT2 TU-12/VT2 selection Drop (common sides) (common sides) User's responsibility maintain TUG-2/VT group mappings SDH/SONET FEATURES: In-band upstream path line detection H1/H2 pointer bits bytes (majority vote) TU/VT pointer tracking sides ETSI 1015-based state machine Size error indication 4-bit increment/decrement counters TU/VT Drop selection TU/VT pointer generation Fixed 2048 kbit/s asynchronous format
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
order TU/VT byte processing byte (programmable port) 64-byte host processor read cycle alignment) 16-byte host processor read with message comparison byte (Z7) byte Single-bit enhanced 3-bit alarm detection event option, selectable through software control bit) (FEBE) counter bits) BIP-2 detector counter bits) with block error count Detect (bit byte) Signal label mismatch, unequipped detection, Access byte (Z6) byte Host processor access Tandem connection option with: Multiframe pattern alignment 16-byte message comparison RDI, alarm detection counters byte access Line generation SDH/SONET alarms with: Masks Microprocessor control order TU/VT byte insertion byte with 64-byte message (Z7) byte with: (FEBE) insertion (from receive side) insertion (microprocessor control) BIP-2 calculation insertion insertion (from receive side) with: Enable bits alarms Microprocessor control Single-bit enhanced 3-bit (selectable through software control bit) Control spare bits byte (Z6) byte Microprocessor Tandem connection insertion with: Multiframe pattern generation 16-byte message RDI, generation with: Alarms microprocessor control AIS, generation Unequipped channel generation with supervisory equipped generation TU/VT generator -6PRELIMINARY TXC-04216-MA November 2000
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
Desynchronizer Meet ETSI ANSI performance requirements for: Pointer test sequence Jitter External clock (also used line generation) O-bit channel microprocessor access selected TU-12/VT2 LINE INTERFACE: Individual port rail interface selection interface detection External loss signal inputted negative rail Programmable clock edge Rail Interface HDB3 CODEC Bipolar violation counter bits) Loss signal detection detection Quiet feature Force receive output High-Z feature TEST FEATURES: Boundary Scan based IEEE 1149.1 EXTEST, SAMPLE, BYPASS test instructions Loopbacks port Facility Line High-Z output leads option BIP-2 error mask port Force inverted value continuous error mask port Force sent Pseudo-random test generator analyzer port 215-1 pattern defined O.151
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
MICROPROCESSOR INTERFACE: Split Intel Motorola Interrupt support Positive, negative, positive/negative alarm transition Positive level option Software polling registers Mask alarm hierarchy Hardware enable control Hardware sense control Reset control bits Hardware reset Full software reset Software reset alarms Software reset port Counter reset port SPOT (internal processor) reset SPOT PROCESSOR: Microcode supplied initialization Downloaded through memory Sanity alarms
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
APPLICATION EXAMPLES
E1Mx16 used wide range telecommunication data communication applications: Terminal Multiplexers, with redundancy Add/Drop Multiplexers TU/VT tributaries Add/Drop Multiplexers protection rings
following diagram illustrates typical application using E1Mx16. WEST TERMINAL STM-1/STS-3 PHAST-3N (TXC-06103) Drivers/Receivers
DROP DROP MICROPROCESSOR
EAST TERMINAL PHAST-3N (TXC-06103) Drivers/Receivers
STM-1/STS-3
E1Mx16 TXC-04216
E1Mx16 TXC-04216
channels STS-3 Figure Typical Application using E1Mx16 application diagram Figure shows fully configured bidirectional add/drop fiber multiplexer. Using full four-bus capability E1Mx16, channels dropped from either direction with full time slot reuse both directions. Using only Drop buses provides add/drop service back network source only, eliminates block marked "East Terminal" terminal configuration.
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E1Mx16 TXC-04216
FUNCTIONAL STM-1/STS-3/STS-1 TELECOM SIDE 2.048 Mbit/s TRIBUTARY SIDE
EXTCK ADCLK ADSPE ADC1J1V1 AD(7-0) ADPAR ADINDp Destuff Desync TU/VT Terminate Side Repeated Ports through Receive Drop) TU/VT Terminate Side HDB3 Coder QUIETpn RPOpn RNOpn RCOpn
Add/Drop Interface Channel blocks #1-16
Receive Drop)
AACLK AASPE AAC1J1V1 AA(7-0) AAPAR AADDp AAINDp
SPOT RISC Processor
Alarms Controls
Alarms Controls, Timing Transmit Add) TU/VT Build Side Stuff/Sync Side HDB3 Decoder Transmit Add) TU/VT Build Side Stuff/Sync Side Repeated Ports through TPIpn TNIpn/TLOSpn TCIpn
BDCLK BDSPE BDC1J1V1 BD(7-0) BDPAR BDINDp
Note: p=1-4; n=1-4 Channel blocks)
Test Access Port Interface (Boundary Scan)
Add/Drop Interface Channel blocks #1-16
Channel
Channel
BACLK BASPE BAC1J1V1 BA(7-0) BAPAR BADDp BAINDp
RESET
HIGHZ ABUST TESTp TESTp TXCTI(1-5)
Microprocessor Interface Common Control/Status
Note: p=1-4 (for four groups four mappers)
SELp MOTO RD/WR
INTSH
(7-0)
DTACKp (10-0)
IRQp
MOTOROLA
SELp MOTO
INTSH
(7-0) (10-0)
RDYp
INTp
INTEL
Figure E1Mx16 TXC-04216 Block Diagram
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
block diagram Mapper 16-Channel device shown Figure E1Mx16 interfaces four buses, designated Drop, Drop, Add, Add. four buses STM-1/STS-3 rate 19.44 Mbyte/s, STS-1 rate 6.48 Mbyte/s. North American applications, asynchronous signals carried floating Virtual Tributary (VT2) format Synchronous Transport Signal (STS-1), STS-1 that carried Synchronous Transport Signal (STS-3). ITU-T applications, signals carried floating mode Tributary Unit (TU-12) format STM-1 Virtual Container structure (VC-4) using Tributary Unit Group (TUG-3), STM-1 Virtual Container structure (VC-3) using Tributary Unit Group (TUG-2) mapping schemes. Sixteen signals dropped from Drop Drop), from combination drop buses, lines. Sixteen asynchronous signals converted into TU-12 format added either both buses, depending upon mode operation. When E1Mx16 configured drop timing, buses are, definition, bytesynchronous multiframe-synchronous with their like-named drop buses, delayed byte time because internal processing. example, byte STM-1 Virtual Container structure (VC-4) using Tributary Unit Group (TUG-3) TU-12/VT2 added bus, time placement derived from Drop timing, from software instructions specifying which TU/VT number being dropped/added. When device configured timing, bus, parity, indicator signals derived from clock, C1J1V1 signals. Receive block identical Receive block. TU/VT Terminate block repeated times, each port sides). Destuff, Desync, HDB3 Coder blocks repeated sixteen times, each port. interface between drop Receive block consists input leads, optional output lead: byte clock, byte-wide data, C1J1 indicator which carrying indication making signal C1J1V1 indicator, indicator, parity lead last-named leads. Parity selectable control bits even parity data byte only. output lead optional TU/VT select indicator signal. Drop C1J1V1 signal used conjunction with Drop signal determine location various pulses. pulse identifies location byte when signal low. single pulse identifies starting location byte VC-4 format, when signal high. Three pulses provided STS-3 format, each identifying starting location byte each STS-1 signals. E1Mx16 operate with pulse C1J1V1 signal, internal detector determining location pulse. pulse location used determine location pointer byte STM-1 VC-4 operation, C1J1V1 signal used, single pulse must occur during three drop clock cycles every four frames following pulse when signal high. STS-3 operation, three pulses must present every four frames. Each three pulses must present three clock cycles after corresponding pulse, when signal high. example, VC-4 signal, pulse identifies byte location (defined starting location VC-4) bytes. next column (first clock cycle) rows assigned fixed stuff. Similarly, next column (second clock cycle) rows assigned fixed stuff. next column (third clock cycle) defines start TUG-3 This column where pulse occurs every four frames. However, actual byte location clock cycles after pulse. STS-1 operation, pulse must present C1J1V1 signal used. pulse must occur next clock cycle after pulse, when signal high. pulse identifies byte location (defined starting location STS-1) bytes. next column (first clock cycle) start. Thus, pulse identifies starting location first byte signal. rest bytes TU-12/VT2s also aligned with respect pulse. Each monitored parity errors, loss clock, multiframe alignment selected, upstream SDH/SONET indication. E1Mx16 monitor either bytes H1/H2 bytes indication. Which byte H1/H2 bytes selected function TU/VT selected.
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
Each TU/VT Terminate block side) performs pointer processing based location bytes. pointer bytes monitored loss pointer, indication, NDF. pointer tracking process based latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer increments decrements also counted, SS-bits monitored correct value. This block also monitors various alarms found (formerly known bytes, including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection error counter, counter, three indications. E1Mx16 performs 16-byte trail trace comparison channels selected. 64-byte messages, bytes stored memory segment microprocessor read cycle. device also provides tandem connection feature performs 16-byte message comparison (formerly known byte message. control each port selects TU/VT from either Drop Drop bus. TU/VT destuffed Destuff block using majority logic rules three sets three justification control bits determine S-bits data bits frequency justification bits. Desync block removes effects output systemic jitter that might occur because signal mappings pointer movements network. Desync block contains parts, pointer leak buffer, loop buffer. pointer leak buffer accept five consecutive pointer movements, adjust effect over time. Loop Buffer consists digital loop filter, which designed track frequency received signal remove both transmission stuffing jitter. option each port provides either data, HDB3-encoded positive negative rail signal interface. Receive data (towards line), sixteen channels, clocked either rising falling edges clock. addition, control bits provided forcing data clock signals high impedance state (tri-state). control lead provided forcing output leads state. direction, E1Mx16 accepts clock either data HDB3-encoded positive negative rail signals. Data, sixteen channels, clocked either falling rising edge clock. mode, external loss clock indication input signal provided. rail signal, coding violations counted, there monitoring loss signal. E1AIS detector also provided. data signal written into FIFO Stuff/Sync blocks. Threshold modulation used frequency justification process. Timing information from drop used read FIFO perform TU/VT justification process. This block permits tracking incoming signal having average frequency offset high ppm, peak-to-peak jitter. Since E1Mx16 supports ring architecture, sets blocks provided each port. TU/VT selection same both blocks. control bit, transmit line alarms, generate E1AIS. TU/VT Build blocks format TU/VT into STS-1, STS-3 STM-1 structure asynchronous 2048 kbit/s signals, shown Figure pointer value carried bytes transmitted with fixed value 105. Transmit access provided overhead communications channel bits (O-bits) microprocessor. microprocessor also writes signal label, value message, either 16-byte 64-byte message. E1Mx16 provides tandem connection feature including transmission 16-byte message various alarms associated with tandem connection feature. device provides single-bit 3-bit using (Z7) bytes, respectively. Local alarms, microprocessor, generate remote payload, server, connectivity defect indications. Block Error FEBE (REI) inserted from BIP-2 errors detected receive side, BIP-2 parity generated byte. Control bits provided generating unequipped status, generating TU/VT AIS, inserting BIP-2 errors. ability generate Null Pointer Indicators (NPIs) also provided STM-1 VC-4 format.
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E1Mx16 TXC-04216
Figure 2048 kbit/s Asynchronous Mapping
VC-12 RRRRRRRR bytes (2048 kbit/s Data) RRRRRRRR bytes (2048 kbit/s Data) RRRRRRRR (Z6) bytes (2048 kbit/s Data) RRRRRRRR (Z7) bytes (2048 kbit/s Data) RRRRRRRR Bytes Path Overhead (V5) Byte BIP-2 BIP-2 Interleaved Parity bits) Remote Error Indication (formerly FEBE, Block Error Indication) Remote Failure Indication L1L2L3 Signal Label Remote Defect Indication (formerly FERF, Receive Failure Indication)
(FEBE)
TU-12/VT2 (Pointer Byte)
bytes
(Pointer Byte)
bytes
(Action)
Information Overhead communications Justification control Justification opportunity Fixed stuff (set
bytes
(Reserved)
bytes
Bytes
(FERF)
Signal Label
Data Flag Normal 0110, 1110, 0010, 0100 0111 1001, 0001, 1101, 1011 1000 Positive Justification Invert five I-bits Negative Justification Invert five D-bits Pointer Range decimal
Size S1S2
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TECHNICAL OVERVIEW
E1Mx16 TXC-04216
Transmit block identical Transmit block. interface between Transmit block consists three input leads eleven output leads, when timing mode selected. input leads byte clock, C1J1V1 indicator, indicator. output leads byte-wide data, parity indicator, indicator, optional TU/VT selection indicator signal. C1J1V1 signal used conjunction with signal determine location various pulses. option provided which drop side reference pulse, either from drop C1J1V1 indicator from multiframe detector, used side reference pulse. When drop timing selected, output leads byte-wide data, parity indicator, indicator, optional TU/VT selection indicator signal. clock, C1J1V1 signals disabled. E1Mx16 configured operate with either Intel Motorola-compatible microprocessors Microprocessor Interface blocks. Separate address, data control leads provided. microprocessor access four separate segments memory which have individual select, ready/acknowledge interrupt leads, corresponding four groups four mappers. Interrupt capability provided with mapper group individual mapper mask bits well activity registers guide software exact cause interrupt most expeditious manner. wide variety alarms provided mapper group level well mapper channel level. Each alarm error reflected current status register counter well latched value register that rising, falling, both transitions positive level alarm. latched value trigger interrupt, unless masked prevent causing interrupt. option provided which permits interrupt polarity inverted. Control bits provided which enable facility line loopback. Because complexity SDH/SONET interface timing modes, SDH/SONET loopback TU/VTs supported. SPOT (SONET Processor Overhead Termination) block RISC processor with associated instruction data memory that performs selected low-speed functions, including overhead processing counter maintenance. SPOT program must loaded into SPOT instruction memory after powerup. Executable microcode provided customer TranSwitch Internet site www.transwitch.com same microcode provided there QE1M product). four SPOT blocks programmed same time simultaneously activating four SELp leads write mode. Boundary Scan Interface Block provides five-lead Test Access Port (TAP) that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external leads from board component test. modified Boundary Scan Description Language (BSDL) file QE1M device, list which describes connections four QE1M chips within E1Mx16 package, combined file format. This file provided customer TranSwitch site, together with documentation E1Mx16 product.
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E1Mx16 TXC-04216
SELECTED PARAMETER VALUES
ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS Parameter Supply voltage input voltage Storage temperature range Ambient Operating Temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity Classification Latch-up Symbol -0.5 -0.5 +6.0 Unit
Conditions Note Note Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note Meets JEDEC STD-78
Level
absolute value 1500
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883D, Method 3015.7.
THERMAL CHARACTERISTICS Parameter Thermal Resistance: junction ambient Unit
oC/W
Test Conditions ft/min linear airflow.
POWER REQUIREMENTS Parameter Power dissipation, Power dissipation, 4.75 1400 1550 5.25 1627 1785 Unit STS-1 STS-1 STM-1 STS-3 STM-1 STS-3 Test Conditions
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PACKAGE INFORMATION
E1Mx16 device packaged 388-lead plastic ball grid array package suitable surface mounting, illustrated Figure
Bottom View
-E1-
TRANSWITCH
TXC-04216AIBG
Note E1/4
-D1-
D1/4
Dimension (Note (Nom) Notes: dimensions millimeters. Values shown reference only. Identification solder ball corner contained within this shaded zone. Package corner angle. (Nom) (Nom) (Ref.) (Nom) (Nom) (Ref.)
2.12 0.50 1.17 0.65 0.76 34.90 31.75 33.60 34.90 31.75 33.60 1.27
2.72 0.70
35.10 33.80 35.105 33.80
Figure E1Mx16 TXC-04216 388-Lead Plastic Ball Grid Array Package
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E1Mx16 TXC-04216
ORDERING INFORMATION
Part Number: TXC-04216AIBG 388-Lead Plastic Ball Grid Array Package
RELATED PRODUCTS
TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock Data Output). This device similar SYN155. both clock data outputs line side. TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). This dualmode device, which configured either emulate TXC-03001 device provide additional capabilities. TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line path overhead processing STM-1/STS-3/STS-3c signals. Compliant with ANSI ITU-T standards. TXC-03011, SOT-1E VLSI Device (SONET STS-1 Overhead Terminator). This device provides extended features relative 84-lead TXC-03001 TXC-03001B SOT-1 devices, 144-lead package. TXC-04252, QE1M VLSI Device (Quad AU-4/VT2 TU-12 Async Mapper-Desync). Interconnects four signals with four asynchronous mode TU-12 tributaries carried AU-4/AU-3 rate payload interface. TXC-06103, PHAST-3N VLSI Device (SONET STM-1, STS-3 STS-3c Overhead Terminator). PHAST-3N VLSI device provides Telecom interface downstream devices operates from power supply volts. combines functions SOT-3 SYN155C devices.
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NOTES
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NOTES
TranSwitch reserves right make changes product(s) circuit(s) described herein without notice. liability assumed result their application. TranSwitch assumes liability TranSwitch applications assistance, customer product design, software performance, infringement patents services described herein. does TranSwitch warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right TranSwitch covering relating combination, machine, process which such semiconductor products services might used.
PRELIMINARY information documents contain information products sampling, preproduction early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product. PRELIMINARY TXC-04216-MA November 2000
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would like receive updated documentation selected devices becomes available, please provide information requested below (print clearly type) then tear this page, fold mail Marketing Communications Department TranSwitch. Marketing Communications will ensure that relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins other publications sent you. also choose provide same information (203.926.9453), e-mail (info@txc.com), telephone (203.929.8810). Most these documents will also made immediately available direct download Adobe files from TranSwitch World Wide Site (www.transwitch.com). Name: Company: Title: Dept./Mailstop: Street: City/State/Zip: located outside U.S.A., please Country: _Postal Code: Telephone: Ext.: Fax: E-mail: Please provide following details managers charge following departments your company location. Department Company/Division Engineering Marketing Title Name
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Mapper 16-Channel TXC-04216 TECHNICAL OVERVIEW FEATURES Add/drop

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