Mapper 28-Channel TXC-04228 DATA SHEET FEATURES Twenty-eight inde
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T1Mx28 Device
Mapper 28-Channel TXC-04228 DATA SHEET FEATURES
Twenty-eight independent 1.544 Mbit/s mappers Single/dual byte-parallel Telecom 6.48 slots) 19.44 slots) Floating VT1.5 byte-synchronous mapping with signaling only with without slip buffer Asynchronous mapping SONET mapping (VT1.5) mapping (VC-4/AU-3/TU-11) B8ZS codec DS1s, Serial control line interface transceivers framers Telecom loopbacks with integral PRBS generator analyzer VT1.5/TU-11 pointer tracking generation VT1.5/TU-11 overhead processing insertion One-second latched performance registers counters alarm detection generation Internal ring port dual 14-channel mapper Gapped line clock option Internet applications without need framer Intel/Motorola-compatible microprocessor interface 3-bit support Boundary scan capability (IEEE 1149.1) Single +3.3 power supply 456-lead plastic ball grid array package
T1Mx28 28-channel byte-synchronous asynchronous mapper. Four field-proven DS1MX7 Mapper chips interconnected single compact package permit higher application board densities. Both SONET mappings provided Bellcore GR253-CORE (VT1.5) G.707 3-96. single-dual add/ drop Telecom provided that operate either 6.48 19.44 MHz, which compatible with other TranSwitch devices. VT1.5/TU-11 pointer tracking overhead extraction/processing with full error alarm control provided. VT1.5/TU-11 pointer calculation overhead assembly also provided. Alarm error mappings from drop SONET/SDH to/from provided. Jitter performance achieved with fully digital threshold modulator DPLL that meets GR-253-CORE MTIE requirements without external de-jitter buffers. line, AMI, B8ZS line codes supported with full alarm detection generation ANSI T1.231-1997. Each channel independently programmable mixed service applications. Access status control bits provided Intel/ Motorola-compatible microprocessor interface. Diagnostic, test, maintenance functions provided, including boundary scan, PRBS generator/analyzer loopbacks.
APPLICATIONS
SONET/SDH terminal add/drop multiplexers supporting both asynchronous byte-synchronous modes Unidirectional bidirectional ring applications SONET remote digital terminal equipment SONET equipment requiring access DS0s SONET/SDH test equipment Internet access equipment
SYSTEM SIDE
Line Transceiver Common Control Interface +3.3V
LINE SIDE
Dual Rail/ Data Clocks
T1Mx28
Telecom Interface Drop Microprocessor Interface
Mapper 28-Channel TXC-04228
Line Transceiver Alarm/Select Interface
Test Access Port Interface System Boundary Scan Clocks
U.S. Patents 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218 U.S. and/or foreign patents issued pending Copyright 2001 TranSwitch Corporation T1Mx28 trademark TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
Document Number: PRELIMINARY TXC-04228-MB April 2001
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
PRELIMINARY information documents contain information products sampling, pre-production early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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T1Mx28 TXC-04228
DATA SHEET TABLE CONTENTS
Section
Page
List Figures Features Features That Independently Selectable each Mappers Features that only Selectable Twenty-Eight Mappers Group Block Diagram Block Diagram Description Lead Diagram. Lead Descriptions. Absolute Maximum Ratings Environmental Limitations Thermal Characteristics Power Requirements. Input, Output Input/Output Parameters Timing Characteristics. Operation. General Mapper Application Overview. Line Interface Selection. Asynchronous Operation with Line Interface Byte-Synchronous Operation with Line Interface. Receive Data Signaling Highway Operation Transmit Data Signaling Highway Operation Synchronizer, Mapper Overhead Generator. Pointer Generation Telecom Slot Selection. VT/TU Pointer Tracking Telecom Slot Selection Demapper Desynchronization Pointer Leak Rate Calculations Jitter Measurements. Microprocessor Interface Common Control/Status Serial Port Control Interface. T1Mx28 Channel Testing using PRBS Generator Analyzer Telecom Interface Multiplex Format Mapping Information. Internal Ring Port Test Access Port Boundary Scan Support. Device Reset Procedure Memory Memory Descriptions. Common Memory Map. Channel Control Registers Channel Status Registers. Application Diagrams Package Information Ordering Information Related Products. Standards Documentation Sources. List Data Sheet Changes Documentation Update Registration Form*. Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
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DATA SHEET LIST FIGURES
Figure
T1Mx28 TXC-04228
Page
T1Mx28 TXC-04228 Block Diagram VT1.5/TU-11 Asynchronous Byte-Synchronous Mappings. T1Mx28 TXC-04228 Lead Diagram Tributary Input Timing Tributary Output Timing Signaling Highway Structure Serial Control Port Structure Timing Telecom Input Timing 6.48 Operation Telecom Input Timing 19.44 Operation Telecom Output Timing 6.48 Operation Telecom Output Timing 19.44 Operation Datacom Mode Output Timing Datacom Mode Input Timing Intel Microprocessor Read Cycle Timing Motorola Microprocessor Read Cycle Timing Intel Microprocessor Write Cycle Timing Motorola Microprocessor Write Cycle Timing Boundary Scan Timing. Line Interface Dual Unipolar Mode Line Interface Mode. Byte-Synchronous Interface Framer System Interface Receive Framing Format. System Interface Receive Signaling Format System Interface Transmit Framing Format. System Interface Transmit Signaling Format VT/TU Pointer Tracking State Machine. Pointer Leak Rate Algorithm Jitter Tolerance Test Setup Jitter Tolerance Measurements. Jitter Transfer Test Setup. Jitter Transfer Measurements Jitter Generation Test Setup Standard Pointer Test Sequences Shadow Register Operation Serial Interface Operation Loopbacks Built-in PRBS Testing T1Mx28 Telecom Structure; SONET VC-3 SDH; Telecom 6.48 Telecom Structure; TUG-3 SDH; Telecom 19.44 STS-1 Mapping STS-3/AU-3 Mapping STM-1/VC-4 Mapping Internal Ring Port Operation Boundary Scan Schematic. Typical Applications using T1Mx28. T1Mx28 TXC-04228 456-Lead Plastic Ball Grid Array Package.
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T1Mx28 TXC-04228 FEATURES
DATA SHEET
following features supported T1Mx28: T1Mx28 device highly-featured twenty-eight-channel (T1) mapper wide variety interface, transmission switching applications. Twenty-eight independent asynchronous/byte-synchronous mappers provided VLSI device using sub-micron CMOS technology. Powered from single +3.3 volt supply, device dissipates less than watts typically. T1Mx28 provided 456-lead plastic ball grid array package mm). ambient operating temperature range extends from with ft/min airflow. T1Mx28 device been designed meet latest industry standards, namely: ANSI T1.102- 1993 ANSI T1.105- 1991 ANSI T1.107- 1995 ANSI T1.231 1997 ANSI T1.403-1998 AT&T Pub. 62411 (December 1990) Bellcore GR-253-CORE (Issue Bellcore TR-NWT-000496 (Issue Bellcore GR-499-CORE (Issue IEEE 1149.1- 1990, -1994 G.707 3-96 G.783
FEATURES THAT INDEPENDENTLY SELECTABLE EACH MAPPERS Line Interface Options Meets ANSI Bellcore input jitter requirements Rail (for asynchronous mapping only) B8ZS ANSI compliant detector ANSI compliant detector 12-bit counters with excessive zeros option option (for asynchronous byte-synchronous mapping) Clock polarity selection clock in/out data inversion clock edge options (separate transmit receive control) asynchronous use, negative rail used count externally detected code violations Programmable clock edges transmit receive data External lead channel status (may programmed combine with internal support external detector) Clock slave asynchronous input; clock multiframe synchronization ms), master slave, byte-synchronous input Separate signaling highway byte-synchronous, carries ABCD signaling bits AIS/ Yellow alarm information T1Mx28 (see TXC-03108, 8-Channel Framer)
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DATA SHEET
T1Mx28 TXC-04228
External lead-controlled shut down Telecom line drive leads card protection Gapped clock option place signaling 1536 datacom byte-synchronous operation CRC-6 generation (DS1 input) error counting (DS1 output) byte-synchronous mapping Mapping Synchronizer Features Mapping SONET columns according GR-253-CORE G.709 channel selectable asynchronous byte-synchronous mapping floating VT1.5 TU-11 both mapping demapping Overhead assembly with BIP-2 calculation, REI-FEBE (microprocessor received BIP-2 error), signal label (microprocessor value), (microprocessor value received signal label mismatch, AIS, LOP, unequipped) (microprocessor value Yellow from signaling highway) Pointer calculation (fixed asynchronous, calculated byte-synchronous mode) with generated pointer increment decrement counters bits each) byte-synchronous mode, line clock input ('modified byte-synchronous mode') output ('true byte-synchronous mode') Multiplexing signaling bits from signaling highway with P0/P1 generation Unequipped unassigned payload generation generation (microprocessor value, from signaling highway, loss frame bytesynchronous, AIS/LOS/external lead from line decoder) Threshold modulator reduce demapping jitter wander Tracking input multiframe pulses pointer movements byte-synchronous mode Demapping Desynchronizer Features Asynchronous byte-synchronous channel, programmable match mapper mode Digital with pass filter track nominal signal providing smooth clock output with need external de-jitter buffer Separate byte pointer leak buffer with programmable dual slope leak rate 2048 steps, automatically doubled 4096 steps within bits center pointer leak buffer); meets Bellcore MTIE with minimal software support Power down with all-zeros all-ones sent line interface Demapping SONET columns according GR-253-CORE G.709 Asynchronous byte-synchronous demapping floating VT1.5/TU-11 Pointer tracking extraction overhead Z7/K4), AIS, with received pointer increment decrement counters bits each) Overhead processing with BIP-2 calculation error counting (12-bit, with overflow), (FEBE) counting (12-bit, with overflow), 3-bit)/RFI signal label debouncing detection, signal label mismatch/unequipped detection Demultiplexing signaling bits signaling highway with multiframe generation bytesynchronous from microprocessor value, AIS, signal label mismatch unequipped (Yellow) signaling highway from
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T1Mx28 TXC-04228
DATA SHEET
Fractional Frame Relay, AAAL1 Access Framer required many applications Receive transmit gapped clock (1536 kbit/s) mapper byte-synchronous mode CRC-6 generation checking Direct connection multichannel HDLC Adevices kbit/s service Internal DPLL minimize received jitter Signaling Support Byte-Synchronous Mapping Receive transmit temporary buffers align VT1.5/TU-11 payloads signaling highway Signaling bits mapped demapped from specific locations GR-253-CORE G.709 ABCD signaling support Byte-synchronous operation with TranSwitch T1Fx8 VLSI device: Signaling positions received DS0s optionally replaced with ones T1Fx8 (Yellow) respectively (Yellow) respectively Unicode support (DS0 alarms) byte-synchronous operation supported T1Fx8 Alarms Errors Detection AIS, RFI, unequipped, signal label mismatch, loss pointer, single-bit RDI, 3-bit RDI, demap error demap direction Detection AIS, loss signal, error, external lead alarm, mapping direction Counting code violations (with without excessive zeros) CRC-6 errors, BIP-2, (FEBE), pointer generation receive pointers with presets overflow indications Microprocessor enable insert alarms detected from line, calculated, overhead Maintenance Loopbacks line remote (toward line), line local (toward Telecom Bus), Telecom (toward line groups seven channels once) PBRS generator with 215-1 pattern transmit framer analyzer receive path assignable channel Separate control bits with software indication Power-down modes force transmit leads low, high tristate
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DATA SHEET
Microprocessor Interface
T1Mx28 TXC-04228
Nineteen-bit status register AIS, RFI, unequipped, signal label mismatch, loss pointer, single-bit RDI, 3-bit RDI, AIS, loss signal, error, demap error, external lead alarm, counter overflow bits code violation/CRC-6, BIP-2, (FEBE), pointer generation receive pointers Latched event registers interrupt mask registers individually control each condition Twelve-bit CRC-6 (byte-synchronous)/code violation (asynchronous), BIP-2, (FEBE) error counters Four-bit increment decrement pointer generation receive pointer counters Shadow registers counters Full control alarm mapping through enable bits Microprocessor forcing alarm conditions channel reset resynchronization Register access Z6/N2, Z7/K4 bytes O-bits read write Performance Fault Monitoring second basis, backplane second clock Shadow registers alarms counters Separate registers indicate alarm changes (performance) hard conditions (faults) updated every second simplify performance report generation
FEATURES THAT ONLY SELECTABLE TWENTY-EIGHT MAPPERS GROUP Telecom Interface Dual drop with individual timing Each connected mappers Paralleled operation mappers multiplexed mapper pair 14-channel dual applications Operation 6.48 Mbyte/s 19.44 Mbyte/s Compatible with TranSwitch PHAST-1, PHAST-3N, SOT-1E SOT-3 devices Parity generation detection with device alarm (odd even) data SPE/C1J1V1 SONET mapping VT1.5 6.48 19.44 Mbyte/s mappings TU-11 AU-3 19.44 Mbyte/s Uses C1J1V1 locate individual Separate STS-1 phases permitted STS-3 asynchronous modified bytesynchronous operation Each transmit receive time slot programmable including internal external contention monitors with global alarm timing programmable zero clock delay Drop clock edges programmable enable lead plus control leads optional and/or drive VT/TU signal failure input common lead Telecom Clock SPE/C1J1V1 presence detectors system system buses Telecom Bus, which generate device alarms failure PRELIMINARY TXC-04228-MB
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T1Mx28 TXC-04228
DATA SHEET
External Line Interface Transceiver Support Four groups three-wire serial port read/write control seven line interface transceivers ('host mode') each group Designed support integrated microprocessor control loopbacks, alarms line build channel broadcast data each group seven line interface transceivers Internal registers drive read external devices Common Microprocessor Support Microprocessor global reset, masks, polling registers, interrupt polarity latch edge control Motorola split address/data Intel split address/data Global alarm Indications group seven mappers ('or' channel alarms same type) with channel pointer register indicating channels with active alarms Global (per group seven mappers) interrupt mask bits, alarm type Interrupt alarm changes: positive edge, negative edge both edges interrupt line group seven mappers Device level alarms Telecom signals reference clocks using status latched event registers with interrupt mask registers Device level alarms enabled appear separate interrupt line Telecom card protection hardware software mechanisms Error insertion microprocessor parity testing Telecom Timed error insertion (FEBE) BIP-2 global value Hardware interrupt polarity selection Common hardware reset lead global (per group seven mappers) software reset register Protection, Test Maintenance Support IEEE 1149.1 boundary scan five lead interface Ability tristate outputs in-circuit testing with single control lead group seven mappers Loss clock detectors parity generator/error detector drop Telecom Buses Internal alarm output programmable variety fault clock fault conditions card switch-off feature assist implementing protection switching External shadow register clock input (1Hz ppm) PRBS generator analyzer group seven mappers switchable seven mapper channels group
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DATA SHEET BLOCK DIAGRAM
SRCLK From PRBS
T1Mx28 TXC-04228
Ring Port
CONFIGI AAPAR AAADD(1-2) AACLK AAC1J1V1 AASPE AAD(0-7) ADATEN ABUSCHK(1-4) ADCLK ADC1J1V1 ADSPE ADD(0-7) ADFAIL MASTERA ADPAR
DATA
TELECOM SIDE DATA DATA Synchronizer/ Inc./Dec. alarms Mapper PRBS Decoder Trib. LPBK ABCD, SLOT TIMING CLK,SPE, C1J1V1 Termination block TRIBUTARY SIDE CLK,MF Input Timing
LRCLKn RSYNCn
Telecom Interface Channel blocks #1-14
RPOSn RNEGn/ RSIGLn/ RCVn/ RGCOn
AIS,
Signaling Store
Alarm
Alarm Control
Control Facility Loopback ALO, SRCLK AIS,YEL (FEBE) CLK,MF Output Timing
LAISn
LTCLKn TSYNCn
CONFIGI BAPAR BAADD(1-2) BACLK BAC1J1V1 BASPE BAD(0-7) BDATEN BBUSCHK(1-4) BDCLK BDC1J1V1 BDSPE BDD(0-7) BDFAIL MASTERB BDPAR Telecom Interface Channel blocks #15-28
Mapper Timing
SLOT TIMING
Desynchronizer/ Demapper
TPOSn TNEGn/ TSIGLn/ TGCOn BCSO
C1J1V1, CLK,SPE
DATA ABCD,
Coder
Signaling
Store
ACSO
Alarm
Channel block
AIS,
Control
marks eight parts Line Interface block.
BIAO AIAO HIGHZp TSTAp TSTBp Test Access Port Interface (Boundary Scan)
Note: n=1-28 (Channel blocks)
LCSn
Mapper Timing
Microprocessor Interface Common Control/Status
PRBS1 Gen. Anal.
RSTI Serial RDYO/ SELIp INTOp/ Port (0-7) DTACKO IRQOp Control READI/ T1SI MOTOI ADDR PCKI Interface (0-8) READI/WRI LSCLKp LSDOp LSDIp
Note: p=1-4 (for four groups seven mappers)
SYSTEM SIDE
LINE SIDE
Figure T1Mx28 TXC-04228 Block Diagram
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T1Mx28 TXC-04228
DATA SHEET
BLOCK DIAGRAM simplified block diagram T1Mx28 device shown Figure major blocks twenty-eight Channel blocks, Microprocessor Interfaces, Serial Port Control Interfaces, Ring Ports, PRBS (Pseudo-Random Binary Sequence) Generators Analyzers, Test Access Port Interfaces, Mapper Timing blocks Telecom Interfaces 14-channel mapper groups. Each twenty-eight Channel blocks consists following component blocks: Decoder/Coder Input/ Output Timing (for Receive Transmit Line Interfaces), Receive Transmit Alarm Control, Receive Transmit Signaling Store, Synchronizer/Mapper Desynchronizer/Demapper, Termination, Telecom Input Output Control blocks. Receive Transmit Line Interface blocks connect each twenty-eight mapper channels external line interface transceiver, which performs clock recovery functions asynchronous mode operation. interface transceiver configured interface modes: dual unipolar (rail) interface interface. When byte-synchronous mode operation used, clock synchronization signals from external framer handled these blocks; data then always mode.These blocks also provide tributary (transmit receive) loopback facility remote (receive line transmit line) loopback. When dual unipolar interface mode selected, input data from external line interface transceiver clocked into T1Mx28 leads RPOSn RNEGn using recovered receive clock present LRCLKn input leads, where n=1-28 identifies twenty-eight mappers (note: RNEGn several leads that multiple functions, with signal symbol each). transmit direction, unipolar data clocked T1Mx28 leads TPOSn TNEGn transmit line clock present LTCLKn output leads. Global control bits each group seven mappers (i.e., channels 1-7, 8-14, 15-21, 22-28) provided memory which enable unipolar data clocked T1Mx28 either edge clocks. dual unipolar interface mode, T1Mx28 provides either Bipolar with Eight Zero Substitution (B8ZS) Alternate Mark Inversion (AMI), coder decoder function, Loss Signal detection. Loss Signal detector meets requirements specified ANSI T1.231 document listed above T1Mx28 Features section. unframed detector also provided assist network fault isolation. 12-bit performance counter provided each mapper, counting B8ZS coding violation errors. option provided also include excessive zeros coding violations counter. When interface mode selected mapper channel programmed asynchronous mapping, data clocked RPOSn lead recovered received clock input LRCLKn lead. data clocked T1Mx28 TPOSn leads transmit system clock present LTCLKn leads. Global control bits provided memory each group seven mappers which enable data inverted clocked T1Mx28 either edge clocks. Bipolar violations which detected external line interface transceiver clocked into T1Mx28 RNEGn/RCVn leads counted associated 12-bit coding violation performance counter. TNEGn output used mode spare drive applications such dual operation single LIU. Remote Line Loopback function each framer also implemented Line Interface blocks. When interface mode selected mapper channel programmed byte-synchronous mapping, data clocked RPOSn leads clock present leads LRCLKn. T1Mx28 generate clock LRCLKn multiframe synchronization signal leads RSYNCn external slip buffer provided framer source signal clock slaved T1Mx28. LRCLKn RSYNCn inputs, T1Mx28 translates clock phase movements with respect SONET/SDH clock VT/TU pointer movements. applications that require framer where CRC-6 performance monitoring function desired (where T1Mx28 clock master), T1Mx28 calculates inserts CRC-6 into defined frame positions VT1.5/TU-11 structure mapping direction. After demapping, CRC-6 checked errors found counted 12-bit counter shared code violation counting.
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DATA SHEET
T1Mx28 TXC-04228
Byte-synchronous mapping supports independent transmission signaling through defined nibbles VT1.5/TU-11 structure, shown Figure T1Mx28 provides Receive Transmit Signaling Stores synchronize signaling framing bits from Framer switching stage with Mapper Demapper blocks. Signaling received through RNEGn/RSIGLn leads byte-synchronous mode, being clocked with LRCLKn. Signaling sent TNEGn/TSIGLn leads byte-synchronous mode, using LTCLKn. TranSwitch framers like T1Fx8 (TXC-03108) utilize signaling bits signaling highways automatic signaling propagation between SONET/SDH byte-synchronous mapping lines. applications using full payload byte-synchronous mode, RNEGn/RSIGLn leads programmed supply gapped clock (RGCOn), TNEGn/TSIGLn leads (TGCOn). Receive Transmit Alarm Control blocks work conjunction with Decoder/Coder Input/Output Timing blocks well Receive Transmit Signaling Store blocks move alarm signals T1Mx28. Receive Alarm Control block detects specific bits from receive signaling highway, such (Yellow), forwarding Synchronizer/Mapper block RFI. also gathers from Receive Line Interface. LAISn input lead used forwarding externally detected Loss Signal Loss Clock, general interrupt input. Transmit Alarm Control block translates from Desynchronizer/Demapper block along with microprocessor controls specific bits transmit signaling highway. TranSwitch framers like T1Fx8 (TXC-03108) utilize control bits signaling highways automatic alarm propagation between SONET/SDH lines. card protection schemes, control input leads ACSO(BCSO), when driven low, cause output leads fourteen Line Interfaces associated with Telecom low. Synchronizer/Mapper block takes clock data from Receive Line Interface asynchronous mode, threshold modulates with SRCLK, buffers FIFO, inserts data bits information positions asynchronous VT1.5/TU-11, stuffs using stuff opportunity bits with indication bits, shown Figure stuffing matches received clock positions available based SONET/SDH network clock supplied T1Mx28 Telecom Clocks, AACLK BACLK, AAC1J1V1 BAC1J1V1 signals. Optional overhead bytes Z6/N2, part taken from microprocessor-written values. Synchronizer/Mapper block takes clock, frame data from Receive Line Interface byte-synchronous mode, buffers FIFO writes defined byte positions byte-synchronous VT1.5/TU11 along with optional overhead bytes Z6/N2 part which taken from microprocessor-written values. byte-synchronous mode signaling bits taken from Receive Signaling Store mapped correct positions VT1.5/TU-11. 500-microsecond long superframe shown Figure repeated times, being synchronized RSYNCn millisecond input. P1P0 bits generated indicate which signaling framing bits being carried specific superframe related RSYNCn. FIFO conditions monitored lead increment decrement requests Termination block. Synchronization changes RSYNCn monitored possible requests. Termination block takes mapped data optional overhead together with frame, increment decrement indications associated with byte-synchronous mode from Synchronizer/Mapper block. bytes built from several received alarms sources (the received alarms, Ring Port error conditions, microprocessor-written values). Parity then calculated over payload. positioning just after asynchronous mode only. byte-synchronous mode (true byte-synchronous modified byte-synchronous), bytes generated track phase incoming signals relative AACLK BACLK; four-bit counters provided keep track pointer increments pointer decrements generated. position RSYNCn pulse generated, this block will generate along with pointer. T1Mx28 acts clock source, lead will used provide this clock must frequency locked STS-1 STM-1 clock, pointer justifications and/or mapping errors will result. generated entire payload ones. unassigned (Idle) generated, all-zeros payload with valid generated. unequipped generated, allzeros payload including generated.
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DATA SHEET
termination block also provides pointer tracking, overhead location VT1.5/TU-11 alarm detection debouncing functions. alarms (RDI four flavors, RFI, Unequipped, Signal Label Mismatch, LOP, AIS, REI, BIP-2 errors, etc.) made available common microprocessor block latching, shadowing, counting interrupting purposes. Alarms provided Ring Port support ring applications. When T1Mx28 used dual mapper, ring port pairs mapper with mapper mapper with mapper etc. example, transmit alarms mapper come from mapper rather than from mapper receive path. also identifies payload Desynchronizer/Demapper block well pointer movements. Desynchronizer/Demapper block takes data alarm information, along with pointer information, extracts signal. This block extracts optional overhead bytes sends Z6/N2 Z7/K4 Transmit Signaling Store. both modes data sent pointer leak buffer which programmable leak rate. This used minimize jitter wander asynchronously mapped signals well smooth byte-synchronously mapped signals that utilize pointer movements frequency adjustment. pointer leak rate adjusted meet MTIE requirements with simple software algorithm which uses second latched pointer increment decrement counters. Desynchronizer uses DPLL operated from signal SRCLK (48.636 MHz) that smooths stuffing jitter compensates demapping gapped positions used orders overhead. Desynchronizer outputs clock along with data Transmit Line Interface block ready transmission framing without additional de-jittering. byte-synchronous mode Frame pulse (3.0 decoded from P1P0 bits used align signaling highway Transmit Signaling Store, becomes signal TSYNCn. correct P1P0 pattern must supplied proper operation even signaling used. Alarm information (RFI AIS) sent Transmit Alarm block forwarding signaling highway. used cause DPLL output in-frequency-range all-ones signal. Telecom Output Input Control blocks buffer assembled VT1.5/TU-11 bytes insertion extraction from Telecom Interface. Each twenty-eight mapper channels independently placed independently taken from three STS-1s TUG-3s (19.44 Telecom only), seven groups TUG-2s, four VT1.5 TU-11s. Enable control bits allow channel disconnected transmit and/or receive from Telecom Bus. Telecom Interface blocks combine signals from twenty-eight mapper channels synchronize them half Telecom based AACLK, BACLK, AAC1J1V1, BAC1J1V1, AASPE BASPE signals. Mappers through tied mappers through tied Bus. Each configured single STS-1 (6.48 MHz), STS-3 (19.44 MHz) STM-1 (19.44 MHz). Contention checks made twenty-eight mapper channels; this feature extended using ABUSCHK(1-4) BBUSCHK(1-4) leads additional T1Mx28 devices sharing Bus. Parity (leads AAPAR BAPAR) indication (leads AAADD(1-2) BAADD(1-2)) included with byte-wide data (leads AAD(0-7) BAD(0-7)). ADATEN, BDATEN, MASTERA MASTERB leads allow optional drive overhead stuff columns, when data delay option used. Drop part Telecom provides ADCLK, BDCLK, ADC1J1V1(BDC1J1V1), ADSPE(BDSPE) signals along with failure indication (leads ADFAIL BDFAIL) indicate twenty-eight mapper channels that received data errored higher order path, section line failures. Parity (leads ADPAR BDPAR) included with data (leads ADD(0-7) BDD(0-7)). Parity covers drop data optionally C1J1V1 signals. signals monitored failure maskable interrupts generated both microprocessor interrupt lead separate failure leads AIAO(BIAO). 28-channel single application leads connected leads.
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DATA SHEET
T1Mx28 TXC-04228
Byte-Synchronous Floating Mode Channels Channels Channels Channels
Legend: Stuff Control Frame Information Path Trace
Asynchronous Floating Mode Information Bytes
Overhead Bits P1P0 Signaling Phase Fixed Stuff Signaling
Information Bytes
Stuff Opportunity pointer Inc/Dec opportunity
Information Bytes
unused Overhead Reserved Byte Reserved 3-bit Byte
Information Bytes
Byte Data Flag Size
Byte
Pointer Range decimal
normal shown (new data flag 1001); S1S2 Positive Justification Invert I-bits; Negative Justification Invert D-bits; shown (bit first.
BIP-2 Byte REI-V RFI-V Signal Label RDI-V
Shown (bit first. REI-V also known FEBE. RDI-V Unequipped, AIS-V LOP-V.
Byte 3-bit RDI-V
3-bit RDI-V Codes: defects; Signal label mismatch; AIS-V LOP-V; Unequipped. Figure VT1.5/TU-11 Asynchronous Byte-Synchronous Mappings
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T1Mx28 TXC-04228
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T1Mx28 four PRBS Generator Analyzer blocks. Each Generator Analyzer supports 215-1 pattern. Generator output substituted place data stream output from each Receive Line Interface Decoder. Analyzer monitors data stream outputs from four groups seven Receive Line Interface Decoders. setting Telecom Loopback function Telecom Interface block) Tributary Loopback twenty-eight channels, entire channel's transmit receive path verified (Synchronizer/Mapper, Termination, Telecom Interface, Desynchronizer/ Demapper, Transmit Line Interface Receive Line Interface). moving loopbacks framers, LIUs, switches remote mappers entire path verified. Serial Port Control Interface blocks provide communicating with external line interface transceivers that support 'Host Mode' operation. This allows system microprocessor control transceiver through T1Mx28. interface consists four sets data output leads (LSDOp), clock output leads (LSCLKp), data input leads (LSDIp), each shared among group seven mappers. Each transceiver selected T1Mx28, using chip select output signals (LCSn). addition, general purpose input lead (LAISn) used mode generate maskable interrupt. Test Access Port block common twenty-eight mapper channels includes five-lead Test Access Port (TAP) that conforms IEEE 1149.1 standard. This block provides external boundary scan read write T1Mx28 input output leads from board component testing. nonboundary scan testing HIGHZp leads provided tristate output leads. T1Mx28 configured operate with either Intel Motorola-compatible microprocessors Microprocessor Input/Output Interface block. Separate address, data control leads provided. microprocessor access four separate 512-byte segments memory which have individual select interrupt leads, corresponding four groups seven mappers. Interrupt capability provided with mapper group individual mapper mask bits well activity registers guide software exact cause interrupt most expeditious manner. wide variety alarms provided mapper group level well mapper channel level. Each alarm error reflected current status register counter well latched value register that rising, falling both edges alarm. Shadow registers alarms counters provided, with alarm shadow registers doubled indicate either change (performance item) persistent condition (fault). latched value trigger interrupt, unless masked prevent causing interrupt. option provided which permits interrupt polarity inverted. external system clock provided lead PCKI used internal state machines.
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DATA SHEET LEAD DIAGRAM
T1Mx28 TXC-04228
Note: This bottom view. leads solder balls.Refer lead descriptions section below lead assignment. Figure package information.
Figure T1Mx28 TXC-04228 Lead Diagram
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T1Mx28 TXC-04228 LEAD DESCRIPTIONS
POWER SUPPLY GROUND Symbol Lead
DATA SHEET
I/O/P*
Type
Name/Function VDD: +3.3 volt supply,
L12, L13, L14, L15, M11, M16, N11, N16, P11, P16, R11, R16, T12, T13, T14, T15, A26, L11, L16, M12, M13, M14, M15, N12, N13, N14, N15, P12, P13, P14, P15, R12, R13, R14, R15, T11, T16, AF1, AF26 AB21
GND: Ground
Connected. Leave floating. make external connections this lead. Connection impair performance cause damage device.
*Note: Input; Output; Power
CHANNEL TRIBUTARY 28); group select Symbol LRCLKn Lead D23, C21, C19, D17, C16, E14, D12, AB5, AD6, AC8, AC10, AD12, AB14, AB11, AD24, AA23, AB19, U24, T24, R22, C23, E20, D19, C17, C15, E15, E17, AD4, AC5, AB9, AD9, AD13, AB13, AB7, AB24, AB20, AA22, W23, P24, P22, I/O/P Type Name/Function**
CMOS Line Receive Clock Input: 1.544 clock from DSX-1 receiver asynchronous mapping mode; (tolerance ANSI Bellcore byte-synchronous operation). Global control RCAEp (bit register 007H determines active edge this clock. Input jitter tolerance peak peak from peak peak from kHz. Bellcore TR-TSY-000499. byte-synchronous operation with external slip buffer which control bits MODE1 MODE0 (bits register X+00H LRCLKn output derived from leads (for (for CMOS Receive Frame Sync.: millisecond multi-frame sync from framer, framer byte-synchronous mode. Sampled LRCLKn falling edge global control RCAEp (bit register 007H byte-synchronous operation with external slip buffer which control bits MODE1 MODE0 (bits register X+00H RSYNCn output derived from leads (for (for
RSYNCn
*Note: Input, Output Input/Output Parameters section below Type definitions. **Note: References global control bits group seven channels. These groups selected lead SELIp Individual channel control bits selected both lead SELIp address offset "X".
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DATA SHEET
Symbol RPOSn Lead D24, C22, D20, E18, E16, D14, B11, AA4, AC4, AC7, AB10, AD10, AD14, AB12, AD23, AB22, Y22, V24, P25, N23, C24, D21, C20, D18, D15, C13, D13, AC3, AD5, AD7, AC9, AB8, AC14, AC11, AC24, AA24, Y23, W24, R25, N22, I/O/P Type Name/Function**
T1Mx28 TXC-04228
CMOS Tributary Receive Data (Positive): NRZ/Positive rail. data from framer DSX-1 Receiver. RPOSn sampled LRCLKn falling edge global control RCAEp (bit register 007H mode, global control RXNRZPp (bit register selects polarity selects logical one).
RNEGn/
CMOS Tributary Receive Data (Negative): Negative rail data from DSX-1 receiver. This lead sampled LRCLKn falling edge global control RCAEp (bit register 007H Receive Signaling Highway Input: Signaling Highway from framer. Sampled LRCLKn falling edge global control RCAEp (bit register 007H Tributary Receive Code Violations: Code violation counter input. Sampled LRCLKn falling edge global control RCAEp (bit register 007H Receive Gapped Clock Output: When datacom mode selected (only available byte-synchronous operation) control DATACOM (bit channel register X+00H being this lead provides gapped clock output which appears Frame times RPOSn.
RSIGLn/
RCVn
RGCOn
LAISn
E23, D22, E19, C18, D16, C14, C12, AB4, AD3, AC6, AD8, AD11, AC13, AC12, AC23, AB23, Y24, W22, U22, P23,
CMOS Line Alarm Input: Line transceiver interrupt, Loss Signal/Clock from DSX-1 receiver.The active level determined global control RXNRZPp (bit register 007, which selects polarity selects logical one). channel control EXPLOS (bit register X+00H enables this lead Control LOS2AIS (bit register X+01H, when causes this signal propagate upstream. When EXPLOS status (bit register X+10H becomes separate status indication with latched, mask, performance fault registers plus global mask status capability.
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T1Mx28 TXC-04228
Symbol LTCLKn Lead B26, B23, A21, B18, A16, B13, B10, AC1, AF2, AE5, AF7, AF10, AF12, AE15, AF24, AD26, AA26, Y26, T25, K26, C26, B24, A22, B19, A17, B14, A12, AB1, AE2, AE4, AF6, AF9, AE9, AE14, AF23, AE26, AB25, W25, U25, R26, C25, A24, B21, A19, B16, A14, A11, AC2, AE1, AF4, AE7, AE10, AE12, AF14, AE24, AD25, AB26, W26, U26, N25, I/O/P
DATA SHEET
Type Name/Function**
CMOS Line Transmit Clock Output: 1.544 clock DSX-1 line driver framer. Global control TCAEp (bit register 007H determines active edge this clock. Also ACSO (for BCSO (for below. output frequency tracks input frequency defined synchronized payload. Output jitter caused de-synchronization single pointer movements less peak peak above (0.075 peak peak less from kHz).
TPOSn
CMOS Tributary Transmit Data (Positive): NRZ/Positive data DSX-1 line driver framer. Output LTCLKn rising edge global control TCAEp (bit register 007H mode, global control TXNRZPp (bit register 007H selects polarity selects logical one). Also ACSO (for BCSO (for below.
TNEGn/
CMOS Tributary Transmit Data (Negative): Negative rail data DSX-1 line driver output LTCLKn rising edge global control TCAEp (bit register 007H When mode used asynchronous mode this lead used spare output (e.g., select B8ZS/AMI line transceiver). Also ACSO (for BCSO (for below. Transmit Signaling Highway Output: Signaling highway framer. Output LTCLKn rising edge global control TCAEp (bit register 007H Also ACSO (for BCSO (for below. Transmit Gapped Clock Output: When Datacom mode selected (only available byte-synchronous operation) control DATACOM (bit channel register X+00H being this lead provides gapped clock output which appears frame times TPOSn.
TSIGLn
TGCOn
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DATA SHEET
Symbol TSYNCn Lead AA2, B25, A23, B20, A18, B15, A13, A10, AD2, AE3, AF5, AE8, AE11, AE13, AF15, AE25, AC25, Y25, V25, T26, J25, A25, B22, A20, B17, A15, B12, AD1, AF3, AE6, AF8, AF11, AF13, AF16, AF25, AC26, AA25, V26, R23, K25, I/O/P Type Name/Function**
T1Mx28 TXC-04228
CMOS Transmit Frame Sync: millisecond multi-frame sync framer. Output LTCLKn rising edge global control TCAEp (bit register 007H Also ACSO (for BCSO (for below.
LCSn
CMOS Line Interface Transceiver Chip Select: active signal that enables communications both directions between external line interface transceiver channel T1Mx28. This lead under control global register 01AH where ENSRPp (bit enables transmission channel which selected BDCSTp (bit select channels channel selection controls (bits 2-0) which select channels.
TRIBUTARY COMMON CONTROL Symbol Lead I/O/P Type CMOS Name/Function Local Oscillator: 1.544 system clock input used byte-synchronous mode. 1.544 synchronized system (AASPE, AACLK specific AAC1J1V1) byte-synchronous operation where LRCLK(1-14) RSYNC(1-14) outputs. This signal also used generate serial port clock output LSCLKp (for Local Oscillator: 1.544 system clock input used byte-synchronous mode. 1.544 synchronized system (BASPE, BACLK specific BAC1J1V1) byte-synchronous operation where LRCLK(15-28) RSYNC(15-28) outputs. This signal also used generate serial port clock output LSCLKp (for System Reference Clock: 48.636 (31.5 times 1.544 MHz) system clock input used operate synchronizer, desynchronizer, PRBS generator/analyzer, generate twenty-eight channels.
AC22
CMOS
SRCLK
CMOS
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T1Mx28 TXC-04228
DATA SHEET
Symbol LSDOp
Lead E26, AA1, AF22
I/O/P
Type CMOS
Name/Function Line Interface Transceiver Data Output Signal: Common serial control data output shared group seven channels. command byte followed data byte, stored control registers 017H 018H respectively, transmitted line interface transceiver selected LCSn. Line Interface Transceiver Data Input Signal: Common serial control data input shared group seven channels. data byte coincident with data byte LSDOp clocked into T1Mx28 stored register 019H from line interface transceiver selected LCSn. Line Interface Transceiver Clock Signal: Common serial control clock output shared group seven channels. 1.544 clock derived from (for (for LSDOp clocked T1Mx28 falling edge LSCLKp LSDIp clocked into T1Mx28 rising edge LSCLKp. Second Performance Clock Input: Shadow register latch. This input which common twenty-eight channels, operates latched counters PM/FM registers. following parameter value limits suggested prevent counters from overflowing when operating noisy environments other unfavorable conditions: min. high time 0.50 min. time max. time Operation ppm, high time, recommended. This clock used conjunction with global control ENPMFMp (bit register 006H clear channel event registers (not device event registers) after registers have been updated.
LSDIp
E25, AC21
CMOS
LSCLKp
D25, AB2, AE23
CMOS
T1SI
AIAO
AB18
CMOS open Internal Alarm Output: Internal Alarm detected, active drain output. Control bits registers 01BH 01CH (for enable Side Telecom clock, payload synchronous failures, well parity errors PRBS lock, generate alarm interrupt this lead. CMOS open Internal Alarm Output: Internal Alarm detected, active drain (4mA) output. Control bits registers 01BH 01CH (for enable Side Telecom clock, payload synchronous failures, well parity errors PRBS lock, generate alarm interrupt this lead. Card Switch Off: When driven low, LTCLK(1-14), TPOS(1-14), TNEG(1-14)/TSIGL(1-14) TSYNC(1-14) driven logic level.
BIAO
ACSO
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DATA SHEET
Symbol BCSO Lead I/O/P Type Name/Function
T1Mx28 TXC-04228
Card Switch Off: When driven low, LTCLK(15-28), TPOS(15-28), TNEG(15-28)/TSIGL(15-28) TSYNC(15-28) driven logic level.
SYSTEM INTERFACE Symbol ADCLK Lead I/O/P Type Name/Function Drop Clock: Telecom clock data from system; 6.48 lead CONFIGI tied high 19.44 lead CONFIGI tied low. Control TBRCIp (bit registers 01EH (for selects rising edge ADCLK active edge. Control bits must same value both proper operation. Drop Clock: Telecom clock data from system; 6.48 lead CONFIGI tied high 19.44 lead CONFIGI tied low. Control TBRCIp (bit registers 01EH (for selects rising edge BDCLK active edge. Control bits must same value both proper operation. Drop C1J1V1 Indicator: Telecom C1#1, J1#1, V1#1 valid from system. Valid rising edge ADCLK when control TBRCIp (bit registers 01EH (for Used with ADSPE identify start payload. Control bits must same value both proper operation. Drop C1J1V1 Indicator: Telecom C1#1, J1#1, V1#1 valid from system. Valid rising edge BDCLK when control TBRCIp (bit registers 01EH (for Used with BDSPE identify start payload. Control bits must same value both proper operation. Drop Indicator: Telecom valid from system. Valid rising edge ADCLK when control TBRCIp (bit registers 01EH (for This signal high during VT1.5 TU11 bytes from system. Control bits must same value both proper operation. Drop Indicator: Telecom valid from system. Valid rising edge BDCLK when control TBRCIp (bit registers 01EH (for This signal high during VT1.5 TU11 bytes from system. Control bits must same value both proper operation.
BDCLK
ADC1J1V1
BDC1J1V1
ADSPE
BDSPE
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T1Mx28 TXC-04228
DATA SHEET
Symbol ADD(0-7)
Lead M24, H24, E21, L23, H23, J23, K23, AC19, AD18, AC18, AC20, AD15, AD17, AC17, AC15
I/O/P
Type
Name/Function Drop Data: Telecom data from system; ADD0 LSB. Valid rising edge ADCLK when control TBRCIp (bit registers 01EH (for Control bits must same value both proper operation. Drop Data: Telecom data from system; BDD0 LSB. Valid rising edge BDCLK when control TBRCIp (bit registers 01EH (for Control bits must same value both proper operation. Drop Parity Bit: Telecom parity received over ADD(0-7), ADSPE ADC1J1V1. Valid rising edge ADCLK when control TBRCIp (bit registers 01EH (for odd/even selectable control TBPEp (bit registers 007H (for when even parity selected. When control TBPISp (bit registers 007H (for only ADD(0-7) checked parity. Control bits must same value both proper operation. Drop Parity Bit: Telecom parity received over BDD(0-7), BDSPE BDC1J1V1. Valid rising edge BDCLK when control TBRCIp (bit registers 01EH (for odd/even selectable control TBPEp (bit registers 007H (for when even parity selected. When control TBPISp (bit registers 007H (for only BDD(0-7) checked parity. Control bits must same value both proper operation. Drop Signal Fail: Signal fail indication valid rising edge ADCLK when control TBRCIp (bit registers 01EH (for ADFAIL high specific slot contains invalid data (ADD(0-7)); alarms invalid masked; generated. Control bits must same value both proper operation. Drop Signal Fail: Signal fail indication valid rising edge BDCLK when control TBRCIp (bit registers 01EH (for BDFAIL high specific slot contains invalid data (BDD(0-7)); alarms invalid masked; generated. Control bits must same value both proper operation.
BDD(0-7)
ADPAR
BDPAR
ADFAIL
BDFAIL
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DATA SHEET
T1Mx28 TXC-04228
Symbol AACLK
Lead
I/O/P
Type
Name/Function Clock: Telecom clock data system; 19.44 lead CONFIGI tied high 6.48 lead CONFIGI tied low. When control TBTCIp (register 01EH, (for AASPE AAC1J1V1 signals clocked rising edge AACLK. falling edge AACLK used clock AAD(0-7), AAPAR AAADD signals that these signals sampled next rising edge. When TBTCIp opposite clock edges used. Control bits must same value both proper operation. Clock: Telecom clock data system; 19.44 lead CONFIGI tied high 6.48 lead CONFIGI tied low. When control TBTCIp (register 01EH, (for BASPE BAC1J1V1 signals clocked rising edge BACLK. falling edge BACLK used clock BAD(0-7), BAPAR BAADD signals that these signals sampled next rising edge. When TBTCIp opposite clock edges used. Control bits must same value both proper operation. C1J1V1 Indicator: Telecom C1#1, J1#1, V1#1 valid data system. This signal sampled rising edge AACLK when control TBTCIp (register 01EH, (for Control bits must same value both proper operation. C1J1V1 Indicator: Telecom C1#1, J1#1, V1#1 valid data system. This signal sampled rising edge BACLK when control TBTCIp (register 01EH, (for Control bits must same value both proper operation. Indicator: Telecom valid data system. This signal sampled rising edge AACLK when control TBTCIp (register 01EH, (for This signal high during VT1.5 TU-11 bytes system. Control bits must same value both proper operation. Indicator: Telecom valid data system. This signal sampled rising edge BACLK when control TBTCIp (register 01EH, (for This signal high during VT1.5 TU-11 bytes system. Control bits must same value both proper operation.
BACLK
AD19
AAC1J1V1
BAC1J1V1
AASPE
BASPE
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T1Mx28 TXC-04228
DATA SHEET
Symbol AAD(0-7)
Lead
I/O/P O(T)
Type
Name/Function
Data: Telecom data system; AAD0 LSB. T1Mx28 will output data falling edge AACLK when control TBTCIp (register 01EH, Control TBDDp (bit registers 01EH (for selects zero AACLK clock period delay single AACLK clock period delay Control bits must same value both proper operation. These signals tristate condition when T1Mx28 driving Bus. Data: Telecom data system; BAD0 LSB. T1Mx28 will output data falling edge BACLK when control TBTCIp (register 01EH, Control TBDDp (bit registers 01EH (for selects zero BACLK clock period delay single BACLK clock period delay Control bits must same value both proper operation. These signals tristate condition when T1Mx28 driving Bus. Parity Bit: Telecom parity generated AAD(0-7), AASPE AAC1J1V1 placed Telecom Bus. T1Mx28 will output parity falling edge AACLK when control TBTCIp (register 01EH, (for Control TBPEp (register 007H, (for selects odd/ even parity. When TBPEp parity selected. When control TBPISp (bit registers 007H (for only AAD(0-7) included parity calculation. Control TBDDp (bit registers 01EH (for selects zero AACLK clock period delay single AACLK clock period delay Control bits must same value both proper operation. This signal tristate condition when T1Mx28 driving Bus.
BAD(0-7)
AF21, AE21, AF20, AE20, AF19, AE19, AF18, AE18
O(T)
AAPAR
O(T)
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DATA SHEET
T1Mx28 TXC-04228
Symbol BAPAR
Lead AE17
I/O/P O(T)
Type
Name/Function
Parity Bit: Telecom parity generated BAD(0-7), BASPE BAC1J1V1 placed Telecom Bus. T1Mx28 will output parity falling edge BACLK when control TBTCIp (register 01EH, Control TBPEp (register 007H, selects odd/even parity. When TBPEp parity selected. When control TBPISp (bit registers 007H (for only BAD(0-7) included parity calculation. Control TBDDp (bit registers 01EH (for selects zero BACLK clock period delay single BACLK clock period delay Control bits must same value both proper operation. This signal tristate condition when T1Mx28 driving Bus. Data Present Indicator: Telecom device outputs valid. This signal goes falling edge AACLK when control TBTCIp, register 01EH, (for This signal active when T1Mx28 writes Telecom Bus, allowing external drivers used. Control TBDDp (bit registers 01EH (for selects zero AACLK clock period delay single AACLK clock period delay Control bits must same value both proper operation. This signal tristate condition when T1Mx28 driving Bus. Data Present Indicator: Telecom device outputs valid. This signal goes falling edge BACLK when control TBTCIp register 01EH, (for This signal active when T1Mx28 writes Telecom Bus, allowing external drivers used. Control TBDDp (bit registers 01EH (for selects zero BACLK clock period delay single BACLK clock period delay Control bits must same value both proper operation. This signal tristate condition when T1Mx28 driving Bus. Check: Used determine another T1Mx28 same Telecom driving same slot. Each ABUSCHK(1-4) input connected AAADD(1-2) same another T1Mx28. collision detected, status TBXESp (bit register 00BH Latched value, mask register bits also supplied. operations section dual single connections.
AAADD(1-2)
O(T)
BAADD(1-2)
AE22, AF17
O(T)
ABUSCHK(1-4)
G26,
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T1Mx28 TXC-04228
DATA SHEET
Symbol BBUSCHK(1-4)
Lead AA3, AD22, AD20
I/O/P
Type
Name/Function Check: Used determine another T1Mx28 same Telecom driving same slot. Each BBUSCHK(1-4) input connected BAADD(1-2) same another T1Mx28. collision detected, status TBXESp (bit register 00BH Latched value, mask register bits also supplied. operations section dual single connections. Master: When tied ground, stuff columns driven zero AAD(0-7) with correct parity. Telecom Operations subsection. Master: When tied ground, stuff columns driven zero BAD(0-7) with correct parity. Telecom Operations subsection. Data Enable: When high, AAD(0-7), AAPAR AAADD(1-2) enabled. normally tied AASPE float Telecom during TOH. Data Enable: When high, BAD(0-7), BAPAR BAADD(1-2) enabled. normally tied BASPE float Telecom during TOH. Add/Drop Configuration Input: Configuration Telecom Bus. CONFIGI high, both Telecom Buses slot/6.48 MHz. CONFIGI low, both Telecom Buses slot/19.44 MHz.
MASTERA
TTLp
MASTERB
TTLp
ADATEN
BDATEN
AD21
CONFIGI
MICROPROCESSOR INTERFACE Symbol RSTI Lead AB17 I/O/P Type TTLp Name/Function Hardware Reset: Device reset. This active signal will reset twenty-eight mappers. should held minimum clock periods PCKI. Motorola Mode: Motorola Intel microprocessor mode select. High selects Motorola. selects Intel. Data: Microprocessor bidirectional, tristate data bus; DTB0 LSB. Address Bus: Microprocessor address bus; ADDR0 LSB.
MOTOI DTB(0-7)
D11, D10, E10, G22, J22, G23, H22, K22, C11, C10,
ADDR(0-8)
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DATA SHEET
T1Mx28 TXC-04228
Symbol SELIp
Lead E13, M22, AB15
I/O/P
Type TTLp
Name/Function Select: Microprocessor Interface select. selects interface each group seven mappers allows transfer information between T1Mx28 microprocessor. When channels addressed. When channels 8-14 addressed. When channels 15-21 addressed. When channels 22-28 addressed. Read: Read Read/Write. Intel: read T1Mx28. Motorola: high read/low write. Write: Intel mode only; write T1Mx28. Ready: Intel mode: high acknowledges that data transfer take place this cycle. indicates wait states. Data Transfer Acknowledge: Motorola mode: during read indicates data valid. during write indicates data accepted.
READI READI/WRI RDYO/
O(T)
DTACKO
INTOp/
E12, H25, AE16
Interrupt: Intel mode: control IPOLp (bit register 006H high indicates interrupt request microprocessor from group seven channels indicated lead channels 1-7, channels 8-14, etc.). Interrupt Request: Motorola mode: control IPOLp (bit register 006H indicates interrupt request microprocessor from group seven channels indicated lead channels 1-7, channels 8-14, etc.).
IRQOp
PCKI
Processor Clock: Processor Clock Input. Required device operation; MHz. T1Mx28 will continue pass data loss PCKI, microprocessor access will blocked.
BOUNDARY SCAN TEST PORT Symbol Lead I/O/P Type Name/Function Test Clock: IEEE 1149.1 Boundary Scan Clock input. This clock used shift data into rising edge falling edge. Test Data Input: Boundary Scan Data input. Serial test instructions data clocked into this lead rising edge TCK. Test Data Output: Boundary Scan Data output. Serial data test instructions clocked this lead falling edge TCK.
TTLp
O(T)
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T1Mx28 TXC-04228
DATA SHEET
Symbol
Lead
I/O/P
Type TTLp
Name/Function Test Mode Select: Boundary Scan Test Mode Select input; sampled rising edge T1Mx28 into test mode. Test Reset: Boundary Scan Reset input. This lead will asynchronously reset Test Access Port (TAP) controller held minimum duration This lead held low, asserted pulsed reset controller T1Mx28 power-up. High Impedance Select: Grounding these leads causes outputs except high impedance group seven mappers chosen, alters internal registers. Test Device test leads. Must connected ground. Test Device test leads. Must connected ground.
TTLp
HIGHZp
G24, AD16
CMOS
TSTAp TSTBp
F23, AB6, AB16 F22, AA5, AC16
CMOS CMOS
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DATA SHEET ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage input voltage Storage temperature range Ambient operating temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit Classification Symbol -0.3 -0.5 VDD+ Unit
T1Mx28 TXC-04228
Conditions Note Notes Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note
Level
absolute value 1500
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. exceed actual operating supply voltage (VDD) more than volts. Test method MIL-STD-883D, Method 3015.7.
THERMAL CHARACTERISTICS
Parameter Thermal Resistance: junction ambient Unit
oC/W
Test Conditions ft/min linear airflow.
POWER REQUIREMENTS
Parameter Power dissipation, 3.15 3.30 4001 13201 3.45 5002 17252 Unit Asynchronous mapping 6.48 Telecom Bus. Byte-synchronous mapping 19.44 Telecom Bus. Test Conditions
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T1Mx28 TXC-04228
DATA SHEET
INPUT, OUTPUT INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS CMOS Parameter Input leakage current Input capacitance (leads BLO) Input capacitance (lead SRCLK) Input capacitance (all other leads) Unit Test Conditions 3.15 <VDD 3.45 3.15 <VDD 3.45 3.45
INPUT PARAMETERS Parameter Input leakage current Input capacitance (leads ABUSCHK(1-4) BBUSCHK(1-4)) Input capacitance (leads ACSO, BCSO System Interface input leads listed above below) Input capacitance (lead CONFIGI other leads) Unit Test Conditions 3.15 <VDD 3.45 3.15 <VDD 3.45
INPUT PARAMETERS TTLp Parameter Input leakage current Input capacitance (leads RSTI, TRS) Input capacitance (all other leads)
Note: Input (nominal) internal pull-up resistor.
Unit
Test Conditions 3.15 <VDD 3.45 3.15 <VDD 3.45 3.45; Input volts
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DATA SHEET
OUTPUT PARAMETERS CMOS Parameter tRISE tFALL Leakage tristate -4.0 Unit CLOAD CLOAD 3.45 input
T1Mx28 TXC-04228
Test Conditions 3.15; -4.0 3.15;
OUTPUT PARAMETERS CMOS OPEN DRAIN Parameter tFALL High leakage current Unit CLOAD 3.45 Test Conditions 3.15;
Note: Open Drain requires kOhm external pull-up resistor. this resistor provided output behaves tristate.
OUTPUT PARAMETERS Parameter tRISE tFALL -8.0 Unit CLOAD CLOAD Test Conditions 3.15; -8.0 3.15;
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T1Mx28 TXC-04228
DATA SHEET
INPUT/OUTPUT PARAMETERS CMOS Parameter Input leakage current Input capacitance tRISE tFALL -4.0 Unit CLOAD CLOAD 3.15; -4.0 3.15; Test Conditions 3.15 <VDD 3.45 3.15 <VDD 3.45 3.45
INPUT/OUTPUT PARAMETERS Parameter Input leakage current Input capacitance (leads DTB(0-7)) tRISE tFALL -8.0 Unit CLOAD CLOAD 3.15; -8.0 3.15; Test Conditions 3.15 <VDD 3.45 3.15 <VDD 3.45 3.45
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DATA SHEET TIMING CHARACTERISTICS
T1Mx28 TXC-04228
Detailed timing diagrams T1Mx28 illustrated Figures through with values timing intervals tabulated below each diagram. output times measured with maximum load capacitance, unless otherwise indicated. Timing parameters measured voltage levels (VOH VOL)/2 output signals (VIH VIL)/2 input signals. Figure Tributary Input Timing
tCYC tPWH tPWL
LRCLKn (see Notes RPOSn RNEGn RSIGLn RCVn (Inputs)
tSU(1)
tH(1)
RSYNCn (see Notes
Note: n=1-28
tH(2) tSU(2)
Parameter LRCLKn clock period LRCLKn high time LRCLKn time RPOSn/RNEGn/RSIGLn/RCVn setup time LRCLKn RPOSn/RNEGn/RSIGLn/RCVn hold time after LRCLKn RSYNCn pulse width input RSYNCn pulse width output RSYNCn setup input before LRCLKn RSYNCn hold input after LRCLKn RSYNCn delay output after LRCLKn
Symbol tCYC tPWH tPWL tSU(1) tH(1) tSU(2) tH(2)
Unit
Notes: true byte-synchronous mode (control bits MODE0 MODE1 LRCLKn RSYNCn outputs. other modes LRCLKn RSYNCn inputs. LRCLKn active edge inverted control RCAEp (bit register 007H; shown RCAEp RPOSn, RNEGn, RSIGLn, RSYNCn RCVn clocked falling edge LRCLKn. true byte-synchronous mode operation, LRCLKn RSYNCn outputs. RSYNCn output delayed from rising edge LRCLKn when control RCAEp
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Figure Tributary Output Timing
tCYC LTCLKn* TPOSn TNEGn TSIGLn TSYNCn
Note: n=1-28
tPWH
Parameter LTCLKn clock period LTCLKn duty cycle, tPWH/tCYC TPOSn/TNEGn/TSIGLn output delay after LTCLKn TSYNCn delay after LTCLKn TSYNCn pulse width
Symbol tCYC -tOD
-5.0 -5.0
Unit
LTCLKn inverted control TCAEp (bit register 007H; shown TCAEp
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Figure Signaling Highway Structure
T1Mx28 TXC-04228
LRCLKn LTCLKn tCYC RSYNCn TSYNCn RPOSn/ RNEGn TPOSn/ TNEGn RSIGLn*
-DS0
F1/M1
S1/C1
TSIGLn*
F1/M1
S1/C1
Multi-frame Number 4630 4631 Multi-frame
Note: n=1-28
Note shown 16-state signaling. Operation section. Note TPOSn, TNEGn, RPOSn, RNEGn, RSIGLn, TSIGLn unused bits (see Operation section). Note present positions through (DS0 24); bits through unused.
Parameter TSYNCn/RSYNCn clock period (n=1-28) TSYNCn/RSYNCn pulse width (n=1-28)
Symbol tCYC
3.000 clock period LTCLKn LRCLKn*
Unit
TSYNCn RSYNCn should valid active edge LTCLKn LRCLKn, respectively.
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Figure Serial Control Port Structure Timing
LCSn
tCYC tD(1)
tPWH
tH(2)
LSCLKp
tPWL
tH(1)
LSDIp
Data Input/Output
LSDOp
addr
addr
addr
addr
addr
addr
addr
Address/Command Byte
Note: n=1-28, p=1-4
tD(2)
Parameter LSCLKp clock period LSCLKp high time LSCLKp time LCSn delay time LSCLKp LCSn inactive pulse width LSDIp setup time LSCLKp LSDIp hold time after LSCLKp LSCLKp LCSn inactive LSDOp delay after LSCLKp LSCLKp rise fall times (10% 90%)
Symbol tCYC tPWH tPWL tD(1) tH(1) tH(2) tD(2)
Unit
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Figure Telecom Input Timing 6.48 Operation
tCYC tPWL tH(1) tSU(1) tH(2) tSU(3) tSU(2) V1#1
T1Mx28 TXC-04228
ADCLK BDCLK (Input) ADD(0-7) BDD(0-7) ADPAR DDPAR (Input) ADSPE BDSPE (Input) tPWH
V4#1
tH(3) V1#1
ADC1J1V1 BDC1J1V1 (Input)
Parameter ADCLK(BDCLK) clock period ADCLK(BDCLK) high time ADCLK(BDCLK) time ADD(0-7)(BDD(0-7))/ADPAR(BDPAR) setup time ADCLK(BDCLK) ADD(0-7)(BDD(0-7))/ADPAR(BDPAR) hold time after ADCLK(BDCLK) ADSPE(BDSPE) setup time ADCLK(BDCLK) ADSPE(BDSPE) hold time after ADCLK(BDCLK) ADC1J1V1(BDC1J1V1) setup time ADCLK(BDCLK) ADC1J1V1(BDC1J1V1) hold time after ADCLK(BDCLK) ADC1J1V1(BDC1J1V1) pulse width
Symbol tCYC tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3)
154.32
Unit
116*
gapped clock applications, skipping rising (and next falling) edge ADCLK(BDCLK) will extend current time twice listed value. data clocked rising clock edge unless control TBRCIp (bit register 01EH which case data clocked falling clock edge.
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Figure Telecom Input Timing 19.44 Operation
tCYC tPWL tSU(1) C1#1
ADCLK BDCLK (Input) ADD(0-7) BDD(0-7) ADPAR BDPAR (Input) ADSPE BDSPE (Input) tPWH
tH(1) J1#1 tSU(2) V1#1 V4#1
tH(2) tSU(3) C1#1
tH(3) J1#1
V1#1
ADC1J1V1 BDC1J1V1 (Input)
Parameter ADCLK(BDCLK) clock period ADCLK(BDCLK) high time ADCLK(BDCLK) time ADD(0-7)(BDD(0-7))/ADPAR(BDPAR) setup time ADCLK(BDCLK) ADD(0-7)(BDD(0-7))/ADPAR(BDPAR) hold time after ADCLK(BDCLK) ADSPE(BDSPE) setup time ADCLK(BDCLK) ADSPE(BDSPE) hold time after ADCLK(BDCLK) ADC1J1V1(BDC1J1V1) setup time ADCLK(BDCLK) ADC1J1V1(BDC1J1V1) hold time after ADCLK(BDCLK) ADC1J1V1(BDC1J1V1) pulse width individual pulse (e.g., isolated ADC1J1V1(BDC1J1V1) J1#1 V1#1 delay (STS-3 mode) ADC1J1V1(BDC1J1V1) J1#1 V1#1 delay (STM-1 mode)
Symbol tCYC tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3)
51.44
Unit
cycles ADCLK(BDCLK) cycles ADCLK(BDCLK)
gapped clock applications, skipping rising (and next falling) edge ADCLK(BDCLK) will extend current time twice listed value. data clocked rising clock edge unless control TBRCIp (bit register 01EH which case data clocked falling clock edge.
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Figure Telecom Output Timing 6.48 Operation
tCYC AACLK BACLK (Input) AAD(0-7) BAD(0-7) AAPAR BAPAR (Output) AASPE BASPE (Input) AAC1J1V1 BAC1J1V1 (Input) AAADD(1-2) BAADD(1-2) (Output) ADATEN BDATEN (Input) tPWL tD(1) tSU(1) tSU(2) tH(2) V1#1 tD(4) tH(1) V1#1
T1Mx28 TXC-04228
tPWH
tD(2) DATA tD(3)
tD(5)
tD(6)
Parameter AACLK(BACLK) clock period AACLK(BACLK) high time AACLK(BACLK) time AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) delay time after AACLK(BACLK) AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) float time after AACLK(BACLK) AASPE(BASPE) setup time AACLK(BACLK) AASPE(BASPE) hold time after AACLK(BACLK) AAC1J1V1(BAC1J1V1) setup time AACLK(BACLK) AAC1J1V1(BAC1J1V1) hold time after AACLK(BACLK) AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) delay time after ADATEN(BDATEN) AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) delay time after ADATEN(BDATEN) AAADD(1-2)(BAADD(1-2)) delay time after ADATEN(BDATEN) AAADD(1-2)(BAADD(1-2)) delay time after ADATEN(BDATEN) AAADD(1-2)(BAADD(1-2)) delay time after AACLK(BACLK) AAC1J1V1(BAC1J1V1) pulse width AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) rise/fall times (10% 90%)
Symbol tCYC tPWH tPWL tD(1) tSU(1) tH(1) tSU(2) tH(2) tD(2) tD(3) tD(4) tD(5) tD(6)
154.32
116*
Unit
gapped clock applications, skipping rising (and next falling) edge AACLK(BACLK) will extend current time twice listed value. control TBTCIp (bit register 01EH data clocked rising AACLK(BACLK) clock edge falling AACLK(BACLK) clock edge, shown timing diagram. control TBTCIp data clocked falling clock edge rising clock edge AACLK(BACLK). control TBDDp AAD(0-7)(BAD(0-7)), AAPAR(BAPAR) AAADD(1-2)(BAADD(1-2)) delayed clock period from what shown timing diagram with reference AASPE(BASPE) AAC1J1V1(BAC1J1V1); Input ADATEN(BDATEN) must also delayed clock period AACLK(BACLK).
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Figure Telecom Output Timing 19.44 Operation
tCYC AACLK BACLK (Input) AAD(0-7) BAD(0-7) AAPAR BAPAR (Output) AASPE BASPE (Input) AAC1J1V1 BAC1J1V1 (Input) AAADD(1-2) BAADD(1-2) (Output) ADATEN BDATEN (Input) tPWL tD(1) tSU(1) tSU(2) tH(2) C1#1 J1#1 tD(7) V1#1 tD(4) tD(5) C1#1 tH(1) J1#1 V1#1
tPWH
tD(2) DATA tD(3)
tD(6)
Parameter AACLK(BACLK) clock period AACLK(BACLK) high time AACLK(BACLK) time AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) delay time after AACLK(BACLK) AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) float time after AACLK(BACLK) AASPE(BASPE) setup time AACLK(BACLK) AASPE(BASPE) hold time after AACLK(BACLK) AAC1J1V1(BAC1J1V1) setup time AACLK(BACLK) AAC1J1V1(BAC1J1V1) hold time after AACLK(BACLK) AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) delay time after ADATEN(BDATEN) AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) delay time after ADATEN(BDATEN) AAADD(1-2)(BAADD(1-2)) delay time after ADATEN(BDATEN) AAADD(1-2)(BAADD(1-2)) delay time after ADATEN(BDATEN) AAADD(1-2)(BAADD(1-2)) delay time after AACLK(BACLK) AAC1J1V1(BAC1J1V1) pulse width individual pulse (e.g., isolated
Symbol tCYC tPWH tPWL tD(1) tSU(1) tH(1) tSU(2) tH(2) tD(2) tD(3) tD(4) tD(5) tD(6)
51.44
Unit
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T1Mx28 TXC-04228
cycles AACLK(BACLK) cycles AACLK(BACLK) Unit
Parameter AAD(0-7)(BAD(0-7))/AAPAR(BAPAR) rise/fall times (10% 90%) AAC1J1V1(BAC1J1V1) J1#1 V1#1 delay (STS-3 mode) AAC1J1V1(BAC1J1V1) J1#1 V1#1 delay (STM-1 mode)
Symbol tD(7) tD(7)
gapped clock applications, skipping rising (and next falling) edge AACLK(BACLK) will extend current time twice listed value. control TBTCIp (bit register 01EH data clocked rising AACLK(BACLK) clock edge falling AACLK(BACLK) clock edge, shown timing diagram. control TBTCIp data clocked falling clock edge rising clock edge AACLK(BACLK). control TBDDp AAD(0-7)(BAD(0-7)), AAPAR(BAPAR) AAADD(1-2)(BAADD(1-2)) delayed clock period from what shown timing diagram with reference AASPE(BASPE) AAC1J1V1(BAC1J1V1); Input ADATEN(BDATEN) must also delayed clock period AACLK(BACLK).
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Figure Datacom Mode Output Timing
tCYC tPWL tPWH
LTCLKn
tD(1)
TGCOn (TNEG)
tD(2) Time
TPOSn
TSYNCn
Note:
Parameter LTCLKn period Delay LTCLKn1,2 TGCOn Delay LTCLKn TPOSn TSYNCn Fall Time (90% 10%)3- LTCLKn, TGCOn, TPOSn TSYNCn LTCLKn TGCOn High time LTCLKn TGCOn time Rise Time (10% TSYNCn 90%)3LTCLKn, TGCOn, TPOSn
Symbol tCYC tD(1) tD(2) tPWH tPWL
-5.0
Unit tCYC tCYC
Notes: LTCLKn inverted with control TCAEp (bit register 007H. LTCLKn shown with TCAEp load
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Figure Datacom Mode Input Timing
T1Mx28 TXC-04228
tCYC tPWL tPWH
LRCLKn (see Note RGCOn
tD(1)
tD(2)
RSYNCn (Output) (See Note RSYNCn (Input)
Time
RPOSn
Note:
Parameter LRCLKn period Delay LRCLKn
Symbol tCYC
Unit
RGCOn
tD(1) tD(2) tPWH tPWL
Delay LRCLKn1,2 RSYNCn Output Fall Time (90% 10%) RGCOn, LRCLKn RSYNCn Outputs Hold RPOSn RSYNCn input after LRCLKn1,2 LRCLKn RGCOn High time LRCLKn RGCOn time Rise Time (10% 90%) RGCOn, LRCLKn RSYNCn Outputs Setup RPOSn RSYNCn input LRCLKn1,2
Notes: LRCLKn active edge inverted control RCAEp (bit register 007H; shown RCAEp RPOSn, RNEGn, RSIGLn, RSYNCn RCVn clocked falling edge LRCLKn. true byte-synchronous mode operation, LRCLKn RSYNCn outputs. RSYNCn output delayed from rising edge LRCLKn when control RCAEp LRCLKn shown with RCAEp load. When RSYNCn output, delayed from falling edge LRCLKn when RCAEp
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Figure Intel Microprocessor Read Cycle Timing
ADDR (0-8)
(0-7)
tD(1) tSU(1)
SELIp
tSU(2) tPW(1)
READI
tD(2)
RDYO
tPW(2)
Parameter ADDR(0-8) setup time SELIp DTB(0-7) valid delay after RDYO DTB(0-7) float time after READI SELIp setup time READI READI pulse width SELIp hold time after READI RDYO delay after READI RDYO pulse width
Symbol tSU(1) tD(1) tSU(2) tPW(1) tD(2) tPW(2)
Unit
-1/2 cycle PCKI* cycles PCKI*
cycles PCKI*
*Note: PCKI (not shown) Processor Clock Input, MHz, which required device operation.
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Figure Motorola Microprocessor Read Cycle Timing
T1Mx28 TXC-04228
ADDR (0-8)
DTB(0-7)
tSU(1) tF(1) tPW(1) tSU(2)
SELIp
READI/WRI tPW(2) DTACKO tD(2)
tD(1) tF(2)
Parameter DTB(0-7) float time after SELIp ADDR(0-8) valid setup time SELIp READI/WRI setup time SELIp SELIp pulse width DTACKO pulse width DTB(0-7) output delay after DTACKO DTACKO float time after SELIp DTACKO delay after SELIp
Symbol tF(1) tSU(1) tSU(2) tPW(1) tPW(2) tD(1) tF(2) tD(2)
cycles PCKI*
Unit
cycles PCKI* -1/2 cycle PCKI*
*Note: PCKI (not shown) Processor Clock Input, MHz, which required device operation.
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Figure Intel Microprocessor Write Cycle Timing
ADDR (0-8)
tH(1)
DTB(0-7)
tSU(2) tSU(1)
SELIp
tSU(3)
tPW(1)
RDYO
tPW(2)
Parameter DTB(0-7) valid setup time DTB(0-7) hold time after ADDR(0-8) setup time SELIp SELIp setup time pulse width RDYO delay after RDYO pulse width
*Note:
Symbol tSU(1) tH(1) tSU(2) tSU(3) tPW(1) tPW(2)
Unit
cycles PCKI*
PCKI (not shown) Processor Clock Input, MHz, which required device operation. Wait states only occur write cycle immediately follows previous read write cycle (e.g.'read modify write' word-wide write).
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Figure Motorola Microprocessor Write Cycle Timing
T1Mx28 TXC-04228
ADDR (0-8) tH(1) DTB(0-7)
tSU(1) tSU(2)
SELIp
tPW(1) tSU(3)
READI/WRI
tPW(2)
DTACKO
Parameter DTB(0-7) valid setup time SELIp DTB(0-7) valid hold time after SELIp ADDR(0-8) valid setup time SELIp READI/WRI setup time SELIp SELIp pulse width DTACKO pulse width DTACKO float time after SELIp DTACKO delay after SELIp
*Note:
Symbol tSU(1) tH(1) tSU(2) tSU(3) tPW(1) tPW(2)
Unit
cycles PCKI*
PCKI (not shown) Processor Clock Input, MHz, which required device operation. Wait states only occur write cycle immediately follows previous read write cycle (e.g.'read modify write' word-wide write).
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Figure Boundary Scan Timing
tPWL tPWH
(Input)
tH(1) tSU(1)
(Input)
tH(2) tSU(2)
(Input)
(Output)
Parameter clock high time clock time setup time hold time after setup time hold time after delay from
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2)
Unit
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GENERAL MAPPER APPLICATION OVERVIEW
T1Mx28 TXC-04228
T1Mx28 used wide variety applications that require either asynchronous mapping signal into SONET payload which input clock data replicated output, byte-synchronous mapping signal into SONET payload which only input clock data replicated output, visibility signaling information replicated output. When used asynchronous application side mapper connects line through Line Interface Units (LIUs) that recover 1.544 clock from received data, provide clock data T1Mx28, input clock data from T1Mx28 format line signal transmission. Four ports provided control LIUs from T1Mx28. When used byte-synchronous applications, framers (like TranSwitch T1Fx8) inserted between LIUs T1Mx28 delineate DS0s, extract insert signaling, process alarms, etc. byte-synchronous applications also used direct interface sources DS0s (e.g., time slot interchangers, codecs) data sources like fractional with HDLC protocol channels (like TranSwitch MCHDLC). T1Mx28 provides complete clock recovery signals through stage digital filter, eliminating need special external de-jitter buffers while still meeting stringent Bellcore MTIE requirements. T1Mx28 provides complete SONET order path termination origination functions (VT1.5/ TU-11) with alarm mapping from line. system side, that required high order section, line path termination/origination function. Telecom provided T1Mx28 allows multiple devices connected seamlessly TranSwitch PHAST-1, SOT-3 PHAST-3N device, which supply these high order functions. Microprocessor access provided optional overhead bytes. redundant ring applications internal ring support port provided well special alarm output isolation input. microprocessor port provided configure T1Mx28 well provide interrupts device-wide/Telecom alarms well VT1.5/TU-11 alarms. second shadow registers provided assist preparation performance monitoring information. IEEE 1149.1 boundary scan function internal PRBS generator/analyzer provided board test support. LINE INTERFACE SELECTION Each twenty-eight T1Mx28 channels individually programmed asynchronous mode, byte-synchronous mode clock master, modified byte-synchronous mode where T1Mx28 channel clock slave which pointer movements generated needed incoming signal SONET/ payload. table below details options present Line Interface. Mode Operation Asynchronous Asynchronous Asynchronous Asynchronous Byte-Synchronous LRCLK/RSYNCn Line Code B8ZS
MODE1 MODE0 X+00 LCODE X+00 ENCOD X+00 DATACOM X+00
RNEGn Data Data RCVn RCVn RSIGLn input
TNEGn
X+00
Data Data High TSIGLn output
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Mode Operation Byte-Synchronous (Datacom) LRCLK/RSYNCn Modified byte-Synchronous LRCLK/RSYNCn Modified byte-Synchronous (Datacom) LRCLK/RSYNCn
Note: X=don't care
Line Code
MODE1
MODE0 X+00
LCODE X+00
ENCOD X+00
DATACOM X+00
RNEGn RGCOn output RSIGLn input RGCOn output
TNEGn
X+00
TGCOn output TSIGLn output TGCOn output
Asynchronous Operation with Line Interface Each twenty-eight mapper channels T1Mx28 programmed provide either dual unipolar interface interface. dual unipolar interface selected when written into control ENCOD (bit control register located address X+00H memory map. 040H), where number mapper selected (1-28), explained Memory section. B8ZS line coder/ decoder (CODEC) feature selected dual unipolar interface. B8ZS CODEC selected writing control LCODE (bit register X+00H. will select CODEC. B8ZS stands Bipolar with Eight Zero Substitution, which described ANSI Document ANSI T1.102-1993 other Bellcore documents. clock polarity input output line clocks selectable writing sense required global control bits TCAEp RCAEp (bits register 007H. When mapper configured dual unipolar mode, line signal monitored loss signal (LOS). detected transitions present pulse positions. Recovery occurs when ones density 12.5% more detected pulse positions. status LOSS (bit register X+10H indicates this condition. mask, LOSM, latched value, LOSE, value, LOSPM value, LOSFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively. Coding violations counted 12-bit performance counter located register locations X+22H X+23H with shadow value registers X+2AH X+2BH. counter overflow CVOS (bit register X+10H provided. mask, CVOM, latched value, CVOE, value, CVOPM value, CVOFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively. Excessive zeros more B8ZS more AMI) included control ENZC (bit register X+00H indication provided which checks more than 99.9% ones occur millisecond period. indication provided less than 99.9% ones occur millisecond period. Status DAISS (bit register X+10H indicates condition. mask, DAISM, latched value, DAISE, value, DAISPM value, DAISFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively. condition also used generate (DS1 payload all-ones will mapped place received signal) control LOS2AIS (bit register X+01H Coder block provides AMI/B8ZS encoder. This block provides generation either from Microprocessor Interface control SDAISL (bit register X+03H when optionally from various system conditions AIS/LOP, Signal Label Mismatch Unequipped) which individually enabled control bits VAIS2AIS (bit X+01H), SLM2AIS (bit X+02H) UNE2AIS (bit X+02H) being high level signal failure input leads ADFAIL BDFAIL will cause twenty-eight mappers. 'transmit all-zeros' capability provided conserve power external Line Transceiver when required setting control SDAISL (bit register X+03H when control TBRVAL (bit register X+04H also (Drop slot assigned). connections between T1Mx28 mapper external line interface transceivers shown Figure below dual unipolar mode.
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T1Mx28 TXC-04228
RXTIP RXRING TXTIP TXRING
Line Interface Transceiver channel
SCLK
receive transmit
RPOSn RNEGn LRCLKn TPOSn TNEGn LTCLKn
T1Mx28
LCSn
LAISn Other Transceivers
LSCLKp LSDOp LSDIp
Note: channel number group seven mappers) number
Figure Line Interface Dual Unipolar Mode interface selected when written into control ENCOD (bit register X+00H. clock polarity line input output clocks selectable writing global control bits TCAEp RCAEp (bits register 007H. Options provided inverting polarity transmit receive data leads. written control TXNRZPp (bit global register 007H inverts polarity transmit data signal, TPOSn, while written control RXNRZPp (bit same register inverts polarity receive data signal RPOSn. mode, RNEGn lead used input external indication coding violations (RCVn). External coding violations counted same 12-bit performance counter described above. Coding violations counted when input high rising edges line clock LRCLKn. same detector described above bipolar available mode. detected only externally input lead LAISn. setting control EXPLOS (bit register X+00H LOSS status plus latched event, mask, functions provided described above. transmit direction, when mode selected, TNEGn lead becomes spare drive lead. When control ENCOD (bit register X+00H output state TNEGn defined value written LCODE (bit register X+00H (LCODE TNEGn LCODE high TNEGn). typical interface between mapper T1Mx28 external line transceiver shown Figure below mode. TNEGn, example, used select encoding mode LIU.
RXTIP RXRING TXTIP TXRING
Line Interface Transceiver channel
SCLK
receive transmit
RPOSn RCVn LRCLKn TPOSn TNEGn LTCLKn
T1Mx28
LCSn LAISn LSCLKp LSDOp LSDIp
Other Transceivers
Note: channel number group seven mappers) number
Figure Line Interface Mode
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T1Mx28 TXC-04228
DATA SHEET
Byte-Synchronous Operation with Line Interface byte-synchronous operation line interface operates mode with RSIGLn TSIGLn carrying signaling information from/to external framer using negative polarity input output leads. Figure basic byte-synchronous setup. Typical applications shown Figure byte-synchronous applications where signaling used, Datacom option provided connections HDLC controllers other devices that operate over payload only. TGCO RGCO gapped clock outputs clocking data TPOSn RPOSn. clock gapped during frame time every This option available setting control DATACOM (bit register X+00H byte-synchronous applications that require DS1-based performance monitoring (control bits MODE1, MODE0 register X+00H bits only), CRC-6 generated optionally each superframe data presented RPOSn inserted frame locations following superframe mapped. When control CRC6 (bit register X+01H CRC-6 both inserted checked. After demapping CRC-6 checked. CRC-6 errors share 12-bit line code violation counter shadow register overflow indications support performance monitoring. CRC-6 errors counted 12-bit performance counter located register locations X+22H X+23H with shadow value registers X+2AH X+2BH. Each superframe which calculated CRC-6 value does match received CRC-6 value increments counter one. counter overflow CVOS (bit register X+10H provided. mask, CVOM, latched value, CVOE, value, CVOPM value, CVOFM available (bit register locations X+08H, X+14H, X+18H X+1CH respectively.
RXTIP RXRING TXTIP TXRING
Framer Other Device
receive
RPRXTOSn RSIGLn/RGCOn LRCLKn RSYNCn LTCLKn TPOSn TSIGLn/TGCOn TSYNCn
T1Mx28
transmit
Note: channel number
Figure Byte-Synchronous Interface Framer Receive Data Signaling Highway Operation receive highway carries information from framer T1Mx28. highway sub-divided into time division multiplexed buses, data (RPOSn), signaling, frame alarms (RSIGLn). These buses synchronous with signals LRCLKn RSYNCn, 1.544 clock millisecond synchronization signal driven from framer T1Mx28 depending mode byte-synchronous operation. T1Mx28 operates modified byte-synchronous mode, receive clock synchronization inputs T1Mx28; T1Mx28 operates true byte-synchronous mode, receive clock synchronization outputs T1Mx28. data highway single-bit serial organized into 193bit groups called frames. Each frame consists spare position followed twenty-four 8-bit data samples representing DS0s. frames form multiframe, beginning which identified synchronization pulse, RSYNCn. RSYNCn high pulse occurs time before first frame multiframe every frames after that. signaling highway, RSIGLn, also divided into 193-bit frames. Each frame consists frame followed bits signaling alarm information data channels data highway. frame pattern tracks signaling pattern received from system. alarm bits signaling highway follow signaling bits. each frame bits, four signaling bits transmitted followed (Yellow) alarm position. positions coincident with through used
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T1Mx28 TXC-04228
alarm bit. Signaling bits through occur frame number one, followed through frame number two, ending with through frame number corresponding mode with 16-state signaling. two-state four-state signaling bits bits replaced bits bits respectively, shown following table. receive framing format signaling format shown Figures signaling information stored Signaling Store block mapping. alarm information (DS1 RAI-Yellow) stored Alarm Control block enabled generate automatically. Control SH2VAIS (bit register X+01H, when causes alarm bits signaling highway activate generation affected channel. When control YEL2RFI (bit register X+01H RAI-Yellow alarm signaling highway causes T1Mx28 mapper channel send byte. status these signaling highway alarm bits available SHDAIS SHYEL (bits register X+20H status only. When control AIS2VAIS (bit register X+01H T1Mx28 will cause generated condition defined above asynchronous mode operation detected. When control DATACOM (bit register X+00H RSIGLn input becomes RGCOn output, which gapped LRCLKn clock with LRCLKn cycle wide occurring frame time RPOSn every microseconds. Signaling positions RSIGLn TSIGLn Frame SF/ESF 16-St. RSIGL; S1-S4
F1/M1 S1/C1 F2/M2 S2/F1 F3/M3 S3/C2 F4/M4 S4/F2 F5/M5 S5/C3 F6/M6 S6/F3 F1/M7 S1/C4 F2/M8 S2/F4 F3/M9 S3/C5 F4/M10 S4/F5 F5/M11 S5/C6 F6/M12 S6/F6 A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23, C01, C02, C03, C05, C06, C07, C09, C10, C11, C13, C14, C15, C17, C18, C19, C21, C22, C23, D01, D02, D03, D05, D06, D07, D09, D10, D11, D13, D14, D15, D17, D18, D19, D21, D22, D23,
TSIGL; S1-S4
A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23, C01, C02, C03, C05, C06, C07, C09, C10, C11, C13, C14, C15, C17, C18, C19, C21, C22, C23, D01, D02, D03, D05, D06, D07, D09, D10, D11, D13, D14, D15, D17, D18, D19, D21, D22, D23,
4-State; S1-S4
A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, B01, B02, B03, B05, B06, B07, B09, B10, B11, B13, B14, B15, B17, B18, B19, B21, B22, B23,
2-State; S1-S4
A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23, A01, A02, A03, A05, A06, A07, A09, A10, A11, A13, A14, A15, A17, A18, A19, A21, A22, A23,
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DATA SHEET
RSYNCn frame frame frame frame
frame (193 bits)
LRCLKn
RPOSn
channel
bits channel
channel
channel
channel
RSIGLn
frame bit; AIS; RAI-Yellow alarm; signaling bits; assigned Figure System Interface Receive Framing Format
RSYNCn frame frame frame frame
RPOSn
first bits frame
first bits frame
first bits frame
first bits frame
first bits frame
LRCLKn
RSIGLn
Figure System Interface Receive Signaling Format
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Transmit Data Signaling Highway Operation
T1Mx28 TXC-04228
transmit highway carries information from T1Mx28 framer. highway sub-divided into time division multiplexed buses, data (TPOSn) signaling, frame bits alarms (TSIGLn). These buses synchronous with signal LTCLKn, 1.544 clock that driven from T1Mx28. data highway single bit-serial that organized into 193-bit groups called frames. Each frame consists frame followed twenty-four 8-bit data samples. Each 8-bit data samples represents single receive highway. 193-bit frames grouped into 24-frame multiframe. order help locate beginning frame extract signaling information, T1Mx28 sources synchronization signal, TSYNCn. byte-synchronous mode only; TSYNCn present standard compliant P1P0 pattern present VT1.5 TU-11 shown Figure TSYNCn high pulse occurs time before first frame multiframe every frames after that. signaling highway, TSIGLn, also divided into 193-bit frames organized identical fashion RSIGLn (see table above signaling assignments). alarm bits signaling highway follow signaling bits. each frame bits, four signaling bits transmitted followed (Yellow) alarm position. positions coincident with through used alarm bit. Signaling bits through occur frame number followed through frame number ending with through frame number corresponding mode with 16-state signaling. two-state four-state signaling bits bits replaced bits bits respectively, shown table above. Yellow alarm sourced T1Mx28 output same positions RSIGLn. These alarm bits used force Yellow automatically T1Fx8. Control VAIS2AIS (bit register X+01H, when causes detection VT-LOP bits TSIGLn unless control DATACOM (bit register X+00H Similarly, control bits SLM2AIS (bit UNE2AIS (bit register X+02H either Signal Label Mismatch Unequipped condition exists, bits signaling highway unless control DATACOM Setting control SDAISL (bit register X+03H will also bits TSIGLn unless control DATACOM Control SDAISL control bits VAIS2AIS, SLM2AIS UNE2AIS condition LOP/AIS, Signal Label Mismatch Unequipped occurs will cause all-ones signal generated TPOSn without regard control bits DATACOM MODE1. Likewise, Yellow alarm signaling highway control RFI2YEL (bit register X+01H alarm detected, control SYELL (bit register X+03H when control MODE1 (bit register X+00H indicating byte-synchronous operation DATACOM (bit same register indicating TSIGLn used gapped clock output. frame bits received from VT1.5/TU-11 available TSIGLn well; they track signaling bits used extraction. When control DATACOM (bit register X+00H TSIGLn output becomes TGCOn output, which gapped LTCLKn clock with LTCLKn cycle wide occurring frame time TPOSn every microseconds. System interface transmit framing format signaling format shown Figures
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DATA SHEET
TSYNCn frame frame frame frame
frame (193 bits)
LTCLKn
TPOSn
channel
bits channel
channel
channel
channel
TSIGLn
frame bit; AIS; Yellow alarm;
signaling bits;
assigned
Figure System Interface Transmit Framing Format
TSYNCn TPOSn frame frame frame frame
first bits frame
first bits frame
first bits frame
first bits frame
first bits frame
LTCLKn
TSIGLn
Figure System Interface Transmit Signaling Format Signaling Store Alarm Control blocks buffer signaling alarm information sent signaling highway. signaling bits output shown table above well Figure support certain protection schemes, leads ACSO BCSO when tied will cause transmit line interface leads (LTCLKn, TNEGn/TSIGLn/TGCOn, TPOSn, TSYNCn) driven logic low.
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Synchronizer, Mapper Overhead Generator
T1Mx28 TXC-04228
Synchronizer/Mapper block operates three different modes, programmable channel basis described above Line Interface Section. Synchronizer/Mapper heart mapping side device. synchronizes 1.544 Mb/s data stream SONET/SDH clock domain, maps data stream virtual tributary (VT1.5/TU-11) inserts order path overhead performance monitoring administrative purposes. Figure shows result synchronization, mapping overhead insertion functions form VT1.5/TU-11 asynchronous byte-synchronous mode. synchronization function adjusts approximately bits that they into VT1.5/TU-11 which microseconds long. signal, whether framed formats framed another format, generates bits every microseconds. shown Figure three opportunities provided bits plus bytes) opportunity bits used information), (one used information) bits (both bits used information) VT1.5/TU-11 asynchronous mode. stuffing control bits repeated twice provided every VT1.5/TU-11 indicate stuffing opportunity used information stuff; C1C1C1 indicates that used information C1C1C1 indicates that used stuff bit. treated likewise.This mechanism allows majority voting used desynchronizer, providing robust solution high error rates. T1Mx28 input buffer that written line clock read SONET/SDH clock. stuffing control T1Mx28 uses depth this input buffer value Buffer overflow/underflow fault condition input caused input frequency being outside stuffing range asynchronous mapping (approximately Hz). This condition will passed Microprocessor Interface alarm (Map Error). Status (bit register X+10H indicates Error status; mask MPM, latched event MPE, performance value MPPM hard fault value MPFM registers X+08H, X+14H, X+18H X+1CH respectively. stuffing mechanism T1Mx28 employs threshold modulation such that desynchronizer will meet GR-253-CORE category jitter requirements. This done using SRCLK vary input clock's phase every sequential VT1.5/TU-11 such that stuffing pattern varies frequency high enough filtered easily desynchronizer. This prevents clock that different from SONET/SDH derived 1.544 reference clock from generating jitter spikes when desynchronized. This feature turned testing purposes setting global control TMDISp (bit register 03DH Byte-synchronous mapping permits full signaling visibility shown Figure bytes every microseconds DS0s; stuffing mechanism replaced P1/P0 pattern that used identify different frame bits well which signaling bits being sent which what DS0s. Byte-synchronous mapping performs synchronization different ways. When LRCLKn RSYNCn outputs they derived from signal ALO(BLO), which must sourced from SONET/SDH payload timing (AACLK(BACLK), AASPE(BASPE) AAC1J1V1(BAC1J1V1)). such, exactly DS0s, frame four signaling bits mapped every microseconds. RSYNCn output defines start first superframes (the P1/P0 pattern goes from that form multiframe. source different clock than leads ALO(BLO), external slip buffer must provided; TranSwitch T1Fx8 (TXC-3108) provides this function. Since some applications want have added delay frames slip buffering (e.g. TR-496 Objective 3-6)), modified version byte-synchronous mapping provided where LRCLKn RSYNCn inputs floating VT1.5/TU-11 mode. tributary line side operates from input timing block, where data into block. system side operates Telecom SONET/SDH drop timing. line side clock multi-frame synchronization uses buffering supplied this block. input buffer becomes full synchronizer requests pointer decrement generated Termination block which aligns virtual container virtual tributary; this will cause extra byte data read input buffer microsecond period. Figure byte will skipped everything will shift byte. Likewise, input buffer empty synchronizer requests pointer increment causing position repeated less byte data will read input buffer microsecond period. Buffer overflow/underflow fault condition input caused loss frame
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synchronization control LOF2VAIS (bit register X+01H this mode. This condition will passed Microprocessor Interface alarm (Map Error). Status (bit register X+10H indicates Error status; mask MPM, latched event MPE, performance value MPPM hard fault value MPFM registers X+08H, X+14H, X+18H X+1CH respectively. RSYNCn input defines start first superframes (the P1/P0 pattern goes from 00), shown table below. Mapper takes output synchronizer adds overhead bits bytes positions driven with values stored registers X+36H (O-bits), X+37H byte), X+38H (Z6/N2 byte) X+39H (Z7/K4 byte). asynchronous operation only, eight O-bits bits included shown Figure byte-synchronous operation mapper also multiplexes into payload data from Signaling Store, which contains both ABCD signaling bits each also frame bits. Since signaling framing bits framed take milliseconds single superframe, 500-microsecond superframes required define P1/P0 bits byte-synchronous mapping coded identify signaling framing bits shown table below. Refer Figure signaling P1/P0 positions. signaling bits shown ESF; with four-state signaling CnDn bits AnBn bits repeated; two-state signaling AnBnCnDn becomes AnAnAnAn table below. Whether frame bits provided not, T1Mx28 calculate CRC-6 over DS0s only, inserting them positions table below control CRC6 (bit register X+01H TranSwitch T1Fx8 (TXC-03108) supports insertion specific ABCD signaling codes control operation signaling buffer write capability, optionally forces robbed positions support byte-synchronous GR-253-CORE signaling conditional requirements.
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T1Mx28 TXC-04228
Signaling Frame Assignments Byte-Synchronous Modes CRC1 FPS1 CRC2 FPS2 CRC3 FPS3 CRC4 FPS4 CRC5 FPS5 CRC6 FPS5 3.000 2.500 2.000 1.500 1.000 Time (ms) 0.125 0.250 0.375 0.500
Legend: signaling bits 16-state signaling format represent bits robbed from frames 4-state signaling interpreted 2-state signaling interpreted frame alignment bits signaling framing bits FPSn frame alignment bits; CRCn CRC-6 bits ESF; Facility Data Link bits ESF.
Pointer Generation Telecom Slot Selection T1Mx28 device only VT1.5/TU-11 termination provided. Termination block accepts data, alarms timing information from Synchronizer/Mapper block completes generation VT1.5/ TU-11 started Synchronizer/Mapper block.
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Each mapper VT1.5/TU-11 slots shown Figure Figure below. Control TBTVAL (bit register X+05H must VT1.5/TU-11 added Telecom Bus. Bits same register determine STS-1, TUG-3 number (one three). Bits this same register determine Group TUG-2 number (one seven) bits determine VT1.5 TU-11 number (one four). asynchronous operation fixed position generated (offset with valid next byte after shown Figure above. modified version byte-synchronous operation, synchronous payload envelope virtual container (VT-SPE/VC) moves accommodate frequency differences described above. Termination block provides pointer generation state machine that follows Bellcore, ANSI rules T1.105, GR-253-CORE G.709 generating more than single movement every four superframes (2.0 ms). Loss frame signal will cause start superframe position when signal recovers; this will force Data Flag (NDF) request Termination block. exiting synchronizer block will re-center buffer request NDF. synchronizer block will also look change expected position RSYNCn indicate request upstream. Valid bytes always generated. used stuff opportunity when pointer decrements done unused. true byte-synchronous operation fixed position results from fact that clock frame synchronization outputs which synchronous with SONET/SDH structure even though pointer generation state machine enabled. four-bit counters (one count increments generated count decrements generated) provided track frequency deviations. These counters located X+25H (bits increment bits decrement) with latched shadow values located same bits X+2DH. overflow either counter occurs, status PGOS (bit register X+10H interrupt generated; second polling/clearing this counter recommended. mask PGOM, latched event PGOE, performance value PGOPM hard fault value PGOFM registers X+08H, X+14H, X+18H X+1CH respectively. byte generated modes. formed from bit-interleaved parity calculation, signal label stored register X+07H bits 2-0, three alarm bits, REI-V, RFI-V RDI-V. that entire virtual container formed, BIP-2 bits calculated inserted byte shown Figure based previous VT-SPE/VC; chosen make bits every byte VT-SPE even parity second chosen make even bits every byte VT-SPE even. alarm bits mapped based results demapping, Line conditions Ring Port shown table below. When Ring Port enabled, only gets REI-V RDI-V from this port. RFI-V used byte-synchronous modes only comes from microprocessor-forced value result softwarebased failure detection (usually second range) persisting line, section high order path defect signaling highway result Yellow alarm.
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T1Mx28 TXC-04228
Generation Alarm Sources Controls Alarm BIP-2 Microproc. Force
SBIPE reg. X+03H, ECTL7p-ECTL0p reg. 01DH sets number times SFEBE reg. X+03H, ECTL7p-ECTL0p reg. 01DH sets number times SRFI reg. X+03H,
Demap Conditions
none
Line Conditions
none
Enable Controls
FEBEIS reg. X+02H, enables microproc. forcing. FEBEIS normal calculation. FEBEIS reg. X+02H, enables microproc. forcing. FEBEIS normal calculation. YEL2RFI reg. X+01H,
Ring
none
Ring Enable
none
REI-V
BIP-2 errors
none
REI-V
RINGEN reg. X+0BH,
RFI-V
Software integrated Yellow signaling failure state from highway; LOS, LOF, AIS-L/P/ Y-bit LOP-P/V, UNEQP/V, PLM-P/V AIS-V, LOP-V UNEQ-V none
none
none
RDI-V
SRDI-VSD reg. X+02H, SRDI-VCD reg. X+02H,
RDIIS RDI-VSD reg. X+02H, enables microproc. RDI-VCD forcing. RDIIS normal insertion from demap
RINGEN reg. X+0BH,
support three-bit RDI, byte also encoded based different demap conditions three-bit values supplied Ring Port. unused bits Z7/K4 supplied from Auxiliary Port internal register X+39H; Figure shows byte usage three-bit RDI. table below defines conditions that generate three-bit RDI. When alarms occur Demap side T1Mx28 supplied internally Ring Port, higher priority code always replaces lower priority code. Three-bit Generation Sources Controls Alarm Microproc. Force Demap Code Conditions bits
Priority
Enable Controls
Ring
Ring Enable
RDI-VSD SRDI-VSD AIS-V, LOP-V reg. X+02H, RDI-VCD SRDI-VCD reg. X+02H, RDI-VPD SRDI-VPD reg. X+02H, none
none UNEQ-V PLM-V defects
RDIIS RDI-VSD RINGEN reg. X+02H, reg. X+0BH, enables microproc. RDI-VCD forcing. RDIIS normal insertion from demap RDI-VPD
VT/TU Idle Insertion performed this point. Microprocessor Interface controls allow either valid with all-zeros payload generated idle all-zeros unequipped. Control IDLE (bit register X+00H, when powers down channel. Control bits RDIIS, FEBEIS, SBIPE,
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SFEBE, Transmit Signal Label, SRDI-VPD, SRDI-VSD, SRDI-VCD have effect idle signal sent. table below provides recommended settings idle unassigned (but still monitored) idle unequipped (not monitored). Idle Control T1Mx28 Control
IDLE; reg. X+00H, RDIIS; reg. X+02H, SRDI-VPD; reg. X+02H, SRDI-VSD; reg. X+02H, SRDI-VCD; reg. X+02H, FEBEIS; reg. X+02H, SFEBE; reg. X+03H, SBIPE; reg. X+03H, reg. X+39H, bits RINGEN Ring Port used); reg. X+0BH,
Valid Payload
Payload
Note: X=don't care
Control bits SH2VAIS, LOS2AIS, LOF2VAIS, AIS2VAIS, SDAISS SVTAIS, together with mapping mode control bits (MODE1, MODE0 DATACOM) line decoder controls (ENCOD EXPLOS) determine whether mapped. alarm bits signaling highway, Loss Frame modified byte-synchronous mode, microprocessor command, all-ones detected decoder, condition detected decoder condition signal LAIS lead used generate (DS1 payload all-ones will mapped place received signal) (payload, overhead plus bytes all-ones). table below details feature.
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T1Mx28 TXC-04228
VT-AIS Generation Sources Controls Alarm Generated Microproc. Force
SDAISS reg. X+03H,
DS1Line DATACOM MODE1 MODE0 Conditions reg. X+00H, reg. X+00H, reg. X+00H,
All-ones LAIS lead high
Enable Controls
none (passes through) none EXPLOS reg. X+00H, LOS2AIS reg. X+01H, ENCOD reg. X+00H, LOS2AIS reg. X+01H, none EXPLOS reg. X+00H, LOS2AIS reg. X+01H, SH2VAIS reg. X+01H, AIS2VAIS reg. X+01H, LOF2VAIS reg. X+01H,
detected
SVTAIS reg. X+03H, LAIS lead high
TSIGLn A-bits >99.9% ones detected decoder Loss signal RSYNCn
Note: X=don't care VT/TU Pointer Tracking Telecom Slot Selection T1Mx28 device only VT1.5/TU-11 termination provided. Termination block accepts data, high order alarms timing information from Telecom Interface block, tracks VT1.5/TU-11 pointer extracts alarms. Termination block also provides data, alarms control Desynchronizer/Demapper block. operations (pointer interpretation, pointer generation, VT/TU detection, VT/TU detection, etc.) performed accordance with GR-253-CORE, G.709, G.783. Each mapper drop VT1.5/TU-11 from slots shown Figure Figure below. Control TBRVAL (bit register X+04H must VT1.5/TU-11 dropped from Telecom Bus. Bits same register determine STS-1, TUG-3 number (one three). Bits t
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