FEATURES Upwards-Compatible with Sharp LH543611/21 Cycle Time fast 36-

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FEATURES Upwards-Compatible with Sharp LH543611/21 Cycle Time fast 36-

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LH54V3611/21
FEATURES Upwards-Compatible with Sharp LH543611/21 Cycle Time fast 36-bit FIFO Buffers (LH54V3611)
1024 36-bit FIFO Buffers (LH54V3621) Selectable 36/18/9-bit Word Width Port Selection Changed Without Reset Programmable Byte-Order Reversal `Big-Endian Little-Endian Conversion' Independent Clocks Both Ports Clock Enable Control Each Port Synchronous Request/Acknowledge `Handshake' Programmable Configuration Registers Enter Default State Following Reset Five Status Flags Port: Full, Almost-Full, Half-Full, Almost-Empty, Empty Flags Independently Programmable Either Synchronous Asynchronous Operation Almost-Full Flag Almost-Empty Flag Have Programmable Offsets Mailbox Registers with Synchronized Flags Data-Bypass Function Data-Retransmit Function LVTTL Interface Supply Space-Saving TQFP Package Individual FIFO FIFO Reset
1024 Synchronous Bidirectional FIFO
FIFO status flags monitor extent which each FIFO buffer been filled. Full, Almost-Full, Half-Full, Almost-Empty, Empty flags included each FIFO. Each these flags independently programmed either synchronous asynchronous interport operation. Almost-Full Almost-Empty flags programmable over entire FIFO depth. They automatically initialized eight locations from respective FIFO boundaries reset. Individual FIFO reset inputs retransmit inputs provide capability purging re-reading data from each individual FIFOs, without altering configuration. data block (LH54V3611) 1024 (LH54V3621) words retransmitted desired number times. mailbox registers provide separate path passing control words status words between ports. Each mailbox New-Mail-Alert Flag, which synchronized reading port's clock. This mailbox function facilitates synchronization data transfers between asynchronous systems. Data-bypass mode allows Port directly transfer data from Port reset. this mode, device acts registered transceiver under control Port instance, master processor Port data bypass feature send receive initialization configuration information directly, from peripheral device Port during system startup. word-width-select option provided Port 36-bit, 18-bit, 9-bit data access. This feature allows word-width matching between Port Port with additional logic needed. also ensures maximum utilization bandwidths. Subject meeting timing requirements, word-width selection changed fly. Byte Parity Check Flag each port monitors data integrity using either even parity. This initialized data parity reset. parity flags programmed operate either latched mode flowthrough mode. Bytewise parity checking performed over 36-bit full-words, over 18-bit half-words, over 9-bit single bytes. Parity generation selected well parity checking, likewise performed over full-words half-words single bytes. case, parity proper mode generated over least-significant eight bits each 9-bit byte, then stored most-significant position byte passes through LH54V3611/21, overwriting whatever present that position previously.
FUNCTIONAL DESCRIPTION
LH54V3611 LH54V3621 each contain FIFO buffers, FIFO FIFO These operate parallel, opposite directions, bidirectional data buffering. FIFO FIFO each organized 1024 bits. LH54V3611 LH54V3621 ideal either wide unidirectional applications bidirectional data applications; component count board area reduced. LH54V3511 LH54V3621 have 36-bit ports, Port Port Each port port-synchronous clock, ports operate asynchronously relative each other. Data flow initiated port rising edge appropriate clock; gated corresponding edge-sampled enable, request, read/write control signals. synchronous request/acknowledge handshake facility provided each port FIFO data access. This request/ acknowledge handshake resolves FIFO full empty boundary conditions, when ports operated asynchronously relative each other.
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CONNECTIONS
144-PIN TQFP
VSSO D23A D22A D21A D20A VSSO D19A D18A MBF2 ACKA REQA R/WA D17A D16A D15A VSSO D14A D13A D12A D11A VSSO
VIEW
VCCO D24A D25A D26A VSSO D27A D28A D29A VCCO D30A D31A D32A VSSO D33A D34A D35A VSSO D35B D34B VSSO D33B D32B D31B VCCO D30B D29B D28B VSSO D27B D26B D25B VCCO VCCO
VCCO VCCO D10A VSSO VCCO VSSO VSSO VSSO VCCO VSSO D10B D11B VCCO
VSSO D24B D23B D22B D21B VSSO D20B D19B D18B R/WB REQB ACKB MBF1 D17B D16B VSSO D15B D14B D13B D12B VSSO
54V3611-1
Figure Connections 144-Pin TQFP Package (Top View)
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LH54V3611/21
LIST
SIGNAL NAME TQFP SIGNAL NAME TQFP SIGNAL NAME TQFP
D17A D16A D15A D14A D13A D12A D11A D10A D10B D11B D12B D13B D14B D15B D16B D17B MBF1
NOTES: PINS
ACKB REQB R/WB D18B D19B D20B D21B D22B D23B D24B D25B D26B D27B D28B D29B D30B D31B D32B D33B D34B D35B D35A D34A D33A D32A D31A D30A D29A D28A D27A D26A D25A D24A D23A
D22A D21A D20A D19A D18A MBF2 ACKA REQA R/WA VSSO VSSO VCCO VCCO VSSO VCCO VSSO VSSO VSSO VCCO VSSO VCCO VSSO VSSO VSSO VSSO VCCO VCCO VSSO VCCO VSSO VSSO VSSO VCCO VSSO VCCO VSSO VSSO
COMMENTS
PINS
COMMENTS
VCCO
Supply internal logic. Connected each other. Supply output drivers only. Connected each other.
VSSO
Supply internal logic. Connected each other. Supply output drivers only. Connected each other.
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WRITE PORT
FIFO
READ PORT
READ
FIFO
WRITE
PORT CONTROL
PORT CONTROL
54V3611-2
Figure Simplified LH54V3611/21 Block Diagram
BYPASS RESET LOGIC MAILBOX REGISTER MBF1
MBF2 MAILBOX REGISTER
COMMAND PORT REGISTER
COMMAND PORT REGISTER
FIFO MEMORY ARRAY 1024 R/WA REQA ACKA FIXED PROGRAMMABLE STATUS FLAGS PORT SYNCHRONOUS CONTROL LOGIC PORT SYNCHRONOUS CONTROL LOGIC R/WB REQB ACKB
WRITE POINTER
READ POINTER
FIXED PROGRAMMABLE STATUS FLAGS
D35A
READ POINTER PORT
WRITE POINTER PORT
D35B WS0,
FIFO MEMORY ARRAY 1024 PARITY CHECKING GENERATION RESOURCE REGISTERS PARITY CHECKING GENERATION
54V3611-3
Figure Detailed LH54V3611/21 Block Diagram
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LH54V3611/21
DESCRIPTIONS
TYPE DESCRIPTION
GENERAL
VCC, VSS,VCCO, VSSO
Power, Ground Global Reset FIFO Reset FIFO Reset
PORT
R/WA A0A, A1A, REQA D35A MBF2 ACKA I/O/Z Port Free-Running Clock Port Edge-Sampled Read/Write Control Port Edge-Sampled Enable Port Edge-Sampled Address Pins Port Level-Sensitive Output Enable Port Request/Enable FIFO Retransmit Port Bidirectional Data FIFO Full Flag (Write Boundary) FIFO Programmable Almost-Full Flag (Write Boundary) FIFO Half-Full Flag FIFO Programmable Almost-Empty Flag (Read Boundary) FIFO Empty Flag (Read Boundary) New-Mail-Alert Flag Mailbox Port Parity Flag Port Acknowledge
PORT
R/WB WS0, REQB D35B MBF1 ACKB I/O/Z Port Free-Running Clock Port Edge-Sampled Read/Write Control Port Edge-Sampled Enable Port Edge-Sampled Address Port Level-Sensitive Output Enable Port Word-Width Select Port Request/Enable FIFO Retransmit Port Bidirectional Data FIFO Full Flag (Write Boundary) FIFO Programmable Almost-Full Flag (Write Boundary) FIFO Half-Full Flag FIFO Programmable Almost-Empty Flag (Read Boundary) FIFO Empty Flag (Read Boundary) New-Mail-Alert Flag Mailbox Port Parity Flag Port Acknowledge
NOTE: Input, Output, High-Impedance, Power Voltage Level
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ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING
Supply Voltage Potential Signal Voltage Potential Output Current
-0.5 -0.5 -65oC 150oC Watts
Storage Temperature Range Power Dissipation (Package Limit)
NOTES:
Stresses greater than those listed under `Absolute Maximum Ratings' cause permanent damage device. This stress rating transient conditions only. Functional operation device these other conditions outside those indicated `Operating Range' this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Outputs should shorted more than seconds. more than output should shorted time. Negative undershoot down -1.5 amplitude permitted more than once cycle.
OPERATING RANGE
SYMBOL PARAMETER UNIT
NOTE:
Temperature, Ambient Supply Voltage Supply Voltage Logic Input Voltage Logic HIGH Input Voltage
-0.5
Negative undershoot down -1.5 amplitude permitted more than once cycle.
ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)
SYMBOL PARAMETER TEST CONDITIONS UNIT
ICC2 ICC3 ICC4
Input Leakage Current Leakage Current Logic Output Voltage Logic HIGH Output Voltage Average Supply Current
MAX, VIH, VOUT -8.0 Measured Inputs VIHMIN (Clocks idle) Inputs (Clocks idle) Inputs (Clocks running MAX)
Average Standby Supply Current Power-Down Supply Current
Power-Down Supply Current
NOTES: ICC, ICC2, ICC3, ICC4 dependent upon actual output loading, ICC, ICC4 also dependent cycle rates. Specified values with outputs open (for ICC: pF); and, ICC4, operating minimum cycle times. (MAX) using `worst case' data pattern. (TYP) using `average' data pattern. ICC2 (TYP) ICC4 (TYP) using 25°C.
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LH54V3611/21
TEST CONDITIONS
PARAMETER RATING
Input Pulse Levels Input Rise Fall Times (10% 90%) Output Reference Levels Input Timing Reference Levels Output Load, Timing Tests
DEVICE UNDER TEST
Figure
NOTE: Includes scope capacitances
54V3611-5
Figure Output Load Circuit
CAPACITANCE
PARAMETER RATING
(Input Capacitance) COUT (Output Capacitance)
NOTES: Sample tested only. Capacitances maximum values 25oC, measured MHz, with
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ELECTRICAL CHARACTERISTICS (VCC 70°C)
SYMBOL DESCRIPTION UNITS
tRWS tRWH tRQS tRQH tWSS tWSH tACK tMBF tSPF tRSS tRSH tFRL tFWL tSKEW1 tSKEW2
NOTES:
Clock Cycle Frequency Clock Cycle Time Clock HIGH Time Clock Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Read/Write Setup Time Read/Write Hold Time Request Setup Time Request Hold Time Address Setup Time Address Hold Time Width Select Setup Time Width Select Hold Time Data Output Access Time Acknowledge Access Time Output Hold Time Output Enable Time, Low-Z Output Disable Time, HIGH High-Z Clock Flag Valid Clock Flag Valid Clock Flag Valid Clock Flag Valid Clock Flag Valid Clock Flag Valid Data Parity Flag Valid Clock Synchronous Parity Flag Valid4 Reset/Retransmit Pulse Width Reset/Retransmit Setup Time Reset/Retransmit Hold Time Resource change Flag Valid First Read Latency First Write Latency Bypass Data Setup Bypass Data Hold Bypass Data Access Skew Time Read-to-Write Clock Skew Time Write-to-Read Clock
66.7
14.5 14.5
28.5
Timing measurements performed Test Condition' levels. tAS, address setup times hold times need only satisfied clock edges which occur while corresponding enables being asserted. Values guaranteed design. Measured with Parity Flag operating bypass mode. When enabled; tRSS tRSH. tRSS and/or tRSH need unless rising edge occurs while being asserted, else rising edge occurs while being asserted. tFRL minimum first-write-to-first-read delay, following empty condition, which required assure valid read data. tFWL minimum first-read-to-first-write delay, following full condition, which required assure successful writing data.
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OPERATIONAL DESCRIPTION
Reset device reset whenever Global Reset (RS) input taken LOW, least rising edge falling edge both occur while LOW. reset operation required after power-up, before first write operation occur. LH54V3611/21 fully ready operation after being reset. device programming required default states described below acceptable. Global reset operation initializes read-address write-address pointers FIFO FIFO those FIFO's first physical memory locations. respective outputs enabled, initial contents these first locations appear outputs. FIFO mailbox status flags updated indicate empty condition. addition, programmable-status-flag offset values initialized eight. Thus, AE1/AE2 flags asserted within eight locations empty condition, AF1/AF2 flags likewise asserted within eight locations full condition, FIFO #1/FIFO respectively. FIFO FIFO reset individually through (FR1 FR2) FIFO reset signals. timing each FIFO reset signal same Global Reset Signal (RS) that least rising edge falling edge both required ensure Read Write pointers both reset their initial values, effectively flushing data from desired FIFO clearing corresponding mailbox flag. Configuration registers altered. Bypass Operation During global reset (whenever LOW) device acts registered transceiver, bypassing internal FIFO memories. Port acts master port. write read operation Port during reset transfers data directly from Port Port considered slave, device does respond Port controls. direction bypass data transmission determined R/WA control input. Here, `write' operation means passing data from Port Port `read' operation means passing data from Port Port bypass capability used pass initialization configuration data directly between master processor peripheral device during global reset. Port Addressing Address pins select device resource register accessed each port. Port three resource-select inputs, A0A, A1A, A2A, which select between FIFO data access, mailbox-register access, control-register access, programmable flag-offset-value-register access. Port single address input, A0B, select between FIFO data access mailbox-register access.The state resource-register-select inputs sampled rising edge enabled clock
(CKA CKB). Resource-register select-input address definitions summarized Table Control Register eighteen Control-Register bits govern synchronization mode fullness-status flags each port, choice even parity both ports, enabling parity generation data flow each port, optional latching behavior parity-error flags each port, selection full-word half-word single-byte field parity checking. global reset operation initializes LH54V3611/21 Control Register LH5420/LH543601-compatible operation, reprogrammed will time during LH54V3611/21 operation. Write Operation Port writes FIFO data, mail data, configuration resource registers. Port writes FIFO data, mailbox data. write operation initiated rising edge clock (CKA CKB) whenever: appropriate enable (ENA ENB) held HIGH; appropriate request (REQA REQB) held HIGH; appropriate Read/Write control (R/WA R/WB) held LOW; resource selected address inputs (A2A A0B); prescribed setup times hold times observed these signals. Setup times hold times must also observed data-bus pins (D0A D35A D35B). Normally, appropriate Output Enable signal (OEA OEB) HIGH, disable outputs that port, that data word present from external sources gets stored. However, `loopback' mode operation also possible, which data word supplied outputs internal FIFO `turned around' port read back into other FIFO. this mode, outputs port disabled. remain within Table Resource-Register Addresses
RESOURCE PORT
FIFO Data Mailbox Data AF2, AE2, AF1, Flag Offsets Register (36-Bit Mode) Control Register FlagSynchronization Parity Operating Mode Flag Offset Register Flag Offset Register Flag Offset Register Flag Offset Register
RESOURCE PORT
FIFO Data Mailbox Data
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OPERATIONAL DESCRIPTION (cont'd)
specification timing parameters, Clock Cycle Frequency must reduced slightly below value which otherwise would permissible that speed grade LH54V3611/21. When FIFO full condition reached, write operations locked out. Following first read operation from full FIFO, another memory location freed corresponding Full Flag deasserted HIGH). first write operation should begin earlier than First Write Latency (tFWL) after first read operation from full FIFO, ensure that correct read data retrieved. (See Figures 33.) Read Operation Port reads from FIFO data, mailbox data configuration resource registers. Port reads from FIFO data mailbox data. read operation initiated rising edge clock (CKA CKB) whenever: appropriate enable (ENA ENB) held HIGH; appropriate request (REQA held HIGH; appropriate Read/Write control (R/WA R/WB) held HIGH; FIFO resource selected address inputs (A2A A0B); prescribed setup times hold times observed these signals. Read data becomes valid data-bus pins (D0A D35A D35B) time after rising clock (CKA CKB) edge, provided that data outputs enabled. asserted-LOW, asynchronous, Output Enable control input signals. Their effect only enable disable output drivers respective port. Disabling outputs does disable read operation; data transmitted corresponding output register will remain available later, when outputs again enabled, unless subsequently overwritten. When empty condition reached, read operations locked until valid write operation(s) loaded additional data into FIFO. Following first write empty FIFO, corresponding empty flag (EF) will deasserted (HIGH). first read operation should begin earlier than First Read Latency (tFRL) after first write empty FIFO, ensure that correct read data words retrieved. (See Figures 31.) Dedicated FIFO Status Flags dedicated FIFO status flags included Full (FF1 FF2), Half-Full (HF1 HF2), Empty (EF1 EF2). FF1, HF1, indicate status FIFO FF2, HF2, indicate status FIFO Full Flag asserted following rising clock edge write operation which first fills FIFO. Full Flag deasserted following falling clock edge next read operation full FIFO. Half-Full Flag updated following rising clock edge read write operation FIFO which changes `half-full' status. Empty Flag asserted following rising clock edge
read operation which empties FIFO. Empty Flag deasserted following falling clock edge write operation empty FIFO. Programmable Status Flags Four programmable FIFO status flags provided, Almost-Full (AF1 AF2), AlmostEmpty (AE1 AE2). Thus, each port programmable flags monitor status internal FIFO buffer memories. offset values these flags initialized eight locations from respective FIFO boundaries during reset, reprogrammed over entire FIFO depth. Almost-Full Flag asserted following rising clock edge write operation which partially filled FIFO `almost-full' offset point. Almost-Full Flag deasserted following falling clock edge read operation which partially emptied FIFO down past `almost-full' offset point. Almost-Empty Flag asserted following rising clock edge read operation which partially emptied FIFO down `almost-empty' offset point. Almost-Empty Flag deasserted following falling clock edge write operation which partially filled FIFO past `almost-empty' offset point. Flag offsets stored register which altered examined through Port data bus. four programmable FIFO status flag offsets simultaneously through single 36-bit status word; each programmable flag offset individually, through four nine-bit (LH54V3611) ten-bit (LH54V3621) status words. Tables illustrate data format flag-programming words. Note that when four offsets simultaneously LH54V3621, settings limited magnitudes expressible nine positive integer; larger offset values, individual setting option must used. (See Table 3b.) Tables specify precise meaning each five flags. NOTE: Control inputs which affect computation flag values port generally should change while clock that port HIGH, since updating flag values deassertion takes place falling edge clock. Mailbox Operation mailbox registers provided passing system hardware software control/status words between ports. Each port read mailbox write other port's mailbox. Mailbox access performed rising edge controlling FIFO's clock, with mailbox address selected enable (ENA ENB) HIGH. That writing Mailbox Register reading from Mailbox Register synchronized CKA; writing MailboxRegister reading from Mailbox Register synchronized CKB.
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OPERATIONAL DESCRIPTION (cont'd)
R/WA/B OEA/B pins control direction mailbox-register accesses. Each mailbox register New-Mail-Alert Flag (MBF1 MBF2). Each fully synchronized reading port's clock. These NewMail-Alert Flags status indicators only, inhibit mailbox-register read write operations. MBF1 asserted after writing data into mailbox register deasserted reading mailbox register resetting FIFO using either FR1. Similarly, MBF2 asserted after writing data into mailbox register deasserted reading mailbox register resetting FIFO using either FR2. Request Acknowledge Handshake synchronous request-acknowledge handshake feature provided each port, perform boundary synchronization between asynchronously-operated ports. this feature optional. When used, Request input (REQA/B) sampled rising clock edge. With REQA/B HIGH, R/WA/B determines whether FIFO read operation FIFO write operation being requested. Acknowledge output (ACKA/B) updated during following clock cycle(s). ACKA/B meets setup hold time requirements Enable input (ENA ENB). Therefore, ACKA/B tied back enable input directly gate FIFO accesses, slight decrease maximum operating frequency. assertion ACKA/B signifies that REQA/B asserted that there sufficient data space FIFO requested write read operation succeed without over/under flow. However, ACKA/B does depend logically ENA/B; thus assertion ACKA/B does prove that FIFO write access FIFO read access actually took place. While REQA/B ENA/B being held HIGH, ACKA/B considered synchronous, predictive boundary flag. That ACKA/B acts synchronized predictor Almost-Full Flag write operations, synchronized predictor Almost-Empty Flag read operations. Within `almost-full' region `almost-empty' region, ACKA/B occurs only every third cycle, throttling back transfer rate FIFO prevent overrun FIFO's actual full empty boundaries ensure that tFWL (first write latency) tFRL (first read latency) specifications satisfied before ACKA/B received. write attempt unsuccessful because corresponding FIFO full, read attempt unsuccessful because corresponding FIFO empty, ACKA/B asserted response REQA/B. REQ/ACK handshake used, then REQA/B input used second enable input. this case, ACKA/B output ignored. Outside `almost-full' region `almost-empty' region, ACKA/B remains continuously HIGH whenever
REQA/B held continuously HIGH. `almost-full region' defined `that region, where Almost-Full Flag being asserted'; `almost-empty region' `that region, where Almost-Empty Flag being asserted.' Thus, extent these `almost' regions depends system programmed offset values Almost-Full Flags Almost-Empty Flags. system programmed them, then these offset values remain their default values, eight each case. NOTE: Whether REQ/ACK handshake being used, REQA/B input port must asserted that port function FIFO, mailbox, data- bypass operation. Data Retransmit retransmit operation resets read-address pointer corresponding FIFO back first FIFO physical memory location, that data reread. write pointer affected. status flags updated; block (LH54V3611) 1024 (LH54V3621) data words repeatedly retrieved. block retransmitted bounded first FIFO memory location, established during most recent global reset fifo reset, FIFO memory location addressed write pointer. FIFO retransmit initiated asserting FIFO retransmit initiated asserting Read write operations FIFO must stop while corresponding Retransmit signal being asserted. Parity Checking Parity Check Flags, PFB, asserted whenever there parity error data word present Port data Port data respectively. inputs parity-evaluation logic come directly from data-bus pins. Thus, provide parity-error indications whatever 36-bit words present Port Port respectively, regardless whether those words originated within LH54V3611/21 external system. parity each nine-bit byte individually checked. four single-byte parity indications logically ORed inverted produce Parity-Flag output. four bytes 36-bit data word grouped D17, D26, D35. Parity Policy (Control-Register HIGH, then parity Port will only computed over field defined Word-Width Selection control inputs WS1, which full-words, half-words, single bytes. Otherwise, parity will computed over full-words regardless setting WS1. Parity checking initialized parity reset, reprogrammed even parity during operation. Control-Register (zero) selects parity mode, even. (See Tables Figure
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nine bits each byte treated alike parity logic. byte parity over nine bits compared with Parity Mode Control Register, generate byte-parity-error indication. Then, four byte-parityerror signals NORed together, compute assertive-LOW parity-flag value. This value pass through output flowthrough basis, latched, according setting Control-Register latching that port (bit 11). (See Figure example parity checking.) Parity Generation Unlike parity checking, parity generation port operates only when explicitly invoked setting corresponding Control-Register that port (bit HIGH. presumed division words into bytes still remains same parity checking. However, longer true that nine bits each byte treated alike; now, most-significant each byte explicitly designated parity that byte. parity-generation process records value into that position each byte passing through port. (See Figure example parity generation.) Parity Policy (Control Register 09), HIGH, parity Port will generated full-words, halfwords, single bytes according setting Word-Width Selection control inputs WS1. Otherwise, parity will generated full-words regardless setting WS1. parity bits generated even odd, according setting Control-Register which same that governs their interpretation during parity checking. Word-Width Selection Byte-Order Reversal Port word width order data access Port selected control inputs. must HIGH 36-bit access; HIGH straightthrough transmission 36-bit words, on-thefly byte-order reversal four bytes word (`big-endian little-endian conversion'). (See Table 2b.) must funneling defunneling operations. this mode, transfer single 9-bit byte each cycle (single-byte access mode); HIGH transfer double-byte (18-bit word) each cycle. Single-byte double-byte FIFO write operations Port essentially pack `defunnel' data form 36-bit words, viewed from Port Similarly, single-byte
double-byte FIFO read operations Port essentially unpack `funnel' 36-bit words through series shift operations. Since values each status flag computed logic directly associated with FIFO-memory arrays, logic associated with Port flag values reflect array fullness situation terms complete 36-bit words, terms bytes double bytes. FIFO status flags updated following last access which forms complete 36-bit transfer. changed full-word boundaries during FIFO operation, without need reset operation, passing dummy words through advance real data. such change made other than full-word boundary, however, least dummy word should passed through port. However, there such restriction switching from writing reading, from reading writing, Port long tRWS, tDS, satisfied, R/WB change state after single-byte double-byte access, only after full 36-bit-word access. Width selection should repeated clock ticks whenever double-byte width selected, clock ticks whenever single-byte width selected, order remain aligned full-word boundaries. Otherwise, invalid word will assembled transition. word-width-matching feature continues operate properly `loopback' mode. Note that configurable word-width matching feature only supported FIFO accesses. Mailbox Data Bypass operations support word-width matching between Port Port Tables Figures summarize word-width selection Port Table Port Word-Width Selection
PORT DATA WIDTH
36-Bit 36-Bit with Byte-Order Reversal 18-Bit 9-Bit
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PARITY CHECKING
DA/B35 DA/B0
Output word: parity: Even parity:
100111100
000111100
100111000
000111000
Parity Bytes 0110; Byte Parity Error) Parity Bytes 1001; Byte Parity Error) PARITY GENERATION
DA/B35 DA/B0
Input word: Output, parity: Output, even parity:
100111100 100111100 000111100
000111100 100111100 000111100
100111000 000111000 100111000
000111000 000111000 100111000
Figure Example Parity Checking Generation
Table Funneling/Defunneling
PORT CYCLE DA[35:0] PORT CYCLE (HH) DB[35:0] (HL) DB[35:0] (LH) DB[35:18] DB[17:0] (LL) DB[35:9] DB[8:0]
NOTE: represent data bytes.
INPUT
BYTE BYTE
LH543611/21 DA35 DB35
OUTPUT: WS[1:0]= (HL)
BYTE BYTE
Example: Intel, DEC, etc.
DA27
BYTE BYTE
DB27 DB26
BYTE BYTE
DA26
DA18
BYTE BYTE
DB18 DB17
BYTE BYTE
DA17
BYTE BYTE
BYTE BYTE
54V3611-42
Figure Example 36-to-36 Byte Order Reversal
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PORT WORD-WIDTH SELECTION
36-Bit Data Stream D35A D18A Bits 18-35 (2nd Halfword) 18-Bit Data Streams D35B Halfword, then Halfword D18B
Bits 18-35 alfw
PORT
D17A Bits 0-17 (1st Halfword)
ord) Bits Halfw (1st
PORT
D17B
54V3611-6
Halfword, then Halfword
Figure 36-to-18 Funneling Through FIFO
36-Bit Data Stream D35A D27A Bits 27-35 (4th Byte)
9-Bit Data Streams D35B D27B Byte, then Byte, then Byte, then Byte
D26A D18A
Bits 18-26 (3rd Byte)
D26B D18B Byte, then Byte, then Byte, then Byte
PORT
D17A Bits 9-17 (2nd Byte) D17B
PORT
Byte, then Byte, then Byte, then Byte
Bits (1st Byte)
54V3611-7
Byte, then Byte, then Byte, then Byte
Figure 36-to-9 Funneling Through FIFO
NOTES: heavy black borders register segments indicate main data path, suitable most applications. Alternate paths feature different ordering bytes within word, Port funneling process does change ordering bits within byte. Halfwords (Figure bytes (Figure transferred parallel form from Port Port word-width setting changed during system operation; however, clock intervals should allowed these signals settle, before again attempting read D35B. Also, incomplete data words occur, when word width changed from shorter longer inappropriate point data block passing through FIFO.
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PORT WORD-WIDTH SELECTION
36-Bit Data Stream D35A D18A 18-Bit Data Stream D35B
Bits 18-35 alfw
D18B
PORT
D17A Bits 0-17 (1st Halfword) D17B
PORT
Halfword, then Halfword
54V3611-8
Figure 18-to-36 Defunneling Through FIFO
36-Bit Data Stream D35A D27A Bits 27-35 (4th Byte)
9-Bit Data Stream D35B D27B
D26A D18A Bits 18-26 (3rd Byte)
D26B
D18B
PORT
D17A Bits 9-17 (2nd Byte) D17B
PORT
Bits (1st Byte)
Byte, then Byte, then Byte, then Byte
54V3611-9
Figure 9-to-36 Defunneling Through FIFO
NOTES: heavy black borders register segments indicate only data paths used. other byte segments Port participate data path during defunneling. defunneling process does change ordering bits within byte. Halfwords (Figure bytes (Figure transferred parallel form from Port Port word-width setting changed during system operation; however, clock intervals should allowed these signals settle, before again attempting send data. Also, incomplete data words occur, when word width changed from shorter longer inappropriate point data block passing through FIFO.
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Table LH54V3611 Resource-Register Programming
RESOURCEREGISTER ADDRESS NORMAL FIFO OPERATION D35A
RESOURCE-REGISTER CONTENTS
MAILBOX D35A
AF2, AE2, AF1, FLAG REGISTER (36-BIT MODE) D35A D27A D26A D18A D17A
Offset
Offset
Offset
Offset
CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION D35A D18A D17A
Port Control
Port Control
9-BIT FLAG OFFSET REGISTER D35A
Offset
9-BIT FLAG OFFSET REGISTER D35A
Offset
9-BIT FLAG OFFSET REGISTER D35A
9-BIT FLAG OFFSET REGISTER D35A
Offset
NOTES:
Offset
four programmable-flag-offset values initialized eight during reset operation. Parity Mode: parity HIGH; even parity LOW. parity mode initialized during reset operation. Tables Figure detailed format Control Register word.
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LH54V3611/21
Table LH54V3621 Resource-Register Programming
RESOURCEREGISTER ADDRESS NORMAL FIFO OPERATION D35A
RESOURCE-REGISTER CONTENTS
MAILBOX D35A
AF2, AE2, AF1, FLAG REGISTER (36-BIT MODE)4 D35A D27A D26A D18A D17A
Offset
Offset
Offset
Offset
CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION D35A D18A D17A
Port Control
Port Control
10-BIT FLAG OFFSET REGISTER D35A D10A
Offset
10-BIT FLAG OFFSET REGISTER D35A D10A
Offset
10-BIT FLAG OFFSET REGISTER D35A D10A
10-BIT FLAG OFFSET REGISTER D35A
Offset
D10A
NOTES:
Offset
four programmable-flag-offset values initialized eight during reset operation. Parity Mode: parity HIGH; even parity LOW. parity mode initialized during reset operation. Tables Figure detailed format Control Register word. 36-bit Flag Register Control word, with only only bits program flag offset: Offset limited value 511. greater value desired, individual flag offset register programming required.
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Table LH54V3611 Flag Definition Table
VALID READ CYCLES REMAINING FLAG FLAG FLAG HIGH VALID WRITE CYCLES REMAINING FLAG FLAG HIGH
NOTE:
512-p
511-p
512-q
511-q
Programmable-Almost-Empty Offset value. (Default value: Programmable-Almost-Full Offset value. (Default value:
Table LH54V3621 Flag Definition Table
VALID READ CYCLES REMAINING FLAG FLAG FLAG HIGH VALID WRITE CYCLES REMAINING FLAG FLAG HIGH
NOTE:
1024 1024-p
1024 1024 1024
1023 1023-p 1024 1024
1024-q 1024
1024 1024
1024 1024 1024 1023-q 1023
Programmable-Almost-Empty Offset value. (Default value: Programmable-Almost-Full Offset value. (Default value:
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Advanced Information Table Control-Register Format
LH54V3611/21
CONTROL PORT REGISTER BITS
CODE
VALUE AFTER RESET
FLAG AFECTED,
DESCRIPTION
NOTES
PFA,
EVEN parity effect. parity effect. Disable Port parity generation. Enable Port parity generation. Port parity-error flag operates 'flowthrough.' Port parity-error flag latched CKA. CKA, reset CKB. reset CKA. CKA, reset CKB. reset CKA. CKA, reset CKB. reset CKB. reset CKA. CKA, reset CKB. reset CKA. CKA, reset CKB. reset CKA. Parity check computed over four bytes each word. Parity check computed over halfword single-byte according setting. Disable Port parity generation. Enable Port parity generation. Port parity-error flag operates 'flowthrough'. Port parity-error flag latched CKB. CKB, reset CKA. reset CKB. CKB, reset CKA. reset CKB. reset CKA. reset CKA. reset CKB.
correct 9-bit byte even number ones. correct 9-bit byte number ones. overwriting parity bits. Parity over eight least-significant bits each byte overwritten into mostsignificant that byte. subject transient glitches while data changing. remains steady until value should change. Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking Port clock. Synchronous flag clocking Port clock. Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking. Full-word parity-error indication regardless setting. Full-word, half word, single-byte parity-error indication according setting. overwriting parity bits. Parity over eight least-significant bits each byte overwritten into mostsignificant that byte. subject transient glitches while data changing. remains steady until value should change. Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking Port clock. Synchronous flag clocking Port clock.
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Table Control-Register Format (cont'd)
PORT CONTROL REGISTER BITS CODE VALUE FLAG AFTER AFFECTED, RESET DESCRIPTION NOTES
CKB, reset CKA. reset CKB. CKB, reset CKA. reset CKB.
Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking.
Table Controllable Functions
TYPE DESCRIPTION CONTROL-REGISTER PORT PORT
Even/Odd Parity Policy 9/18-Bit Word-Width Selection Generation: Enable/Disable Flag Behavior: Latched/Flowthrough Synchronous/Asynchronous Synchronous/Asynchronous Flag Synchronization Synchronous/Asynchronous Synchronous/Asynchronous
NOTE: LH5420/LH543601 also have this Control-Register function. same Control-Register bit, controls both Port Port functionality.
PARITY
LH5420/LH543601 CONTROL REGISTER (WRITE-ONLY) (FOR COMPARISON PURPOSES)
PORT FLAG SYNCHRONIZATION PARITY
PORT FLAG SYNCHRONIZATION PARITY
LH54V3611/21 CONTROL REGISTER (READ/WRITE)
54V3611-4
Figure LH5420/LH543601 LH54V3611/21 Control-Register Formats 2-445
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LH54V3611/21
TIMING DIAGRAMS
FR1,
tRQS tRQH tRQS tRQH
REQA
tRQS tRQH tRQS tRQH
REQB
(NOTE
(NOTE
NOTES: overrides other input signals, except R/WA, ENA, REQA. operates asynchronously. FR1, operate whether and/or asserted. least rising edge falling edge both must occur while FR1, being asserted LOW), with timing defined tRSS tRSH. Otherwise, tRSS, tRSH need unless rising edge and/or occurs while that clock enabled. parity-check even/odd selection (Control Register initialized byte parity reset (HIGH). other Control Register bits initialized LOW. alter configuration; flags reflect absence data. flag offsets initialized eight locations from boundary reset controlled HF1, AF1, FF1, MBF1 reset HIGH HF2, AF2, FF2, MBF2 reset HIGH
54V3611-10
Figure Reset Timing
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TIMING DIAGRAMS
tRWS tRWS
R/WA
tRQS tRQH
D35B
BYPASS
BYPASS DATA
D35A
PREVIOUS DATA
BYPASS
BYPASS
NOTES: tRSS, tRSH need unless rising edge occurs while that clock enabled. Port considered master port bypass operation. Thus, CKA, R/WA, ENA, REQA control transmission data between ports reset.
54V3611-11
Figure Data Bypass Timing
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LH54V3611/21
TIMING DIAGRAMS (cont'd)
READ FROM FIFO READ FROM FIFO WRITE FIFO
tRWS tRWS tRWS
R/WA
tRQS tRQH tRQS tRQH
REQA
PREVIOUS DATA
D35A ASYNCHRONOUS
DATA
DATA
DATA
VALID
VALID
VALID
VALID
tSPF SYNCHRONOUS
tSPF
tSPF
VALID
VALID
VALID
NOTES: Port Parity Error Flag (PFA) reflects parity status data present data bus, after delay tPF, when operated asynchronously. Port Parity Error Flag (PFA) reflects parity status data present data during previous clock cycle, meeting setup time CKA, when operated synchronously. does gate read write operations. left during write operation, then previous data held output latch written back into FIFO
54V3611-12
Figure Port FIFO Read/Write 2-448
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TIMING DIAGRAMS (cont'd)
READ FROM FIFO READ FROM FIFO WRITE FIFO
tRWS tRWH tRWS tRWS
R/WB
tRQS tRQH tRQS tRQH tRQS tRQH
REQB
PREVIOUS DATA
D35B ASYNCHRONOUS
DATA
DATA
DATA
VALID
VALID
VALID
VALID
tSPF SYNCHRONOUS
tSPF
tSPF
VALID
VALID
VALID
NOTES: Port Parity Error Flag (PFB) reflects parity status data present data bus, after delay tPF, when operated asynchronously. Port Parity Error Flag (PFB) reflects parity status data present data during previous clock cycle, meeting setup time CKB, when operated synchronously. does gate read write operations. left during write operation, then previous data held output latch written back into FIFO
54V3611-13
Figure Port FIFO Read/Write
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LH54V3611/21
TIMING DIAGRAMS (cont'd)
WRITE MAILBOX tRWS tRWS READ FROM MAILBOX
R/WA
tRQS tRQH tRQS tRQH
REQA
MBF2 MAXIMUM CYCLES LATENCY
MBF1
D35A
MAILBOX
MAILBOX
NOTES: Both edges MBF2 synchronized Port clock, CKA. Both edges MBF1 synchronized Port clock, CKB. There maximum clock cycles synchronization latency before MBF1 asserted indicate valid mailbox data. status mailbox flags does prevent mailbox read write operations.
54V3611-14
Figure Port Mailbox Access
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TIMING DIAGRAMS (cont'd)
WRITE MAILBOX tRWS tRWS READ FROM MAILBOX
R/WB
tRQS tRQH tRQS tRQH
REQB
MBF1 MAXIMUM CYCLES LATENCY
MBF2
D35B
MAILBOX
MAILBOX
NOTES: Both edges MBF2 synchronized Port clock, CKA. Both edges MBF1 synchronized Port clock, CKB. There maximum clock cycles synchronization latency before MBF2 asserted indicate valid mailbox data. status mailbox flags does prevent mailbox read write operations.
54V3611-15
Figure Port Mailbox Access
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LH54V3611/21
TIMING DIAGRAMS (cont'd)
LOAD RESOURCE REGISTER tRWS tRWS READ RESOURCE REGISTER
R/WA
tRQS tRQH tRQS tRQH
REQA
D35A
DATA
DATA
AE1, AE2, AF1, NOTES: valid flag address codes data formats, Table flag status altered flag programming, updated flags will valid within time tRF. Control Register loaded read back shown here, with A2A, A1A, HLL.
54V3611-16
Figure Resource Register Programming
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TIMING DIAGRAMS (cont'd)
(CKB tRWS
R/WA (R/WB
tRQS tRQH
REQA (REQB)
(EF1)
tRWS
R/WB (R/W
(ENA tRQS tRQH
REQB (REQA)
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Empty Flags controlled rising clock edges; whereas, deassertion Empty Flags controlled falling clock edges.
54V3611-17
Figure Empty Flag Timing, When Asynchronous
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TIMING DIAGRAMS (cont'd)
(CKB) tRWS
tRWH
R/WA (R/WB)
(ENB) tRQS tRQH
REQA (REQB) tSKEW2
(EF1)
(CKA) tRWS tRWH
R/WB (R/WA)
(ENA) tRQS tRQH
REQB (REQA) NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Empty Flags controlled rising clock edges; whereas, internal deassertion Empty Flags controlled falling clock edges, their external deassertion controlled rising clock edges. tSKEW2 minimum time between falling (CKA) edge rising (CKB) edge change predictably during current clock cycle. time between falling edge (CKA) rising edge (CKB) less than tSKEW2, then guaranteed that will change state until next following (CKB) edge.
54V3611-34
Figure Empty Flag Timing, When Synchronous
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TIMING DIAGRAMS (cont'd)
(CKB tRWS
R/WA (R/WB
(ENB
REQA (REQB
(AE1)
(CKA tRWS
R/WB (R/WA
(ENA
(REQA
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Almost-Empty Flags controlled rising clock edges; whereas, deassertion Almost-Empty Flags controlled falling clock edges.
54V3611-18
Figure Almost-Empty Flag Timing, When Asynchronous
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TIMING DIAGRAMS (cont'd)
(CKB) tRWS
tRWH
R/WA (R/WB)
(ENB) tRQS tRQH
REQA (REQB) tSKEW2
(AE1)
(CKA) tRWS tRWH
R/WB (R/WA)
(ENA) tRQS tRQH
REQB (REQA) NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Almost-Empty Flags controlled rising clock edges; whereas, internal deassertion Almost-Empty Flags controlled falling clock edges, their external deassertion controlled rising clock edges. tSKEW2 minimum time between falling (CKA) edge rising (CKB) edge change predictably during current clock cycle. time between falling edge (CKA) rising edge (CKB) less than tSKEW2, then guaranteed that will change state until next following (CKB) edge.
54V3611-35
Figure Almost-Empty Flag Timing, When Synchronous
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TIMING DIAGRAMS (cont'd)
(CKB tRWS
R/WA (R/WB
(ENB tRQS tRQH
REQA (REQB)
(FF2)
(CKA tRWS
R/WB (R/WA
(ENA tRQS tRQH
REQB (REQA) NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Full Flags controlled rising clock edges; whereas, deassertion Full Flags controlled falling clock edges.
54V3611-19
Figure Full Flag Timing, When Asynchronous
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TIMING DIAGRAMS (cont'd)
(CKB) tRWS
tRWH
R/WA (R/WB)
(ENB) tRQS tRQH
REQA (REQB) tSKEW1
(FF2)
(CKA) tRWS tRWH
R/WB (R/WA)
(ENA) tRQS tRQH
REQB (REQA) NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Full Flags controlled rising clock edges; whereas, internal deassertion Full Flags controlled falling clock edges, their external deassertion controlled rising clock edges. tSKEW1 minimum time between falling (CKA) edge rising (CKB) edge change predictably during current clock cycle. time between falling edge (CKA) rising edge (CKB) less than tSKEW1, then guaranteed that will change state until next following (CKB) edge.
54V3611-36
Figure Full Flag Timing, When Synchronous
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TIMING DIAGRAMS (cont'd)
(CKB tRWS
R/WA (R/WB
(ENB tRQS tRQH
REQA (REQB)
(AF2)
(CKA tRWS
R/WB (R/WA
(ENA tRQS tRQH
REQB (REQA)
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Almost-Full Flags controlled rising clock edges; whereas, deassertion Almost-Full Flags controlled falling clock edges.
54V3611-20
Figure Almost-Full Flag Timing, When Asynchronous
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TIMING DIAGRAMS (cont'd)
(CKB) tRWS
tRWH
R/WA (R/WB)
(ENB) tRQS tRQH
REQA (REQB) tSKEW1
(AF2)
(CKA) tRWS tRWH
R/WB (R/WA)
(ENA) tRQS tRQH
REQB (REQA)
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Assertion Almost-Full Flags controlled rising clock edges; whereas, internal deassertion Almost-Full Flags controlled falling clock edges, their external deassertion controlled rising clock edges. tSKEW1 minimum time between falling (CKA) edge rising (CKB) edge change predictably during current clock cycle. time between falling edge (CKA) rising edge (CKB) less than tSKEW1, then guaranteed that will change state until next following (CKB) edge.
54V3611-37
Figure Almost-Full Flag Timing, When Synchronous
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TIMING DIAGRAMS (cont'd)
(CKB tRWS
R/WA (R/WB
(ENB tRQS tRQH
REQA (REQB)
(HF2)
(CKA tRWS
R/WB (R/WA
(ENA tRQS tRQH
REQB (REQA) NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Both assertion deassertion Half-Full Flags controlled entirely rising clock edges, rather than falling clock edges.
54V3611-21
Figure Half-Full Flag Timing, When Asynchronous
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TIMING DIAGRAMS (cont'd)
(CKB) tRWS
tRWH
R/WA (R/WB)
(ENB) tRQS tRQH
REQA (REQB) tSKEW2
(HF1)
(CKA) tRWS tRWH
R/WB (R/WA)
(ENA) tRQS tRQH
REQB (REQA) NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Both assertion deassertion Half-Full Flags controlled entirely rising clock edges, rather than falling clock edges. tSKEW2 minimum time between rising (CKA) edge rising (CKB) edge change predictably during current clock cycle. time between rising edge (CKA) rising edge (CKB) less than tSKEW2, then guaranteed that will change state until next following (CKB) edge.
54V3611-38
Figure Half-Full Flag Timing, When Synchronized Port Clock Doing Reading
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TIMING DIAGRAMS (cont'd)
(CKB) tRWS
tRWH
R/WA (R/WB)
(ENB) tRQS tRQH
REQA (REQB) tSKEW1
(HF2)
(CKA) tRWS tRWH
R/WB (R/WA)
(ENA) tRQS tRQH
REQB (REQA)
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation. Both assertion deassertion Half-Full Flags controlled entirely rising clock edges, rather than falling clock edges. tSKEW1 minimum time between rising (CKA) edge rising (CKB) edge change predictably during current clock cycle. time between rising edge (CKA) rising edge (CKB) less than tSKEW1, then guaranteed that will change state until next following (CKB) edge.
54V3611-39
Figure Half-Full Flag Timing, When Synchronized Port Clock Doing Writing
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TIMING DIAGRAMS (cont'd)
tRWS
R/WA
tRQS tRQH tRQS tRQH tRQS
REQA
tRWS
R/WB
tRQS tRQH tRQS tRQH tRQS
REQB NOTES: tRSS tRSH need unless rising edge occurs while that clock enabled. tRSS time needed deassert before returning normal FIFO cycle. tRSH time needed before asserting after normal FIFO cycle. Read write operations FIFO should disabled while being asserted. During retransmit,WS1 must stable throughout entire clock cycle.
54V3611-22
Figure FIFO Retransmit
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TIMING DIAGRAMS (cont'd)
tRWS
R/WB
tRQS tRQH tRQS tRQH tRQS
REQB tRSS
tRWS
R/WA
tRQS tRQH tRQS tRQH tRQS
REQA NOTES: tRSS tRSH need unless rising edge occurs while that clock enabled. tRSS time needed deassert before returning normal FIFO cycle. tRSH time needed before asserting after normal FIFO cycle. Read write operations FIFO should disabled while being asserted. During retransmit, must stable throughout entire clock cycle.
54V3611-23
Figure FIFO Retransmit
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TIMING DIAGRAMS (cont'd)
tRWS tRWS
R/WA
tRQH tRQS tRQH tRQS
REQA D35A
tRWS tRWS
tRQH tRQS tRQH tRQS
REQB
D35B
PREVIOUS DATA
NOTES: A2A, A1A, A0A, held HIGH FIFO access. held HIGH. held LOW. tFRL (First Read Latency) first read following empty condition begin earlier than tFRL after first write empty FIFO, ensure that valid read data retrieved.
54V3611-24
Figure FIFO Write Read Operation Near-Empty Region 2-466
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TIMING DIAGRAMS (cont'd)
tRWS R/WB tRWS
tRQH tRQS REQB D35B
tRQH tRQS
tRWS tRQH tRQS tRQH tRQS
REQA D35A
PREVIOUS DATA
NOTES: A2A, A1A, A0A, held HIGH FIFO access. held HIGH. held LOW. tFRL (First Read Latency) first read following empty condition begin earlier than tFRL after first write empty FIFO, ensure that valid read data retrieved.
54V3611-25
Figure FIFO Write Read Operation Near-Empty Region
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TIMING DIAGRAMS (cont'd)
tRWS tRWS
R/WA
tRQH tRQS tRQH tRQS
REQA
D35A
tRWS tRWS
tRQH tRQS tRQH tRQS
REQB
D35B
PREVIOUS DATA
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port held HIGH. held LOW. tFWL (First Write Latency) first write following full condition begin earlier than tFWL after first read from full FIFO, ensure that valid write data written.
54V3611-26
Figure FIFO Read Write Operation Near-Full Region
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TIMING DIAGRAMS (cont'd)
tRWS tRWS
R/WB
tRQH tRQS tRQH tRQS
REQB D35B
tRWS tRWS
tRQH tRQS tRQH tRQS
REQA
D35A
PREVIOUS DATA
NOTES: A2A, A1A, held HIGH FIFO access Port held HIGH FIFO access Port held HIGH. held LOW. tFWL (First Write Latency) first write following full condition begin earlier than tFWL after first read from full FIFO, ensure that valid write data written.
54V3611-27
Figure FIFO Read Write Operation Near-Full Region
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LH54V3611/21
TIMING DIAGRAMS (cont'd)
tRWS
R/WB
D17B
BITS 0-17
BITS 18-35
BITS 0-17
BITS 18-35
BITS 0-17
WORD D18B D35B
BITS 18-35
WORD
BITS 0-17 BITS 18-35
WORD
BITS 0-17 BITS 18-35
WORD NOTES: held HIGH FIFO access. held LOW. held HIGH held double-byte access. Data-access time after rising edge CKB, shown first read cycle, applies similarly subsequent read cycles.
WORD
WORD
54V3611-28
Figure Port Double-Byte FIFO Read Access 36-to-18 Funneling
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TIMING DIAGRAMS (cont'd)
tRWS
R/WB
D17B
BITS 0-17
BITS 18-35
BITS 0-17
BITS 18-35
BITS 0-17
BITS 18-35
WORD
WORD
WORD
NOTES: held HIGH FIFO access. held HIGH. held HIGH held double-byte access. Data-setup time data-hold time tDH, before after rising edge CKB, shown first write cycle, apply similarly subsequent write cycles.
54V3611-29
Figure Port Double-Byte FIFO Write Access 18-to-36 Defunneling
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TIMING DIAGRAMS (cont'd)
tRWS
R/WB
BITS
BITS 9-17
BITS 18-26
BITS 27-35
BITS
WORD D17B
BITS 9-17 BITS 18-26 BITS 27-35
WORD
BITS BITS 9-17
WORD D18B D26B
BITS 18-26 BITS 27-35 BITS
WORD
BITS 9-17 BITS 18-26
WORD D27B D35B
BITS 27-35 BITS BITS 9-17
WORD
BITS 18-26 BITS 27-35
WORD NOTES: held HIGH FIFO access. held LOW. both held single-byte access. Data-access time after rising edge CKB, shown first read cycle, applies similarly subsequent read cycles.
WORD
54V3611-30
Figure Port Single-Byte FIFO Read Access 36-to-9 Funneling
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TIMING DIAGRAMS (cont'd)
tRWS
R/WB
BITS
BITS 9-17
BITS 18-26
BITS 27-35
BITS
BITS 9-17
WORD NOTES: held HIGH FIFO access. held HIGH. both held single-byte access. Data-setup time data-hold time tDH, before after rising edge CKB, shown first write cycle, apply similarly subsequent write cycles.
WORD
54V3611-31
Figure Port Single-Byte FIFO Write Access 9-to-36 Defunneling
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TIMING DIAGRAMS (cont'd)
Outside 'almost-full' region, acknowledge continuous continuous request. Starting third cycle after entering 'almost-full' region, acknowledge occurs every third cycle prevent overrun full condition.
(CKB tRWS
R/WA (R/WB
(REQB
(ACKB
(AF2) NOTES: FIFO access occur, must held HIGH required setup hold times. tied directly directly gate FIFO accesses. Indicates where write would take place, were tied must maintained HIGH with stable throughout entire clock cycle generated. When REQ/ACK handshake used, ignored, tied HIGH used second enable. Parameters without parentheses apply Port Parameters with parentheses apply Port
54V3611-32
Figure Write Request/Acknowledge Handshake
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TIMING DIAGRAMS (cont'd)
Outside 'almost-empty' region, acknowledge continuous continuous request. Starting third cycle after entering 'almost-empty' region, acknowledge occurs every third cycle prevent underrun empty condition.
(CKB tRWS
R/WA (R/WB
(REQB
(ACKB
(AE1) NOTES: FIFO access occur, must held HIGH required setup hold times. tied directly directly gate FIFO accesses. Indicates where read would take place, were tied must maintained HIGH with stable throughout entire clock cycle generated. When REQ/ACK handshake used, ignored, tied HIGH used second enable. Parameters without parentheses apply Port Parameters with parentheses apply Port
54V3611-33
Figure Read Request/Acknowledge Handshake
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TIMING DIAGRAMS (cont'd)
WIDTH SELECTED WIDTH BYTE-REVERSE
WIDTH
tRWS
R/WB
tRQS
REQB tWSS tWSH tWSS tWSH
tSPF
(SYNCHRONOUS LATCHING)
D35B
(WHEN DATA WORDS INCOMING)
(ASYNCHRONOUS, WHEN DATA WORDS INCOMING)
D35B
(WHEN DATA WORDS OUTGOING)
(ASYNCHRONOUS, WHEN DATA WORDS OUTGOING)
NOTE: During retransmit, must stable throughout entire clock cycle.
54V3611-40
Figure Parity Checking Changing Port Word-Width Selection During Operation
2-476
LH54V3611/21
Advanced Information
2/1024 BiFIFOs
TIMING DIAGRAMS (cont'd)
WIDTH SELECTED WIDTH
tRWS
R/WB
tRQS
REQB tWSS tWSH tWSS tWSH
tSPF
(SYNCHRONOUS LATCHING)
(WHEN DATA WORDS INCOMING)
D35B
(ASYNCHRONOUS, WHEN DATA WORDS INCOMING)
D35B
(WHEN DATA WORDS OUTGOING)
(ASYNCHRONOUS, WHEN DATA WORDS OUTGOING)
NOTE: During parity mode changes (odd even), TSPF have additional delay from rising edge clock.
54V3611-41
Figure Parity Checking Changing Port Word-Width Selection (Continued)
2-477
2/1024 BiFIFOs
Advanced Information
LH54V3611/21
PACKAGE DIAGRAM
144TQFP (TQFP-144-P-2020)
0.50 [0.020] TYP. 0.27 [0.010] 0.17 [0.007] 0.20 [0.008] 0.09 [0.004]
20.0 [0.787] BASIC
22.0 [0.866] BASIC
20.0 [0.787] BASIC 22.0 [0.866] BASIC 1.45 [0.057] 1.35 [0.053]
DETAIL
1.60 [0.063] REF. 0.15 [0.006] 0.05 [0.002] 0.75 [0.030] 0.47 [0.019] 1.00 [0.039] REF.
DIMENSIONS [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
144TQFP
144-pin TQFP
2-478
LH54V3611/21
Advanced Information
2/1024 BiFIFOs
ORDERING INFORMATION
LH54V3611/21 Device Type Package Speed Cycle Times (ns) 144-pin, Thin Quad Flat Package (TQFP144-P-2020) 2/1K Bidirectional FIFO Example: LH54V3611M-15 (512 Bidirectional FIFO, 144-pin, Thin Quad Flat Package)
54V3611-43
2-479

FEATURES Upwards-Compatible with Sharp LH543611/21 Cycle Time fast 36-

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