8/16-BIT FAMILY WITH ROM/OTP/EPROM Register File based 8/16 Core
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ST90158 ST90135
8/16-BIT FAMILY WITH ROM/OTP/EPROM
Register File based 8/16 Core Architecture with RUN, WFI, SLOW HALT modes Operation 5V±10%, -40°C +85°C +70°C Operating Temperature Ranges Operation 3V±10% +70°C Operating Temperature Range Fully Programmable Clock Generator, with Frequency Multiplication frequency, cost external crystal Minimum 8-bit Instruction Cycle time: 83ns internal clock frequency) Minimum 16-bit Instruction Cycle time: 250ns internal clock frequency) Internal Memory: EPROM/OTP/ROM 16/24/32/48/64K bytes ROMless version available 512/768/1K/1.5K/2K bytes Maximum External Memory: bytes general purpose registers available RAM, accumulators index pointers (register file) 80-pin Plastic Quad Flat Package 80-pin Thin Quad Flat Package fully programmable bits external Non-Maskable Interrupts Controller Programmable Interrupt Handler Single Master Serial Peripheral Interface 16-bit Timers with 8-bit Prescaler, usable Watchdog Timer (software hardware) Three (ST90158) (ST90135) 16-bit Multifunction Timers, each with prescaler, operating modes capabilities channel 8-bit Analog Digital Converter, with Automatic voltage monitoring capabilities external reference inputs (ST90158) (ST90135) Serial Communication Interfaces with asynchronous, synchronous capabilities Rich Instruction with Addressing modes Division-by-Zero trap generation
TQFP80
PQFP80 Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger Hardware Emulators with Real-Time Operating System available from Third Parties DEVICE SUMMARY
DEVICE
Program Memory PACKAGE (Bytes) (Bytes) 1.5K PQFP80/ TQFP80 CQFP80 CQFP80 PQFP80 PQFP80/ TQFP80/ PQFP80/ TQFP80 PQFP80
ST90135
ST90158 ST90E158
EPROM ST90E158LV EPROM ST90T158 ST90T158LV ST90R158 ROMleRev.
January 2000 1/190
Table Content1 GENERAL DESCRIPTION INTRODUCTION 1.1.1 ST9+ Core 1.1.2 Power Saving Modes 1.1.3 system Clock 1.1.4 Ports 1.1.5 Multifunction Timers (MFT) 1.1.6 Standard Timer (STIM) 1.1.7 Watchdog Timer (WDT) 1.1.8 Serial Peripheral Interface (SPI) 1.1.9 Serial Communications Controllers (SCI) 1.1.10 Analog/Digital Converter (ADC) DESCRIPTION PORT PINS DEVICE ARCHITECTURE CORE ARCHITECTURE MEMORY SPACES 2.2.1 Register File 2.2.2 Register Addressing SYSTEM REGISTERS 2.3.1 Central Interrupt Control Register 2.3.2 Flag Register 2.3.3 Register Pointing Techniques 2.3.4 Paged Registers 2.3.5 Mode Register 2.3.6 Stack Pointers MEMORY ORGANIZATION MEMORY MANAGEMENT UNIT ADDRESS SPACE EXTENSION 2.6.1 Addressing 16-Kbyte Pages 2.6.2 Addressing 64-Kbyte Segments REGISTERS 2.7.1 DPR[3:0]: Data Page Registers 2.7.2 CSR: Code Segment Register 2.7.3 ISR: Interrupt Segment Register 2.7.4 DMASR: Segment Register USAGE 2.8.1 Normal Program Execution 2.8.2 Interrupts 2.8.3 REGISTER MEMORY MEMORY CONFIGURATION EPROM PROGRAMMING MEMORY ST90158/135 REGISTER INTERRUPTS INTRODUCTION INTERRUPT VECTORING
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Table Content4.2.1 Divide Zero trap 4.2.2 Segment Paging During Interrupt Routines INTERRUPT PRIORITY LEVELS PRIORITY LEVEL ARBITRATION 4.4.1 Priority level (Lowest) 4.4.2 Maximum depth nesting 4.4.3 Simultaneous Interrupts 4.4.4 Dynamic Priority Level Modification ARBITRATION MODES 4.5.1 Concurrent Mode 4.5.2 Nested Mode EXTERNAL INTERRUPTS LEVEL INTERRUPT ON-CHIP PERIPHERAL INTERRUPTS INTERRUPT RESPONSE TIME 4.10 INTERRUPT REGISTERS ON-CHIP DIRECT MEMORY ACCESS (DMA) INTRODUCTION PRIORITY LEVELS TRANSACTIONS CYCLE TIME SWAP MODE REGISTERS RESET CLOCK CONTROL UNIT (RCCU) INTRODUCTION CLOCK CONTROL UNIT 6.2.1 Clock Control Unit Overview CLOCK MANAGEMENT 6.3.1 Clock Multiplier Programming 6.3.2 Clock Prescaling 6.3.3 Peripheral Clock 6.3.4 Power Modes 6.3.5 Interrupt Generation CLOCK CONTROL REGISTERS OSCILLATOR CHARACTERISTICS RESET/STOP MANAGER 6.6.1 RESET Timing EXTERNAL STOP MODE EXTERNAL MEMORY INTERFACE (EXTMI) INTRODUCTION EXTERNAL MEMORY SIGNALS 7.2.1 Address Strobe 7.2.2 Data Strobe 7.2.3 DS2: Data Strobe 7.2.4 Read/Write 7.2.5 BREQ, BACK: Request, Acknowledge 7.2.6 PORT
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Table Content7.2.7 PORT 7.2.8 WAIT: External Memory Wait REGISTER DESCRIPTION PORTS INTRODUCTION SPECIFIC PORT CONFIGURATIONS PORT CONTROL REGISTERS INPUT/OUTPUT CONFIGURATION ALTERNATE FUNCTION ARCHITECTURE 8.5.1 Declared 8.5.2 Declared Alternate Input 8.5.3 Declared Alternate Function Output STATUS AFTER WFI, HALT RESET ON-CHIP PERIPHERALS TIMER/WATCHDOG (WDT) 9.1.1 Introduction 9.1.2 Functional Description 9.1.3 Watchdog Timer Operation 9.1.4 Interrupts 9.1.5 Register Description MULTIFUNCTION TIMER (MFT) 9.2.1 Introduction 9.2.2 Functional Description 9.2.3 Input Assignment 9.2.4 Output Assignment 9.2.5 Interrupt 9.2.6 Register Description STANDARD TIMER (STIM) 9.3.1 Introduction 9.3.2 Functional Description 9.3.3 Interrupt Selection 9.3.4 Register Mapping 9.3.5 Register Description SERIAL PERIPHERAL INTERFACE (SPI) 9.4.1 Introduction 9.4.2 Device-Specific Options 9.4.3 Functional Description 9.4.4 Interrupt Structure 9.4.5 Working With Other Protocols 9.4.6 I2C-bus Interface 9.4.7 S-Bus Interface 9.4.8 IM-bus Interface 9.4.9 Register Description SERIAL COMMUNICATIONS INTERFACE (SCI) 9.5.1 Introduction 9.5.2 Functional Description 9.5.3 Operating Modes 9.5.4 Serial Frame Format
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Table Content9.5.5 Clocks Serial Transmission Rates 9.5.6 Initialization Procedure 9.5.7 Input Signals 9.5.8 Output Signals 9.5.9 Interrupts 9.5.10 Register Description EIGHT-CHANNEL ANALOG DIGITAL CONVERTER (A/D) 9.6.1 Introduction 9.6.2 Functional Description 9.6.3 Interrupts 9.6.4 Register Description ELECTRICAL CHARACTERISTICS GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA 11.2 80-PIN PLASTIC QUAD FLAT PACKAGE 11.3 ORDERING INFORMATION
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ST90158 GENERAL DESCRIPTION
GENERAL DESCRIPTION
INTRODUCTION ST90158 ST90135 microcontrollers developed manufactured STMicroelectronics using proprietary n-well CMOS process. Their performance derives from flexible 256-register programming model ultra-fast context switching real-time event response. intelligent on-chip peripherals offload core from data management processing tasks allowing critical application tasks maximum core resources. new-generation devices also support power consumption voltage operation power-efficient low-cost embedded systems. 1.1.1 ST9+ Core advanced Core consists Central Processing Unit (CPU), Register File, Interrupt controller, Memory Management Unit. allows addressing Megabytes program data mapped into single linear space. Four independent buses controlled Core: 16-bit memory bus, 8-bit register data bus, 8-bit register address 6-bit interrupt/DMA which connects interrupt controllers on-chip peripherals with core. This multiple architecture makes family devices highly efficient accessing offchip memory fast exchange data with on-chip peripherals. general-purpose registers used accumulators, index registers, address pointers. Adjacent register pairs make 16-bit registers addressing 16-bit processing. Although 8-bit ALU, chip handles 16-bit operations, including arithmetic, loads/stores, memory/register memory/memory exchanges. 1.1.2 Power Saving Modes optimize performance versus power consumption, range operating modes dynamically selected. Mode. This full speed execution mode with peripherals running maximum clock speed delivered Phase Locked Loop (PLL) Clock Control Unit (CCU). Slow Mode. Power consumption significantly reduced running peripherals reduced clock speed using Prescaler Clock Divider (PLL used) using CK_AF external clock. Wait Interrupt Mode. Wait Interrupt (WFI) instruction suspends program execution until interrupt request acknowledged. During WFI, clock halted while peripheral interrupt controller keep running frequency programmable CCU. this mode, power consumption device reduced more than (Low Power WFI). Halt Mode. When executing HALT instruction, Watchdog enabled, peripherals stop operating status machine remains frozen (the clock also stopped). reset necessary exit from Halt mode. 1.1.3 system Clock programmable Clock Generator allows standard crystals used obtain large range internal frequencies MHz. 1.1.4 Ports lines grouped into nine 8-bit Ports configured basis provide timing, status signals, address/data interfacing external memory, timer inputs outputs, analog inputs, external interrupts serial parallel I/O.
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ST90158 GENERAL DESCRIPTION
1.1.5 Multifunction Timers (MFT) Each multifunction timer 16-bit Up/Down counter supported 16-bit Compare registers 16-bit input capture registers. Timing resolution programmed using 8-bit prescaler. Multibyte transfers between peripheral memory supported channels. 1.1.6 Standard Timer (STIM) Standard Timer includes programmable 16bit down counter associated 8-bit prescaler with Single Continuous counting modes. 1.1.7 Watchdog Timer (WDT) Watchdog timer used monitor system integrity. When enabled, generates reset after timeout period unless counter refreshed application software. additional
security, watchdog function enabled hardware using specific pin. 1.1.8 Serial Peripheral Interface (SPI) used communicate with external devices SPI, communication standards. uses lines serial data synchronous clock signal. 1.1.9 Serial Communications Controllers (SCI) Each provides synchronous asynchronous serial port using channels. Baud rates data formats programmable. 1.1.10 Analog/Digital Converter (ADC) ADCs provide analog inputs with onchip sample hold. analog watchdog generates interrupt when input voltage moves preset threshold.
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ST90158 GENERAL DESCRIPTION
Figure ST90158 Block Diagram
ADDRESS DATA
Port0 EPROM/ ROM/OT Kbyte
P0[7:0]
ADDRE
Port1
P1[7:0] P0[7:0] P1[7:0] P2[6:0] P4[7:0] P5[7:3], P5.1 P6[6:0] P7[7:0] P8[7:0] P9[7:4], P9[2:0]
KbyteFully Prog.
bytes Register File 8/16 bits Interrupt Management ST9+ CORE
MEMORY
WAIT
STIM
STOUT
INT0-7
OSCIN OSCOUT RESET INTCLK CKAF
I2C/IM
RCCU REGISTER Converter with analog watchdog
WDIN WDOUT HW0SW1 T0OUTA T0OUTB T0INA T0INB T1OUTA T1OUTB T1INA T1INB T3OUTA T3OUTB T3INA T3INB
EXTRG AIN[7:0] TX0CKIN RX0CKIN S0IN DCD0 S0OUT CLK0OUT RTS0 TX1CKIN RX1CKIN S1IN DCD1 S1OUT CLK1OUT RTS1
WATCHDOG
MFT0
SCI0
MFT1 SCI1 MFT3
alternate functions (Italic characters) mapped Port2 through Port9
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ST90158 GENERAL DESCRIPTION
Figure ST90135 Block Diagram
ADDRESS DATA
Kbyte
Port0
P0[7:0]
ADDRESS
Port1 Kbyte
Fully Prog.
P1[7:0] P0[7:0] P1[7:0] P2[6:0] P4[7:0] P5[7:3], P5.1 P6[6:0] P7[7:0] P8[7:0] P9[7:4], P9[2:0]
bytes Register File 8/16 bits Interrupt Management ST9+ CORE
MEMORY
WAIT
STIM
STOUT
INT0-7
OSCIN OSCOUT RESET INTCLK CKAF
I2C/IM
RCCU REGISTER Converter with analog watchdog SCI0
WDIN WDOUT HW0SW1 T1OUTA T1OUTB T1INA T1INB T3OUTA T3OUTB T3INA T3INB
EXTRG AIN[7:0] TX0CKIN RX0CKIN S0IN DCD0 S0OUT CLK0OUT RTS0
WATCHDOG
MFT1
MFT3
alternate functions (Italic characters mapped Port2 through Port9
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ST90158 GENERAL DESCRIPTION
DESCRIPTION Address Strobe (output, active low, 3-state). Address Strobe pulsed once beginning each memory cycle. rising edge indicates that address, Read/Write (R/W), Data Memory signals valid memory transfers. Under program control, placed high-impedance state along with Port Port Data Strobe (DS). Data Strobe (output, active low, 3-state). Data Strobe provides timing data movement from Port each memory transfer. During write cycle, data valid leading edge During read cycle, Data must valid prior trailing edge When ST90158 accesses on-chip memory, held high during whole memory cycle. placed high impedance state along with Port Port RESET: Reset (input, active low). ST9+ initialised Reset signal. With deactivation RESET, program execution begins from memory location pointed vector contained memory locations 01h. R/W: Read/Write (output, 3-state). Read/Write determines direction data transfer external memory transactions. when writing external memory, high other transactions. placed high impedance state along with Port Port OSCIN, OSCOUT: Oscillator (input output). These pins connect parallel-resonant crystal MHz), external source on-chip clock oscillator buffer. OSCIN input oscillator inverter internal clock generator; OSCOUT output oscillator inverter. HW0_SW1: When connected through pull-up resistor, software watchdog option selected. When connected through pull-down resistor, hardware watchdog option selected. VPP: Programming voltage EPROM/OTP devices. Must connected user mode through Kohm resistor. AVDD: Analog Analog Digital Converter. AVSS: Analog Analog Digital Converter. VDD: Main Power Supply Voltage 10%). VSS: Digital Circuit Ground. P0[7:0], P1[7:0]: (Input/Output, CMOS compatible). lines grouped into ports providing external memory interface addressing 64Kbytes external memory. P0[7:0], P1[7:0], P2[6:0], P4[7:0], P5[7:3], P5.1, P6[6:0], P7[7:0], P8[7:0], P9[7:4], P9[2:0]: Port Lines (Input/Output, CMOS compatible). lines grouped into ports bits, programmable under program control general purpose alternate functions.
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ST90158 GENERAL DESCRIPTION
DESCRIPTION (Cont'd) Figure 80-Pin TQFP Pin-out
AD6/P0.6 AD7/P0.7 P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 WDOUT/I NT0/P4.4 INT4/P4.5 T0OUTB/INT5 /P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 P2.4
P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P6.6 P6.5/RW P6.4 P6.3 P6.2 P6.1 P6.0 P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 P1.2/A10 P1.1/A9
ST90158/ST90135
P1.0/A8 RESET OSCIN OSCOUT P5.1/SDI HW0SW1 P5.3 P5.4/T1OUTA/DCD0 P5.5/T1OUT1/RTS0 P5.6/T3OUTA/DCD1 P5.7/T3OUTB/RTS1/CKAF P8.0/T3INA P8.1/T1INB P8.2/INT1/T1OUTA P8.3/INT3/T1OUTB P8.4/T1INA/WA IT/WDOUT P8.5/T3INB P8.6/INT7/T3OUTA
P2.5 P2.6 S1OUT/P9.0 T0OUTB/S1IN/P9.1 TX1CKIN/CLK1OUT/P9.2 S0OUT/RX1CKIN/P9.4 S0IN/P9.5 INT2/SCK/P9.6 INT6/SDO/P9.7 AIN0/RX0CKIN/WDIN/EXTRG/P7.0 AIN1/T0INB/SDI/P7.1 AIN2/CLK0OUT/TX0CKIN/P7.2 AIN3/T0INA/P7.3 AIN4/P7.4 AIN5/P7.5 AIN6/P7.6 AIN7/P7.7 AVDD AVSS NMI/T3OUTB/P8.7
*EPROM devices only
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ST90158 GENERAL DESCRIPTION
DESCRIPTION (Cont'd) Figure 80-Pin PQFP Pin-Out
P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P6.6 P6.5/RW P6.4 P6.3 P6.2 P6.1 P6.0 P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 AD4/P0.4 AD5/P0.5 AD6/P0.6 AD7/P0.7 VPP* P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 INT0/WDOUT/P4.4 INT4/P4.5 INT5/T0OUTB/P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6
ST90158/ST90135
P1.2/A10 P1.1/A9 P1.0/A8 RESET OSCIN OSCOUT P5.1/SDI HW0SW1 P5.3 P5.4/T1OUTA/DCD0 P5.5/T1OUTB/RTS0 P5.6/T3OUTA/DCD1 P5.7/T3OUTB/RTS1/CK_AF P8.0/T3INA P8.1/T1INB P8.2/T1OUTA/INT1 P8.3/T1OUTB/INT3 P8.4/T1INA/WAIT/WDOUT P8.5/T3INB P8.6/INT7/T3OUTA P8.7/NMI/T3OUTB AVSS
S1OUT/P9.0 T0OUTB/S1IN/P9.1 TX1CKIN/CLK1OUT/P9.2 S0OUT/RX1CKIN/P9.4 S0IN/P9.5 INT2/SCK/P9.6 INT6/SDO/P9.7 AIN0/RX0CKIN/WDIN/EXTRG/P7.0 AIN1/T0INB/P7.1 AIN2/CLK0OUT/TX0CKIN/P7.2 AIN3/T0INA/P7.3 AIN4/P7.4 AIN5/P7.5 AIN6/P7.6 AIN7/P7.7 AVDD 12/190
*EPROM devices only
ST90158 GENERAL DESCRIPTION
PORT PINS ports device programmed Input/Output Input mode, compatible with CMOS levels (except where Schmitt Trigger present). Each programmed individually (Refer ports chapter). TTL/CMOS Input those port bits where input schmitt trigger implemented, always possible program input level CMOS compatible programming relevant PxC2.n control bit. Refer section titled "Input/Output Configuration" Ports Chapter Table Port CharacteristicPort Port Port Port Port Port Port Port Port Input TTL/CMOS TTL/CMOS TTL/CMOS Schmitt trigger Schmitt trigger TTL/CMOS Schmitt trigger Schmitt trigger Schmitt trigger Output Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Weak Pull-Up Reset State Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Push-Pull/OD Output output buffer programmed pushpull open-drain: attention must paid fact that open-drain option corresponds only disabling P-channel transistor buffer itself: still present physically connected pin. Consequently possible increase output voltage over VDD+0.3 Volt, avoid direct junction biasing.
Legend: Weak Pull-Up, Open Drain
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ST90158 GENERAL DESCRIPTION
PORT PINS (Cont'd) Configure ports configure ports, information Table Table Port Configuration Table ports Chapter (See page 92). Input Note hardware characteristics fixed each port line Table Input note TTL/CMOS, either CMOS input level selected software. Input note Schmitt trigger, selecting CMOS input software effect, input will always Schmitt Trigger. Alternate Functions (AF) More than cannot assigned same time: alternate function selected follows. Inputs: selected implicitly enabling corresponding peripheral. Exception this inputs which must explicitly selected software. Outputs Bidirectional Lines: case Outputs I/Os, selected explicitly software. Example data input S0IN, Port: P9.5, Port Style: Input Schmitt Trigger. Write port configuration bits: P9C2.5=1 P9C1.5=0 P9C0.5=1 Enable peripheral software described chapter. Example data output S0OUT, Port: P9.4 Output push-pull (configured software). Write port configuration bits: P9C2.4=0 P9C1.4=1 P9C0.4=1 Example data input AIN0, Port P7.0, Input Note: does apply Write port configuration bits: P7C2.0=1 P7C1.0=1 P7C0.0=1 Example External Memory AD0, Port P0.0 Write port configuration bits: P0C2.0=0 P0C1.0=1 P0C0.0=1
Table Port Description Alternate FunctionPin PQFP TQFP Alternate Function
Port Name
General Purpose
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 ports useable general purpose (input, output bidirectional)
Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address Address Address
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ST90158 GENERAL DESCRIPTION
Port Name
P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.1 P5.3 P5.4
PQFP
TQFP
General Purpose
Alternate Function
Address Address Address Address Address Internal main Clock Standard Timer Output External Interrupt
INTCLK ports useable STOUT general purINT0 pose (input, WDOUT output bidirectional) INT4 INT5 T0OUTB
Watchdog Timer output External interrupt External Interrupt
Timer Output Timer Output Serial Data
T0OUTA T1OUTA DCD0 RTS0 T1OUTB T3OUTA DCD1 RTS1
Timer output SCI0 Data Carrier Detect
P5.5
SCI0 Request Send Timer output Timer output SCI1 Data Carrier Detect SCI1 Request Send Timer output External Clock Input
P5.6
P5.7
T3OUTB CK_AF
P6.0
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ST90158 GENERAL DESCRIPTION
Port Name
P6.1 P6.2 P6.3 P6.4 P6.5 P6.6
AIN0
PQFP
TQFP
General Purpose
Alternate Function
Read/Write Analog input SCI0 Receive Clock input T/WD input External Trigger Analog input Timer input Serial Data Analog input
P7.0
RX0CKIN WDIN EXTRG AIN1
P7.1
T0INB AIN2
P7.2
CLK0OUT SCI0 Byte Sync Clock output TX0CKIN SCI0 Transmit Clock input Analog input Timer input Analog input Analog input Analog input Analog input Timer input Timer input External interrupt
P7.3 P7.4 P7.5 P7.6 P7.7 P8.0 P8.1 P8.2
AIN3 ports useable general purT0INA pose (input, output bidirec- AIN4 tional) AIN5 AIN6 AIN7 T3INA T1INB INT1 T1OUTA INT3 T1OUTB T1INA
Timer output External interrupt
P8.3
Timer output Timer input External Wait input
P8.4
WAIT WDOUT
Watchdog Timer output Timer input External interrupt
P8.5 P8.6
T3INB INT7 T3OUTA T3OUTB
Timer output Non-Maskable Interrupt
P8.7
Timer output
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ST90158 GENERAL DESCRIPTION
Port Name
PQFP
TQFP
General Purpose
Alternate Function
P9.0 P9.1
S1OUT T0OUTB S1IN
SCI1 Serial Output Timer output SCI1 Serial Input SCI1 Transmit Clock input
P9.2
ports useable general purpose (input, output bidirectional)
CLK1OUT SCI1 Byte Sync Clock output TX1CKIN S0OUT RX1CKIN S0IN INT2 INT6
P9.4 P9.5 P9.6
SCI0 Serial Output SCI1 Receive Clock input SCI0 Serial Input External interrupt
Serial Clock External interrupt
P9.7
Serial Data
Note present ST90135
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ST90158 DEVICE ARCHITECTURE
DEVICE ARCHITECTURE
CORE ARCHITECTURE ST9+ Core Central Processing Unit (CPU) features highly optimised instruction set, capable handling bit, byte (8-bit) word (16-bit) data, well Boolean formats; addressing modes available. Four independent buses controlled Core: 16-bit Memory bus, 8-bit Register data bus, 8-bit Register address 6-bit Interrupt/DMA which connects interrupt controllers on-chip peripherals with Core. This multiple architecture affords high degree pipelining parallel operation, thus making ST9+ family devices highly efficient, both numerical calculation, data handling with regard communication with on-chip peripheral resources. which hold data control bits on-chip peripherals I/Os. single linear memory space accommodating both program data. physically separate memory areas, including internal ROM, internal external memory mapped this common address space. total addressable memory space Mbytes (limited size on-chip memory number external address pins) arranged segments Kbytes. Each segment further subdivided into four pages Kbytes, illustrated Figure Memory Management Unit uses pointer registers address 22-bit memory field using 16-bit address-based instructions. 2.2.1 Register File Register File consists (see Figure MEMORY SPACES general purpose registers (Group There separate memory spaces: registers R223) Register File, which comprises 8-bit system registers System Group (Group registers, arranged groups (Group registers R224 R239) each containing sixteen 8-bit registers plus pages, depending device configura64 pages registers mapped Group tion, each containing registers, mapped Group (R240 R255), Figure Figure Single Program Data Memory Address Space
Addres3FFFFFh 3F0000h 3EFFFFh 3E0000h
Data Page255
Code Segment63
Mbyte135
21FFFFh 210000h 20FFFFh
Reserved
02FFFFh 020000h 01FFFFh 010000h 00FFFFh 000000h
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ST90158 DEVICE ARCHITECTURE
MEMORY SPACES (Cont'd) Figure Register GroupUP PAGES
Figure Page Pointer Group mapping
PAGE
PAGED REGISTERS SYSTEM REGISTERS
PAGE R255 PAGE
R240 R234 GENERAL PURPOSE REGISTERS R224 PAGE POINTER
VA00432
VA00433
Figure Addressing Register File
REGISTER FILE PAGED REGISTERS SYSTEM REGISTERS
VR000118
GROUP R195 (R0C3h) R207
(1100) (0011) GROUP
R195 R192 GROUP
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ST90158 DEVICE ARCHITECTURE
MEMORY SPACES (Cont'd) 2.2.2 Register Addressing Register File registers, including Group paged registers (but excluding Group addressed explicitly means decimal, hexadecimal binary address; thus R231, RE7h R11100111b represent same register (see Figure Group registers only addressed Working Register mode. Note that upper case used denote this direct addressing mode. Working Registers Certain types instruction require that registers specified form "rx", where range these known Working Registers. Note that lower case used denote this indirect addressing mode. addressing schemes available: single group working registers, separately mapped groups, each consisting working registers. These groups mapped starting byte boundary register file means dedicated pointer registers. This technique described more detail Section 2.3.3 Register Pointing Techniques, illustrated Figure Figure System Registers registers Group (R224 R239) System registers addressed using register addressing modes. These registers described greater detail Section SYSTEM REGISTERS. Paged Registers pages, each containing registers, mapped Group These addressed using register addressing mode, conjunction with Page Pointer register, R234, which System registers. This register selects page mapped Group and, once set, does need changed more registers same page addressed succession.
Therefore Page Pointer, R234, instructions: R242, will load contents working register into third register page (R242). These paged registers hold data control information relating on-chip peripherals, each peripheral always being associated with same pages registers ensure code compatibility between ST9+ devices. number these registers therefore depends peripherals which present specific ST9+ family device. other words, pages only exist relevant peripheral present. Table Register File Organization
Hex. Address F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F Decimal Address 240-255 224-239 208-223 192-207 176-191 160-175 144-159 128-143 112-127 96-111 80-95 64-79 48-63 32-47 16-31 00-15 General Purpose Registers Function Paged Registers System Registers Register File Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group
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ST90158 DEVICE ARCHITECTURE
SYSTEM REGISTERS System registers listed Table They used perform important system settings. Their purpose described following pages. Refer chapter dealing with description PORT[5:0] Data registers. Table System Registers (Group
R239 (EFh) R238 (EEh) R237 (EDh) R236 (ECh) R235 (EBh) R234 (EAh) R233 (E9h) R232 (E8h) R231 (E7h) R230 (E6h) R229 (E5h) R228 (E4h) R227 (E3h) R226 (E2h) R225 (E1h) R224 (E0h) SSPLR SSPHR USPLR USPHR MODE REGISTER PAGE POINTER REGISTER REGISTER POINTER REGISTER POINTER FLAG REGISTER CENTRAL INT. CNTL PORT5 DATA REG. PORT4 DATA REG. PORT3 DATA REG. PORT2 DATA REG. PORT1 DATA REG. PORT0 DATA REG.
Note: included device, then this effect. TLIP: Level Interrupt Pending This hardware when Level Interrupt Request recognized. This also software simulate Level Interrupt Request. Level Interrupt pending Level Interrupt pending TLI: Level Interrupt bit. Level Interrupt acknowledged depending TLNM NICR Register. Level Interrupt acknowledged depending TLNM bits NICR Register (described Interrupt chapter). IEN: Interrupt Enable This cleared interrupt acknowledgement, interrupt return (iret). modified implicitly iret, instructions interrupt acknowledge cycle. also explicitly written user, only when interrupt pending. Therefore, user should execute instruction guarantee other means that interrupt request arrive) before write operation CICR register. Disable interrupts except Level Interrupt. Enable Interrupts IAM: Interrupt Arbitration Mode. This cleared software select arbitration mode. Concurrent Mode Nested Mode. CPL[2:0]: Current Priority Level. These three bits record priority level routine currently running (i.e. Current Priority Level, CPL). highest priority level represented 000, lowest 111. bits hardware software provide reference according which subsequent interrupts either left pending allowed interrupt current interrupt service routine. When current interrupt replaced higher priority, current priority value automatically stored until required NICR register.
2.3.1 Central Interrupt Control Register Please refer "INTERRUPT" chapter detailed description interrupt philosophy. CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 Read/Write Register Group: (System) Reset Value: 1000 0111 (87h)
TLIP CPL2 CPL1 CPL0
GCEN: Global Counter Enable. This Global Counter Enable Multifunction Timers. GCEN ANDed with Register (only devices featuring Multifunction Timer) order enable Timers when both bits set. This after Reset cycle.
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SYSTEM REGISTERS (Cont'd) 2.3.2 Flag Register Flag Register contains flags which indicate status. During interrupt, flag register automatically stored system stack area recalled interrupt service routine, thus returning original status. This occurs interrupts and, when operating nested mode, seven versions flag register stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: (System) Reset value: 0000 0000 (00h)
decw), Test (tm, tmw, tcm, tcmw, btset). most cases, Zero flag when contents register being used accumulator become zero, following above operations. Sign Flag. Sign flag affected same instructions Zero flag. Sign flag when (for byte operation) (for word operation) register used accumulator one. Overflow Flag. Overflow flag affected same instructions Zero Sign flags. When set, Overflow flag indicates that two'scomplement number, result register, error, since exceeded largest less than smallest), number that represented two's-complement notation. Decimal Adjust Flag. flag used arithmetic. Since algorithm correcting operations different addition subtraction, this flag used specify which type instruction executed last, that subsequent Decimal Adjust (da) operation perform function correctly. flag cannot normally used test condition programmer. Half Carry Flag. flag indicates carry borrow into) result adding subtracting 8-bit bytes, each representing digits. flag used Decimal Adjust (da) instruction convert binary result previous addition subtraction into correct result. Like flag, this flag normally accessed user. Reserved (must Data/Program Memory Flag. This indicates memory area addressed. value affected Data Memory (sdm) Program Memory (spm) instructions. Refer Memory Management Unit further details.
Carry Flag carry flag affected Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply Divide (mul, div, divws). When set, generally indicates carry most significant position register being used accumulator (bit byte operations word operations). carry flag Carry Flag (scf) instruction, cleared Reset Carry Flag (rcf) instruction, complemented Complement Carry Flag (ccf) instruction. Zero Flag. Zero flag affected Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply Divide (mul, div, divws), Logical (and, andw, orw, xor, xorw, cpl), Increment Decrement (inc, incw, dec,
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SYSTEM REGISTERS (Cont'd) set, data accessed using Data Pointers (DPRs registers), otherwise pointed Code Pointer (CSR register); therefore, user initialization routine must include instruction. Note that code always pointed Code Pointer (CSR). Note: ST9+, flag only compatibility with software developed first generation devices. With single memory addressing space, redundant. must kept with instruction beginning program ensure normal different memory pointers. 2.3.3 Register Pointing Techniques registers within System register group, used pointers working registers. Register Pointer (R232) used single pointer 16-register working space, conjunction with Register Pointer (R233), point separate 8-register spaces. purpose register pointing, register groups register file subdivided into 8register blocks. values specified with Register Pointer instructions refer blocks pointed twin 8-register mode, lower 8-register block location single 16-register mode. Register Pointer instructions srp, srp0 srp1 automatically inform whether Register File operate single 16-register mode twin 8-register mode. instruction selects single 16-register group mode
specifies location lower 8-register block, while srp0 srp1 instructions automatically select twin 8-register group mode specify locations each 8-register block. There limitation order position these register groups, other than that they must start 8-register boundary twin 8-register mode, 16-register boundary single 16register mode. block number should always even number single 16-register mode. 16-register group will always start block whose number nearest even number equal lower than block number specified instruction. Avoid using block numbers, since this confusing twin mode subsequently selected. Thus: will interpreted will allow using .R31 r15. single 16-register mode, working registers referred r15. twin 8-register mode, registers block pointed means srp0 instruction), while registers block pointed means srp1 instruction). Caution: Group registers only accessed working registers using Register Pointers, means Stack Pointers. They cannot addressed explicitly form "Rxxx".
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SYSTEM REGISTERS (Cont'd) POINTER REGISTER (RP0) R232 Read/Write Register Group: (System) Reset Value: xxxx xx00 (xxh)
POINTER REGISTER (RP1) R233 Read/Write Register Group: (System) Reset Value: xxxx xx00 (xxh)
RG[4:0]: Register Group number. These bits contain number range register block specified srp0 instructions. single 16-register mode number indicates lower 8-register blocks which working registers mapped, while twin 8-register mode indicates 8-register block which mapped. RPS: Register Pointer Selector. This instructions srp0 srp1 indicate that twin register pointing mode selected. reset instruction indicate that single register pointing mode selected. Single register pointing mode Twin register pointing mode 1:0: Reserved. Forced hardware zero.
This register only used twin register pointing mode. When using single register pointing mode, when using only twin register groups, register must considered RESERVED used general purpose register. RG[4:0]: Register Group number. These bits contain number range 8-register block specified srp1 instruction, which mapped. RPS: Register Pointer Selector This srp0 srp1 instructions indicate that twin register pointing mode selected. reset instruction indicate that single register pointing mode selected. Single register pointing mode Twin register pointing mode 1:0: Reserved. Forced hardware zero.
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SYSTEM REGISTERS (Cont'd) Figure Pointing single group registerREGISTER GROUP REGIST FILE
Figure Pointing groups registerREGIST GROUP REGISTER FILE
BLOCK NUMBER
BLOCK NUMBER
points addressed BLOCK addressed BLOCK GROUP REGISTER POINTER
REGISTER POINTE REGIST POINTE
instruction
srp0
srp1
instructions point
GROUP
GROUP addressed BLOCK
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SYSTEM REGISTERS (Cont'd) 2.3.4 Paged Registers pages, each containing registers, mapped Group These paged registers hold data control information relating on-chip peripherals, each peripheral always being associated with same pages registers ensure code compatibility between ST9+ devices. number these registers depends peripherals present specific device. other words, pages only exist relevant peripheral present. paged registers addressed using normal register addressing modes, conjunction with Page Pointer register, R234, which System registers. This register selects page mapped Group and, once set, does need changed more registers same page addressed succession. Thus instructions: R242, will load contents working register into third register page (R242). Warning: During interrupt, register saved automatically stack. needed, should saved/restored user within interrupt routine. PAGE POINTER REGISTER (PPR) R234 Read/Write Register Group: (System) Reset value: xxxx xx00 (xxh)
Selection internal external System User Stack areas, Management clock frequency, Enabling request Wait signals when interfacing external memory. MODE REGISTER (MODER) R235 Read/Write Register Group: (System) Reset value: 1110 0000 (E0h)
DIV2 PRS2 PRS1
PRS0 BRQEN HIMP
SSP: System Stack Pointer. This selects internal external System Stack area. External system stack area, memory space. Internal system stack area, Register File (reset state). USP: User Stack Pointer. This selects internal external User Stack area. External user stack area, memory space. Internal user stack area, Register File (reset state). DIV2: OSCIN Clock Divided This controls divide-by-2 circuit operating OSCIN. Clock divided Clock divided PRS[2:0]: CPUCLK Prescaler. These bits load prescaler division factor internal clock (INTCLK). prescaler factor selects internal clock frequency, which divided factor from Refer Reset Clock Control chapter further information. BRQEN: Request Enable. External Memory Request disabled External Memory Request enabled BREQ (where available). HIMP: High Impedance Enable. When Ports depending device configuration, programmed Address Data lines interface external Memory, these lines Memory interface control lines (AS,
PP[5:0]: Page Pointer. These bits contain number range page specified instruction. Once page pointer been set, there need refresh unless different page required. 1:0: Reserved. Forced hardware 2.3.5 Mode Register Mode Register allows control following operating parameters:
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SYSTEM REGISTERS (Cont'd) R/W) forced into High Impedance state setting HIMP bit. When this reset, effect. Setting HIMP recommended noise reduction when only internal Memory used. Port and/or declared address port (for example: P10. Address, P15. I/O), HIMP effect lines. 2.3.6 Stack Pointers separate, double-register stack pointers available: System Stack Pointer User Stack Pointer, both which address registers memory. stack pointers point "bottom" stacks which filled using push commands emptied using commands. stack pointer automatically pre-decremented when data "pushed" post-incremented when data "popped" out. push commands used manage System Stack addressed User Stack adding suffix "u". stack instruction word, suffix added. These suffixes combined. When bytes words) "popped" from stack, contents stack locations unchanged until fresh data loaded. Thus, when data "popped" from stack area, stack contents remain unchanged. Note: Instructions such pushuw RR236 pushw RR238, well corresponding instructions (where R236 R237, R238 R239 themselves user system stack pointers respectively), must used, since pointer values themselves automatically changed push instruction, thus corrupting their value. System Stack System Stack used temporary storage system and/or control data, such Flag register Program counter. following automatically push data onto System Stack: Interrupts When entering interrupt, Flag Register pushed onto System Stack. ENCSR EMR2 register set, then
Code Segment Register also pushed onto System Stack. Subroutine Calls When call instruction executed, only pushed onto stack, whereas when calls instruction (call segment) executed, both Code Segment Register pushed onto System Stack. Link Instruction link linku instructions create language stack frame user-defined length System User Stack. above conditions associated with their counterparts, such return instructions, which stored data items stack. User Stack User Stack provides totally user-controlled stacking area. User Stack Pointer consists registers, R236 R237, which both used addressing stack memory. When stacking Register File, User Stack Pointer High Register, R236, becomes redundant must considered reserved. Stack Pointers Both System User stacks pointed double-byte stack pointers. Stacks Register File. Only lower byte will required stack Register File. upper byte must then considered reserved must used general purpose register. stack pointer registers located System Group Register File, this illustrated Table Stack location Care necessary when managing stacks there limit stack sizes apart from bottom address space which stack placed. Consequently programmers advised stack pointer value high possible, particularly when using Register File stacking area. Group good location stack Register File, since highest available area. stacks located anywhere first groups Register File (internal stacks) (external stacks). Note. Stacks must located Paged Register Group System Register Group.
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SYSTEM REGISTERS (Cont'd) USER STACK POINTER HIGH REGISTER (USPHR) R236 Read/Write Register Group: (System) Reset value: undefined
USP1 USP1 USP1 USP1 USP1 USP1 USP9 USP8
SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 Read/Write Register Group: (System) Reset value: undefined
SSP1 SSP1 SSP1 SSP1 SSP1 SSP1 SSP9 SSP8
USER STACK POINTER REGISTER (USPLR) R237 Read/Write Register Group: (System) Reset value: undefined
SYSTEM STACK POINTER REGISTER (SSPLR) R239 Read/Write Register Group: (System) Reset value: undefined
USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Figure Internal Stack Mode
Figure External Stack Mode
REGIST FILE STACK POINTER (LOW) points
REGISTER FILE
STACK POINTER (LOW) STACK POINTER (HIGH) point MEMORY
STACK
STACK
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MEMORY ORGANIZATION Code data accessed within same linear address space. physically separate memory areas, including internal ROM, internal external memory mapped common address space. ST9+ provides total addressable memory space Mbytes. This address space arranged segments Kbytes; each segment again subdivided into four Kbyte pages. mapping various memory areas (internal ROM, external memory) differs from device device. Each 64-Kbyte physical memory segment mapped either internally externally; memory internal smaller than Kbytes, remaining locations 64-Kbyte segment used (reserved). Refer Register Memory Chapter more details memory map.
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MEMORY MANAGEMENT UNIT Core includes Memory Management Unit (MMU) which must programmed perform memory accesses (even external memory used). controlled registers bits (ENCSR DPRREM) present EMR2, which written read user program. These registers mapped within group Page Register File. registers Figure Page RegisterPage EMR2 EMR1 DPR3 DPR2 DPR1 DPR0 DMASR R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 SSPLR SSPHR USPLR USPHR MODER FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR SSPLR SSPHR USPLR USPHR MODER FLAGR CICR P5DR P4DR DPR3 DPR2 DPR1 DPR0
sub-divided into main groups: first group four 8-bit registers (DPR[3:0]), second group three 6-bit registers (CSR, ISR, DMASR). first group used extend address during Data Memory access (DPR[3:0]). second used manage Program Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR CSR), transfers (DMASR ISR).
Relocation P[3:0] DPR[3:0] Register
DMASR EMR2 EMR1 DPR3 DPR2 DPR0
DMASR EMR2 EMR1 P3DR P2DR P1DR P0DR
DPRREM=0 (default setting)
DPRREM=1
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ADDRESS SPACE EXTENSION manage Mbytes addressing space necessary have address bits. adds bits usual 16-bit address, thus translating 16-bit virtual address into 22-bit physical address. There different ways this depending memory involved operation being performed. 2.6.1 Addressing 16-Kbyte Pages This extension mode implicitly used address Data memory space being performed. Data memory space divided into pages Kbytes. Each four 8-bit registers (DPR[3:0], Data Page Registers) selects different 16-Kbyte page. registers allow access entire memory space which contains pages Kbytes. Data paging performed extending 16-bit address with contents register. MSBs 16-bit address interpreted identification number register used. Therefore, registers Figure Addressing DPR[3:0] involved following virtual address ranges: DPR0: from 0000h 3FFFh; DPR1: from 4000h 7FFFh; DPR2: from 8000h BFFFh; DPR3: from C000h FFFFh. contents selected register specify possible data memory pages. This 8-bit data page number, addition remaining 14-bit page offset address forms physical 22-bit address (see Figure 14). register cannot modified addressing mode that uses same register. instance, instruction "POPW DPR0" legal only stack kept either register file memory location above 8000h, where DPR2 DPR3 used. Otherwise, since DPR0 DPR1 modified instruction, unpredictable behaviour could result.
registers DPR0 DPR1 DPR2 DPR3
16-bit virtual addre00
22-bit physical addre31/190
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ADDRESS SPACE EXTENSION (Cont'd) 2.6.2 Addressing 64-Kbyte Segments This extension mode used address Data memory space during Program memory space during code execution (normal code interrupt routines). Three registers used: CSR, ISR, DMASR. 6-bit contents registers CSR, ISR, DMASR define Memory segments Kbytes within Mbytes address space. register contents represent MSBs memory address, whereas LSBs address (intra-segment address) given virtual 16-bit address (see Figure 15). REGISTERS uses registers mapped into Group Page Register File bits EMR2 register.
Most these registers have default value after reset. 2.7.1 DPR[3:0]: Data Page Registers DPR[3:0] registers allow access entire Mbyte memory space composed pages Kbytes. 2.7.1.1 Data Page Register Relocation these registers used frequently, they relocated register group programming EMR2-R246 register page this set, DPR[3:0] registers located R224-227 place Port Data Registers, which re-mapped default DPR's locations: R240-243 page Data Page Register relocation illustrated Figure
Figure Addressing CSR, ISR, DMASR
registers DMASR
16-bit virtual addre1 Fetching program instruction Data Memory accessed Fetching interrupt instruction access Program Memory
22-bit physical addre32/190
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REGISTERS (Cont'd) DATA PAGE REGISTER (DPR0) R240 Read/Write Register Page: Reset value: undefined This register relocated R224 EMR2.5 set.
DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0
DATA PAGE REGISTER (DPR2) R242 Read/Write Register Page: Reset value: undefined This register relocated R226 EMR2.5 set.
DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2
DPR0_[7:0]: These bits define 16Kbyte Data Memory page number. They used most significant address bits (A21-14) extend address during Data Memory access. DPR0 register used when addressing virtual address range 0000h-3FFFh. DATA PAGE REGISTER (DPR1) R241 Read/Write Register Page: Reset value: undefined This register relocated R225 EMR2.5 set.
DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1
DPR2_[7:0]: These bits define 16Kbyte Data memory page. They used most significant address bits (A21-14) extend address during Data memory access. DPR2 register involved when virtual address range 8000h-BFFFh. DATA PAGE REGISTER (DPR3) R243 Read/Write Register Page: Reset value: undefined This register relocated R227 EMR2.5 set.
DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3
DPR1_[7:0]: These bits define 16Kbyte Data Memory page number. They used most significant address bits (A21-14) extend address during Data Memory access. DPR1 register used when addressing virtual address range 4000h-7FFFh.
DPR3_[7:0]: These bits define 16Kbyte Data memory page. They used most significant address bits (A21-14) extend address during Data memory access. DPR3 register involved when virtual address range C000h-FFFFh.
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REGISTERS (Cont'd) 2.7.2 CSR: Code Segment Register This register selects 64-Kbyte code segment being used run-time access instructions. also used access data instruction been executed ldpp, ldpd, lddp). Only LSBs register implemented, bits reserved. register allows access entire memory space, divided into segments Kbytes. generate 22-bit Program memory address, contents register directly used MSBs, 16-bit virtual address LSBs. Note: register should only read written data operations (there some exceptions which documented following paragraph). however, modified either directly means calls instructions, indirectly stack, means rets instruction. CODE SEGMENT REGISTER (CSR) R244 Read/Write Register Page: Reset value: 0000 0000 (00h)
CSR_ CSR_ CSR_ CSR_ CSR_ CSR_
ENCSR (EMR2 register) also described chapter relating Interrupts, please refer this description further details. Reserved, keep reset state. ISR_[5:0]: These bits define 64-Kbyte memory segment (among which contains interrupt vector table code interrupt service routines transfers (when DAPR register reset). These bits used most significant address bits (A21-16). used extend address space cases: Whenever interrupt occurs: points 64-Kbyte memory segment containing interrupt vector table interrupt service routine code. also Interrupts chapter. During transactions between peripheral memory when DAPR register reset points K-byte Memory segment that will involved transaction. 2.7.4 DMASR: Segment Register SEGMENT REGISTER (DMASR) R249 Read/Write Register Page: Reset value: undefined
SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Reserved, keep reset state. CSR_[5:0]: These bits define 64Kbyte memory segment (among which contains code being executed. These bits used most significant address bits (A21-16). 2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR) R248 Read/Write Register Page: Reset value: undefined
ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
Reserved, keep reset state. DMASR_[5:0]: These bits define 64Kbyte Memory segment (among used when transaction performed between peripheral's data register Memory, with DAPR register set. These bits used most significant address bits (A21-16). reset, register used extend address.
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REGISTERS (Cont'd) Figure Memory Addressing Scheme (example)
byte3FFFFFh
294000h
DPR3 DPR2 DPR1 DPR0 20C000h 200000h 1FFFFFh 240000h 23FFFFh
DMASR
040000h 03FFFFh 030000h 020000h
010000h 00C000h 000000h
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USAGE 2.8.1 Normal Program Execution Program memory organized 64Kbyte segments. program span many segments needed, procedure cannot stretch across segment boundaries. jps, calls rets instructions, which automatically modify CSR, must used jump across segment boundaries. Writing forbidden during normal program execution because synchronized with opcode fetch. This could result fetching first byte instruction from memory segment second byte from another. Writing allowed when being used, during interrupt service routine ENCSR reset. Note that routine must always called same way, i.e. either always with call always with calls, depending whether routine ends with rets. This means that routine written without prior knowledge location other routines which call program code does into single 64-Kbyte segment, then calls/rets should used. typical microcontroller applications, less than Kbytes used, four Data space pages normally sufficient, change DPR[3:0] needed during Program execution. useful however part into data space contains strings, tables, maps, etc. there frequent paging, user (DPRREM) register R246 (EMR2) Page This swaps location registers DPR[3:0] with that data registers Ports this way, registers accessed without need save/set/restore Page Pointer Register. Port registers therefore moved page Applications that require paging typically more than Kbytes external memory, ports required address their data registers unused. 2.8.2 Interrupts register been created that interrupt routines found means same vector table even after segment jump/call. When interrupt occurs, behaves ways, depending value ENCSR EMR2 register (R246 Page 21). this reset (default condition), works original compatibility mode. duration interrupt service routine, used instead CSR, interrupt stack frame kept exactly original (only flags pushed). This avoids need save stack case interrupt, ensuring fast interrupt response time. drawback that possible interrupt service routine perform segment calls/jps: these instructions would update CSR, which, this case, used (ISR used instead). code size interrupt service routines thus limited Kbytes. instead, EMR2 register set, used only point interrupt vector table initialize beginning interrupt service routine: pushed onto stack together with flags, then loaded with ISR. this case, iret will also restore from stack. This approach lets interrupt service routines access whole 4-Mbyte address space. drawback that interrupt response time slightly increased, because need also save stack. Compatibility with original also lost this case, because interrupt stack frame different; this difference, however, would noticeable vast majority programs. Data memory mapping independent value EMR2 register, remains same normal code execution: stack same that used main program, ST9. interrupt service routine needs access additional Data memory, must save more) DPRs, load with needed memory page restore before completion. 2.8.3 Depending DAPR register (see chapter) uses either DMASR memory accesses: this guarantees that will always find memory segment(s), matter what segment changes application performed. Unlike interrupts, transactions cannot save/restore paging registers, dedicated segment register (DMASR) been created. Having only register this kind means that accesses should programmed following segments: pointed (when DAPR register reset), referenced DMASR (when set).
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REGISTER MEMORY
MEMORY CONFIGURATION Program memory space ST90135/158, 0/16/24/32/48/64/K bytes directly addressable on-chip memory, fully available user. first memory locations from address hold Reset Vector, Top-Level (Pseudo Non-Maskable) interrupt, Divide Zero Trap Routine vector and, optionally, interrupt vector table with on-chip peripherals external interrupt sources. Apart from this case other part Program memory predetermined function except segment which reserved STMicroelectronics. EPROM PROGRAMMING 65536 bytes EPROM memory ST90E158 programmed using EPROM Programming Boards (EPB) gang programmers available from STMicroelectronics. EPROM Erasing EPROM windowed package ST90E158 erased exposure Ultra-Violet light. erasure characteristic ST90E158 such that erasure begins when memory exposed light with wave lengths shorter than approximately should noted that sunlight some types fluorescent lamps have wavelengths range thus recommended that window ST90E158 packages covered opaque label prevent unintentional erasure problems when testing application such environment. recommended erasure procedure EPROM exposure short wave ultraviolet light which have wave-length integrated dose (i.e. U.V. intensity exposure time) erasure should minimum 15W-sec/cm2. erasure time with this dosage approximately minutes using ultraviolet lamp with 12000mW/cm2 power rating. ST90E158 should placed within 2.5cm inch) lamp tubes during erasure. Table First Bytes Program Space
Address high Power Reset routine Address Power Reset routine Address Address Address Address high Divide zero trap Subroutine Divide zero trap Subroutine high Level Interrupt routine Level Interrupt routine
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Figure Interrupt Vector Table
REGISTE FILE PAGE REGISTE PROGRAM MEMORY USER USER DIVIDE-BY -ZERO USER MAIN PROGRAM INT. VECTOR REGISTER USER LEVEL R240 R239
0000FFh EVEN 000004h 000002h 000000h ADDRES VECTOR LEVEL INT. DIVIDE-B Y-ZERO POWER-ON RESET TABLE
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MEMORY Figure Memory
3FFFFFh
External Memory
Upper Memory (usually mapped Segment 23h)
230000h 22FFFFh
Reserved
SEGMENTS Kbyte
Internal bytes bytes Kbytes Kbytes Kbyte
20FFFFh
210000h 20FFFFh
PAGE Kbyte20C000h 20BFFFh
PAGE Kbyte20FE00h 20FD00h 20FC00h 204000h 203FFFh 208000h 207FFFh
SEGMENT Kbyte
PAGE Kbytes PAGE Kbyte200000h 1FFFFFh
20FA00h 20F800h
External Memory
Lower Memory (usually ROM/EPROM mapped Segment
010000h 00FFFFh
Kbytes Kbytes Kbyte
00FFFFh 00BFFFh 007FFFh 00FFFFh 003FFFh
PAGE Kbyte00C000h 00BFFFh
Kbytes Internal Kbyte
Internal ROM/EPROM (external ROMless devices)
PAGE Kbyte008000h 007FFFh
SEGMENT Kbyte
PAGE Kbyte004000h 003FFFh
000000
PAGE Kbyte000000h
Note: total amount directly addressable external memory Kbytes.
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ST90158/135 REGISTER following pages contain list ST90158/135 registers, grouped peripheral function. very careful correctly program both: registers dedicated particular function peripheral. Registers common other functions. particular, double-check that registers with "undefined" reset values have been correctly initialised. Warning: Note that EIVR each register, bits significant. Take care when defining base vector addresses that entries Interrupt Vector table overlap.
Table Common RegisterFunction Peripheral SCI, SPI, WDT, STIM PORTS EXTERNAL INTERRUPT RCCU Common Registers CICR NICR REGISTERS PORT REGISTERS CICR NICR PORT REGISTERS CICR NICR EXTERNAL INTERRUPT REGISTERS PORT REGISTERS PORT REGISTERS MODER INTERRUPT REGISTERS PORT REGISTERS INTERRUPT REGISTERS MODER
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Table Group Pages Resources available ST90158/ST90135 devices:
Register R255 R254 R253 R252 R251 R250 R249 R248 MFT1 R247 R246 R245 R244 R243 R242 R241 Res. R240 ST90158/ST90E158 only. present ST90135. PORT PORT PORT PORT MFT1 MFT3 Res. Res. PORT Res. Res. Page
PORT Res. Res. Res.
PORT
Res.
PORT
Res. MFT0 MFT3 Res. SCI0 SCI1
PORT
RCCU
Res. Res. Res. Res. STIM Res. Res. RCCU RCCU
MFT0
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Table Detailed Register
Page (Decimal) Block Reg. R230 R231 R232 R233 Core R234 R235 R236 R237 R238 R239 R224 Port 5:4,2:0 R225 R226 R228 R229 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 Port Port Port R253 R254 R240 R241 R242 R244 R245 R246 R248 R249 R250 Register Name CICR FLAGR MODER USPHR USPLR SSPHR SSPLR P0DR P1DR P2DR P4DR P5DR EITR EIPR EIMR EIPLR EIVR NICR WDTHR WDTLR WDTPR WDTCR SPIDR SPICR P0C0 P0C1 P0C2 P1C0 P1C1 P1C2 P2C0 P2C1 P2C2 Description Central Interrupt Control Register Flag Register Pointer Register Pointer Register Page Pointer Register Mode Register User Stack Pointer High Register User Stack Pointer Register System Stack Pointer High Reg. System Stack Pointer Reg. Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register External Interrupt Trigger Register External Interrupt Pending Reg. External Interrupt Mask-bit Reg. External Interrupt Priority Level Reg. External Interrupt Vector Register Nested Interrupt Control Watchdog Timer High Register Watchdog Timer Register Watchdog Timer Prescaler Reg. Watchdog Timer Control Register Wait Control Register Data Register Control Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Reset Value Hex.
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Page (Decimal)
Block Port Port
Reg. R240 R241 R242 R244 R245 R246 R248 R249 R250 R251 R252 R253 R254 R255
Register Name P4C0 P4C1 P4C2 P5C0 P5C1 P5C2 P6C0 P6C1 P6C2 P6DR P7C0 P7C1 P7C2 P7DR
Description Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register
Reset Value Hex. 00/FF 00/00 00/00
Port Port
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Page (Decimal)
Block
Reg. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R244 R245 R246 R247
Register Name REG0HR1 REG0LR1 REG1HR1 REG1LR1 CMP0HR1 CMP0LR1 CMP1HR1 CMP1LR1 TCR1 TMR1 ICR1 PRSR1 OACR1 OBCR1 FLAGR1 IDMR1 DCPR0 DAPR0 IVR0 IDCR0 IOCR DCPR1 DAPR1 IVR1 IDCR1 REG0HR0 REG0LR0 REG1HR0 REG1LR0 CMP0HR0 CMP0LR0 CMP1HR0 CMP1LR0 TCR0 TMR0 ICR0 PRSR0 OACR0 OBCR0 FLAGR0 IDMR0
Description Capture Load Register High Capture Load Register Capture Load Register High Capture Load Register Compare Register High Compare Register Compare Register High Compare Register Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output Control Register Output Control Register Flags Register Interrupt/DMA Mask Register Counter Pointer Register Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Connection Register Counter Pointer Register Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Capture Load Register High Capture Load Register Capture Load Register High Capture Load Register Compare Register High Compare Register Compare Register High Compare Register Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output Control Register Output Control Register Flags Register Interrupt/DMA Mask Register
Reset Value Hex.
MFT1
MFT0,1
R248 R240 R241 R242 R243 R240 R241 R242 R243 R244
MFT0
R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255
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Page (Decimal)
Block
Reg. R240
Register Name REG0HR1 REG0LR1 REG1HR1 REG1LR1 CMP0HR1 CMP0LR1 CMP1HR1 CMP1LR1 TCR1 TMR1 ICR1 PRSR1 OACR1 OBCR1 FLAGR1 IDMR1 DCPR0 DAPR0 IVR0 IDCR0 DPR0 DPR1 DPR2 DPR3 DMASR EMR1 EMR2
Description Counter High Byte Register Counter Byte Register Standard Timer Prescaler Register Standard Timer Control Register Capture Load Register High Capture Load Register Capture Load Register High Capture Load Register Compare Register High Compare Register Compare Register High Compare Register Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output Control Register Output Control Register Flags Register Interrupt/DMA Mask Register Counter Pointer Register Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Data Page Register Data Page Register Data Page Register Data Page Register Code Segment Register Interrupt Segment Register Segment Register External Memory Register External Memory Register
Reset Value Hex.
STIM
R241 R242 R243 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R244 R245 R246 R247 R240 R241 R242
MFT3
R243 R244 R248 R249 R245 R246
EXTMI
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Page (Decimal)
Block
Reg. R240 R241 R242 R243 R244 R245 R246 R247
Register Name RDCPR0 RDAPR0 TDCPR0 TDAPR0 IVR0 ACR0 IMR0 ISR0 RXBR0 TXBR0 IDPR0 CHCR0 CCR0 BRGHR0 BRGLR0 SICR0 SOCR0 RDCPR1 RDAPR1 TDCPR1 TDAPR1 IVR1 ACR1 IMR1 ISR1 RXBR1 TXBR1 IDPR1 CHCR1 CCR1 BRGHR1 BRGLR1 SICR1 SOCR1 P8C0 P8C1 P8C2 P8DR P9C0 P9C1 P9C2 P9DR
Description Receiver Transaction Counter Pointer Receiver Source Address Pointer Transmitter Transaction Counter Pointer Transmitter Destination Address Pointer Interrupt Vector Register Address/Data Compare Register Interrupt Mask Register Interrupt Status Register Receive Buffer Register Transmitter Buffer Register Interrupt/DMA Priority Register Character Configuration Register Clock Configuration Register Baud Rate Generator High Reg. Baud Rate Generator Register Synchronous Input Control Synchronous Output Control Receiver Transaction Counter Pointer Receiver Source Address Pointer Transmitter Transaction Counter Pointer Transmitter Destination Address Pointer Interrupt Vector Register Address/Data Compare Register Interrupt Mask Register Interrupt Status Register Receive Buffer Register Transmitter Buffer Register Interrupt/DMA Priority Register Character Configuration Register Clock Configuration Register Baud Rate Generator High Reg. Baud Rate Generator Register Synchronous Input Control Synchronous Output Control Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register
Reset Value Hex. 00/03 00/00 00/00 00/00 00/00 00/00
SCI0
R248 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 R248 R248 R249 R250 R251 R252 R253 R254 R255 R248 R249 R250 R251 R252 R253 R254 R255
SCI1
Port Port
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Page (Decimal)
Block
Reg. R240
Register Name CLKCTL CLK_FLAG PLLCONF D0R0 D1R0 D2R0 D3R0 D4R0 D5R0 D6R0 D7R0 LT6R0 LT7R0 UT6R0 UT7R0 CRR0 CLR0 ICR0 IVR0
Description Clock Control Register Clock Flag Register Configuration Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Lower Threshold Reg. Channel Lower Threshold Reg. Channel Upper Threshold Reg. Channel Upper Threshold Reg. Compare Result Register Control Logic Register Interrupt Control Register Interrupt Vector Register
Reset Value Hex.
RCCU
R242 R246 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255
present ST90135. Note: denotes byte with undefined value, however some bits have defined values. Refer register description details.
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INTERRUPTS
INTRODUCTION responds peripheral external events through interrupt channels. Current program execution suspended allow execute specific response routine when such event occurs, providing that interrupts have been enabled, according priority mechanism. event generates valid interrupt request, current program status saved control passes appropriate Interrupt Service Routine. receive requests from following sources: On-chip peripherals External pins Top-Level Pseudo-non-maskable interrupt According on-chip peripheral features, event occurrence generate Interrupt request which depends selected mode. eight external interrupt channels, with programmable input trigger edge, available. addition, dedicated interrupt channel, Top-level priority, devoted either external (where available) provide NonMaskable Interrupt, Timer/Watchdog. Interrupt service routines addressed through vector table mapped Memory. Figure Interrupt Response
INTERRUPT VECTORING implements interrupt vectoring structure which allows on-chip peripheral identify location first instruction Interrupt Service Routine automatically. When interrupt request acknowledged, peripheral interrupt module provides, through Interrupt Vector Register (IVR), vector point into vector table locations containing start addresses Interrupt Service Routines (defined programmer). Each peripheral specific mapped within Register File pages. Interrupt Vector table, containing addresses Interrupt Service Routines, located first locations Memory pointed register, thus allowing 8-bit vector addressing. description register refer chapter describing MMU. user Power Reset vector stored first physical bytes memory, 000000h 000001h. Level Interrupt vector located addresses 0004h 0005h segment pointed Interrupt Segment Register (ISR). With Interrupt Vector register, possible address several interrupt service routines; fact, peripherals share same interrupt vector register among several interrupt channels. most significant bits vector user programmable define base vector address within vector table, least significant bits controlled interrupt module, hardware, select appropriate vector. Note: first locations memory segment pointed contain program code. 4.2.1 Divide Zero trap Divide Zero trap vector located addresses 0002h 0003h each code segment; should noted that each code segment Divide Zero service routine required. Warning. Although Divide Zero Trap operates interrupt, FLAG Register pushed onto system Stack automatically. result must regarded subroutine, service routine must with instruction (not IRET
NORMAL PROGRAM FLOW
INTERRUPT SERVICE ROUTINE
INTERRUPT
CLEAR PENDING
IRET INSTRUCTION
VR001833
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4.2.2 Segment Paging During Interrupt Routines ENCSR EMR2 register used select between original backward compatibility mode ST9+ interrupt management mode. backward compatibility mode (ENCSR ENCSR reset, works original compatibility mode. duration interrupt service routine, used instead CSR, interrupt stack frame identical that original ST9: only Flags pushed. This avoids saving stack event interrupt, thus ensuring faster interrupt response time. possible interrupt service routine perform inter-segment calls jumps: these instructions would update CSR, which, this case, used (ISR used instead). code segment size interrupt service routines thus limited bytes. ST9+ mode (ENCSR ENCSR set, only used point interrupt vector table initialize beginning interrupt service routine: pushed onto stack together with flags, then loaded with contents ISR. this case, iret will also restore from stack. This approach allows interrupt service routines access entire Mbytes address space. drawback that interrupt response time slightly increased, because need also save stack. Full compatibility with original lost this case, because interrupt stack frame different.
ENCSR Mode Compatible ST9+ Pushed/Popp FLAGR, FLAGR Registers Max. Code Size 64KB limit interrupt service routine Within segment Across segment
INTERRUPT PRIORITY LEVELS supports fully programmable interrupt priority structure. Nine priority levels available define channel priority relationships: on-chip peripheral channels eight external interrupt sources programmed within eight priority levels. Each channel 3bit field, (Priority Level), that defines priority level range from (highest priority) (lowest priority). level (Top Level Priority) reserved Timer/Watchdog External Pseudo Non-Maskable Interrupt. Interrupt service routine this level cannot interrupted arbitration mode. mask both maskable (TLI) non-maskable (TLNM). PRIORITY LEVEL ARBITRATION bits (Current Priority Level) Central Interrupt Control Register contain priority currently running program (CPU priority). (lowest priority) upon reset modified during program execution either software automatically hardware according selected Arbitration Mode. During every instruction, arbitration phase takes place, during which, every channel capable generating Interrupt, each priority level compared other requests (interrupts DMA). highest priority request interrupt, value must strictly lower (that higher priority) than value stored CICR register (R230) order acknowledged. Level Interrupt overrides every other priority. 4.4.1 Priority level (Lowest) Interrupt requests level cannot acknowledged, this value (the lowest possible priority) cannot strictly lower than value. This fully polled interrupt environment. 4.4.2 Maximum depth nesting more than routines nested. interrupt routine level being serviced, other Interrupts located level interrupt This guarantees maximum number nested levels including Level Interrupt request. 4.4.3 Simultaneous Interrupts more requests occur same time same priority level, on-chip daisy chain, specific every version, selects channel
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with highest position chain, shown Figure Table Daisy Chain Priority
Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 TIMER0 SCI0 SCI1 TIMER3 TIMER1 INT0/WDT INT1 INT2/SPI INT3 INT4/STIM INT5 INT6/RCCU INT7
Lowest Position
4.4.4 Dynamic Priority Level Modification main program routines specifically prioritized. Since represented bits read/write register, possible modify dynamically current priority value during program execution. This means that critical section have higher priority with respect other interrupt requests. Furthermore possible prioritize even Main Program execution modifying during execution. Figure Figure Example Dynamic priority level modification Nested Mode
INTERRUPT PRIORITY LEVEL Priority Level MAIN program INT6 MAIN CPL6 CPL5: INT6 pending
CPL=6 MAIN CPL=7
ARBITRATION MODES provides interrupt arbitration modes: Concurrent mode Nested mode. Concurrent mode standard interrupt arbitration mode. Nested mode improves effective interrupt response time when service routine nesting required, depending request priority levels.
control CICR Register selects Concurrent Arbitration mode Nested Arbitration Mode. 4.5.1 Concurrent Mode This mode selected when cleared (reset condition). arbitration phase, performed during every instruction, selects request with highest priority level. value modified this mode. Start Interrupt Routine interrupt cycle performs following steps: maskable interrupt requests disabled clearing CICR.IEN. byte pushed onto system stack. high byte pushed onto system stack. ENCSR set, pushed onto system stack. Flag register pushed onto system stack. loaded with 16-bit vector stored Vector Table, pointed IVR. ENCSR set, loaded with contents; otherwise used place until iret instruction. Interrupt Routine Interrupt Service Routine must ended with iret instruction. iret instruction executes following operations: Flag register popped from system stack. ENCSR set, popped from system stack. high byte popped from system stack. byte popped from system stack. unmasked Interrupts enabled setting CICR.IEN bit. ENCSR reset, used instead ISR. Normal program execution thus resumes interrupted instruction. pending interrupts remain pending until next instruction (even executed during interrupt service routine). Note: Concurrent mode, source priority level only useful during arbitration phase, where compared with other priority levels with CPL. trace kept value during ISR. other requests issued during interrupt service routine, once global CICR.IEN re-enabled, they will acknowledged regardless interrupt service routine's priority. This cause undesirable interrupt response sequences.
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ARBITRATION MODES (Cont'd) Examples following examples, three interrupt requests with different priority levels occur simultaneously during interrupt service routine.
Example first example, (simplest case, Figure instruction used within interrupt service routines. This means that interrupt serviced middle current one. interrupt routines will thus serviced after another, order their priority, until main program eventually resumes.
Figure Simple Example Sequence Interrupt Requests with: Concurrent mode selected unchanged interrupt routine0 Priority Level Interrupt Request
INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL
MAIN MAIN
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ARBITRATION MODES (Cont'd) Example second example, (more complex, Figure 22), each interrupt service routine sets Interrupt Enable with instruction beginning routine. Placed here, minimizes response time requests with higher priority than being serviced. level interrupt routine (with highest priority) will acknowledged first, then, when instruction executed, will interrupted level interrupt routine, which itself will interrupted level interrupt routine. When level interrupt routine completed, level interrupt routine resumes finally level interrupt routine. This results three interrupt serv-
routines being executed opposite order their priority. therefore recommended avoid inserting instruction interrupt service routine Concurrent mode. instruction only nested mode. WARNING: Concurrent Mode, interrupts nested executing interrupt service routine), make sure that either ENCSR CSR=ISR, otherwise iret innermost interrupt will make instead before outermost interrupt service routine terminated, thus making outermost routine fail.
Figure Complex Example Sequence Interrupt Requests with: Concurrent mode selected during interrupt service routine execution
Priority Level Interrupt Request
INTERRUP PRIORITY LEVEL INTERRUP PRIORITY LEVEL INTERRUP PRIORITY LEVEL INTERRUP PRIORITY LEVEL
MAIN
MAIN
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ARBITRATION MODES (Cont'd) 4.5.2 Nested Mode difference between Nested mode Concurrent mode, lies modification Current Priority Level (CPL) during interrupt processing. arbitration phase basically identical Concurrent mode, however, once request acknowledged, saved Nested Interrupt Control Register (NICR) setting NICR corresponding value (i.e. will set). then loaded with priority request just acknowledged; next arbitration cycle thus performed with reference priority interrupt service routine currently being executed. Start Interrupt Routine interrupt cycle performs following steps:
maskable interrupt requests disabled clearing CICR.IEN. saved special NICR stack hold priority level suspended routine. Priority level acknowledged routine stored CPL, that next request priority will compared with routine currently being serviced. byte pushed onto system stack. high byte pushed onto system stack. ENCSR set, pushed onto system stack. Flag register pushed onto system stack. loaded with 16-bit vector stored Vector Table, pointed IVR. ENCSR set, loaded with contents; otherwise used place until iret instruction.
Figure Simple Example Sequence Interrupt Requests with: Nested mode unchanged interrupt routinePriority Level Interrupt Request CPL=0 CPL6 CPL3: INT6 pending
INTE RRUPT PRIORITY LEVEL INTE RRUPT PRIORITY LEVEL INTE RRUPT PRIORITY LEVEL INTE RRUPT PRIORITY LEVEL INTE RRUPT PRIORITY LEVEL INTE RRUPT PRIORITY LEVEL
INT0 CPL=2
INT6 CPL=3
CPL=2
INT2 INT3 INT4 CPL=5
INT2 CPL=4
INT5
CPL2 CPL4: Serviced next
CPL=6 MAIN CPL=7
MAIN
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ARBITRATION MODES (Cont'd) Interrupt Routine iret Interrupt Return instruction executes following steps: Flag register popped from system stack. ENCSR set, popped from system stack. high byte popped from system stack. byte popped from system stack. unmasked Interrupts enabled setting CICR.IEN bit. priority level interrupted routine popped from special register (NICR) copied into CPL.
ENCSR reset, used instead ISR, unless program returns another nested routine. suspended routine thus resumes interrupted instruction. Figure contains simple example, showing that instruction used interrupt service routines, nested concurrent modes equivalent. Figure contains more complex example showing nested mode allows nested interrupt processing (enabled inside interrupt service routinesi using instruction) according their priority level.
Figure Complex Example Sequence Interrupt Requests with: Nested mode during interrupt routine execution
Priority Level Interrupt Request
INTERRUPT PRIORI LEVEL INTERRUPT PRIORI LEVEL
CPL=0 CPL6 CPL3: INT6 pending CPL=2 CPL=2
INTERRUPT PRIORI LEVEL INTERRUPT PRIORI LEVEL INTERRUPT PRIORI LEVEL INTERRUPT PRIORI LEVEL
INT0 CPL=2 INT2 INT3 INT4 CPL=5 INT5 MAIN
INT6 CPL=3
INT2 CPL=4 CPL=4 CPL=5 CPL=6 MAIN CPL=7
CPL2 CPL4: Serviced just after
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EXTERNAL INTERRUPTS standard core contains external interrupts sources grouped into four pairs. Table External Interrupt Channel Grouping
External Interrupt INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Channel INTD1 INTD0 INTC1 INTC0 INTB1 INTB0
Figure Priority Level ExamplePL2 PL1D PL2B PL1B PL2A PL1A
SOURCE PRIORITY
EIPLR
SOURCE PRIORITY
INT.D0: 100=4 INT.D1: 101=5 INT.C0: 000=0 INT.C1: 001=1
INT.A0: 010=2 INT.A1: 011=3 INT.B0: 100=4 INT.B1: 101=5 VR000151
INTA1 INTA0
Each source trigger control TEA0,.TED1 (R242,EITR.0,.,7 Page select triggering rising falling edge external pin. Trigger control "1", corresponding pending IPA0,.,IPD1 (R243,EIPR.0,.,7 Page input rising edge, cleared, pending falling edge input pin. Each source individually masked through corresponding control IMA0,.,IMD1 (EIMR.7,.,0). Figure priority level external interrupt sources programmed among eight priority levels with control register EIPLR (R245). priority level each pair software defined using bits PRL2, PRL1. each pair, even channel (A0,B0,C0,D0) group even priority level channel (A1,B1,C1,D1) (lower) priority level.
Figure shows example priority levels. Figure gives overview External interrupt control bits vectors. source interrupt channel selected between external INT0 (when IA0S "1", reset value) On-chip Timer/ Watchdog peripheral (when IA0S "0"). source interrupt channel selected between external INT2 (when (SPEN,BMS)=(0,0)) on-chip peripheral. source interrupt channel selected between external INT4 (when INTS "1") on-chip Standard Timer. source interrupt channel selected between external INT6 (when INT_SEL "0") on-chip RCCU. Warning: When using channels shared both external interrupts peripherals, special care must taken configure their control registers both peripherals interrupts. Table Multiplexed Interrupt SourceChannel INTA0 Internal Interrupt Source Timer/Watchdog External Interrupt Source INT0
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EXTERNAL INTERRUPTS (Cont'd) Figure External Interrupts Control Bits Vectorn
Watchdog/Timer IA0S count TEA0
VECTOR Priority level PL2A PL1A Mask IMA0 TEA1 VECTOR Priority level PL2A PL1A Mask IMA1
request
Pending IPA0
SPEN,BM TEB0 Interrupt
request
Pending IPA1
VECTO Priority level PL2B PL1B "0,0" Mask IMB0 TEB1 VECTOR Priority level PL2B PL1B Mask IMB1 INTS TEC0 Timer VECTO PL2C PL1C Priority level Mask IMC0 TEC1 VECTOR PL2C PL1C Priority level Mask IMC1 INT_SEL TED0 RCCU VECTOR PL2D PL1D Priority level Mask IMD0 TED1 VECTOR Priority level PL2D PL1D Mask IMD1
request
Pending IPB0
request
Pending IPB1
request
Pending IPC0
request
Pending IPC1
request
Pending IPD0
request
Pending IPD1
Shared channels, warning
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LEVEL INTERRUPT Level Interrupt channel assigned either external Timer/ Watchdog according status control EIVR.TLIS (R246.2, Page this high (the reset condition) source external NMI. low, source Timer/ Watchdog Count. When source external pin, control EIVR.TLTEV (R246.3; Page selects between rising set) falling reset) edge generating interrupt request. When selected event occurs, CICR.TLIP (R230.6) set. Depending mask situation, Level Interrupt request generated. kinds masks available, Maskable mask Non-Maskable mask. first mask CICR.TLI (R230.5): cleared enable disable respectively Level Interrupt request. enabled, global Enable Interrupt bit, CICR.IEN (R230.4) must also enabled order allow Level Request. second mask NICR.TLNM (R247.7) setonly mask. Once set, enables Level Interrupt request independently value CICR.IEN cannot cleared program. Only processor RESET cycle clear this bit. This does prevent user from ignoring some sources change TLIS. Level Interrupt Service Routine cannot interrupted other interrupt request, arbitration mode, even subsequent Level Interrupt request. Figure Level Interrupt Structure
Warning. interrupt machine cycle Level Interrupt does clear CICR.IEN bit, corresponding iret does Furthermore never modifies bits NICR register. ON-CHIP PERIPHERAL INTERRUPTS general structure peripheral interrupt unit described here, however each on-chip peripheral specific interrupt unit containing more interrupt channels, channels. Please refer specific peripheral chapter description interrupt features control registers. on-chip peripheral interrupt channels provide following control bits: Interrupt Pending (IP). hardware when Trigger Event occurs. set/ cleared software generate/cancel pending interrupts give status Interrupt polling. Interrupt Mask (IM). "0", interrupt request generated. ="1" interrupt request generated whenever CICR.IEN "1". Priority Level (PRL, bits). These bits define current priority level, PRL=0: highest priority, PRL=7: lowest priority (the interrupt cannot acknowledged) Interrupt Vector Register (IVR, bits). points vector table which itself contains interrupt routine start address.
WATCHDOG ENABLE WDEN
CORE RESET TLIP PENDING LEVEL INTERRUPT REQUEST
WATCHDOG TIMER COUNT
MASK TLIS
TLTEV TLNM
VA00294
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INTERRUPT RESPONSE TIME interrupt arbitration protocol functions completely asynchronously from instruction flow requires clock cycles. more CPUCLK cycle required when interrupt acknowledged. Requests sampled every CPUCLK cycles. interrupt request comes from external pin, trigger event must occur minimum INTCLK cycle before sampling time. When arbitration results interrupt request being generated, interrupt logic checks current instruction (which could stage execution) safely aborted; this case, instruction execution terminated immediately interrupt request serviced; not, waits until current instruction terminated then services request. Instruction execution normally aborted provided write operation been performed. interrupt deriving from external interrupt channel, response time between user event start interrupt service routine range from minimum clock cycles maximum clock cycles (DIV instruction), clock
cycles (DIVWS instructions) other instructions. non-maskable Level interrupt, response time between user event start interrupt service routine range from minimum clock cycles maximum clock cycles (DIV instruction), clock cycles (DIVWS instructions) other instructions. order guarantee edge detection, input signals must kept low/high minimum INTCLK cycle. interrupt machine cycle requires basic internal clock cycles (CPUCLK), which must added further clock cycles stack Register File. more clock cycles must further added pushed (ENCSR =1). interrupt machine cycle duration forms part examples interrupt response time previously quoted; includes time required push values stack, well interrupt vector handling. Wait Interrupt mode, further cycle required wake-up delay.
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4.10 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 Read/Write Register Group: System Reset value: 1000 0111 (87h)
GCEN TLIP CPL2 CPL1 CPL0
when interrupts disabled when peripheral generate interrupts. example, state known advance, value must restored from previous push CICR stack, sequence CICR make sure that interrupts being arbitrated when CICR modified. IAM: Interrupt Arbitration Mode. This cleared software. Concurrent Mode Nested Mode CPL[2:0]: Current Priority Level. These bits define Current Priority Level. CPL=0 highest priority. CPL=7 lowest priority. These bits modified directly interrupt hardware when Nested Interrupt Mode used. EXTERNAL INTERRUPT TRIGGER REGISTER (EITR) R242 Read/Write Register Page: Reset value: 0000 0000 (00h)
GCEN: Global Counter Enable. This enables 16-bit Multifunction Timer peripheral. disabled enabled TLIP: Level Interrupt Pending. This hardware when Level Interrupt (TLI) trigger event occurs. cleared hardware when acknowledged. also software implement software TLI. pending pending TLI: Level Interrupt. This cleared software. Level Interrupt generared when TLIP set, only TLNM=1 NICR register (independently value bit). Level Interrupt request generated when IEN=1 TLIP set. IEN: Interrupt Enable. This cleared interrupt machine cycle (except TLI). iret instruction (except return from TLI). instruction. cleared instruction. Maskable interrupts disabled Maskable Interrupts enabled Note: also changed software using instruction that operates register CICR, however this case, take care avoid spurious interrupts, since cannot cleared middle interrupt arbitration. Only modify
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
TED1: INTD1 Trigger Event TED0: INTD0 Trigger Event TEC1: INTC1 Trigger Event TEC0: INTC0 Trigger Event TEB1: INTB1 Trigger Event TEB0: INTB0 Trigger Event TEA1: INTA1 Trigger Event TEA0: INTA0 Trigger Event These bits cleared software. Select falling edge interrupt trigger event Select rising edge interrupt trigger event
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INTERRUPT REGISTERS (Cont'd) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 Read/Write Register Page: Reset value: 0000 0000 (00h)
IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0
IMB1: INTB1 Interrupt Mask IMB0: INTB0 Interrupt Mask IMA1: INTA1 Interrupt Mask IMA0: INTA0 Interrupt Mask These bits cleared software. Interrupt masked Interrupt masked interrupt generated IPxx bits EXTERNAL INTERRUPT PRIORITY REGISTER (EIPLR) R245 Read/Write Register Page: Reset value: 1111 1111 (FFh)
IPD1: INTD1 Interrupt Pending IPD0: INTD0 Interrupt Pending IPC1: INTC1 Interrupt Pending IPC0: INTC0 Interrupt Pending IPB1: INTB1 Interrupt Pending IPB0: INTB0 Interrupt Pending IPA1: INTA1 Interrupt Pending IPA0: INTA0 Interrupt Pending These bits hardware occurrence trigger event specified EITR register) cleared hardware interrupt acknowledge. They also software implement software interrupt. interrupt pending Interrupt pending EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR) R244 Read/Write Register Page: Reset value: 0000 0000 (00h)
LEVEL
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
PL2D, PL1D: INTD0, Priority Level. PL2C, PL1C: INTC0, Priority Level. PL2B, PL1B: INTB0, Priority Level. PL2A, PL1A: INTA0, Priority Level. These bits cleared software. priority three-bit value. fixed hardware Channels Channels
PL2x PL1x Hardware Priority (Highest) (Lowest)
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0
IMD1: INTD1 Interrupt Mask IMD0: INTD0 Interrupt Mask IMC1: INTC1 Interrupt Mask IMC0: INTC0 Interrupt Mask
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INTERRUPT REGISTERS (Cont'd) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 Read/Write Register Page: Reset value: xxxx 0110b (x6h)
TLTEV TLIS IAOS EWEN
WAITN disabled WAITN enabled stretch external memory access cycle). Note: more details Wait mode refer section describing WAITN External Memory Chapter. NESTED INTERRUPT CONTROL (NICR) R247 Read/Write Register Page: Reset value: 0000 0000 (00h)
TLNM
V[7:4]: Most significant nibble External Interrupt Vector. These bits initialized reset. representation full vector generated from V[7:4] selected external interrupt channel, refer Figure TLTEV: Level Trigger Event bit. This cleared software. Select falling edge trigger event Select rising edge trigger event TLIS: Level Input Selection. This cleared software. Watchdog Count interrupt source interrupt source IA0S: Interrupt Channel Selection. This cleared software. Watchdog Count INTA0 source External Interrupt INTA0 source EWEN: External Wait Enable. This cleared software.
TLNM: Level Maskable. This software cleared only hardware reset. Level Interrupt Maskable. level request generated IEN, TLIP bits Level Interrupt Maskable. level request generated TLIP HL[6:0]: Hold Level These bits hardware when, Nested Mode, interrupt service routine level interrupted from request with higher priority (other than Level interrupt request). They cleared hardware iret execution when routine level recovered.
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INTERRUPT REGISTERS (Cont'd) EXTERNAL MEMORY REGISTER (EMR2) R246 Read/Write Register Page: Reset value: 0000 1111 (0Fh)
ENCSR
Reserved, keep reset state. Refer external Memory Interface Chapter. ENCSR: Enable Code Segment Register. This cleared software. affects behaviour whenever interrupt request issued. works original compatibility mode. duration interrupt service routine, used instead CSR, interrupt stack frame identical that original ST9: only Flags pushed. This avoids saving stack event interrupt, thus ensuring faster
terrupt response time. drawback that possible interrupt service routine perform inter-segment calls jumps: these instructions would update CSR, which, this case, used (ISR used instead). code segment size interrupt service routines thus limited bytes. only used point interrupt vector table initialize beginning interrupt service routine: pushed onto stack together with flags, then loaded with contents ISR. this case, iret will also restore from stack. This approach allows interrupt service routines access entire Mbytes address space; drawback that interrupt response time slightly increased, because need also save stack. Full compatibility with original lost this case, because interrupt stack frame different; this difference, however, should affect vast majority programs.
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ON-CHIP DIRECT MEMORY ACCESS (DMA)
INTRODUCTION includes on-chip Direct Memory Access (DMA) order provide high-speed data transfer between peripherals memory Register File. Multi-channel fully supported peripherals having their controller channel(s). Each channel transfers data from contiguous locations Register File, Memory. maximum number bytes that transferred transaction each channel with Register File, 65536 with Memory. controller Peripheral uses indirect addressing mechanism Pointers Counter Registers stored Register File. This reason maximum number transactions Register File 222, since Registers allocated Pointer Counter. Register pairs used memory pointers counters order offer full 65536 byte count capability. Figure Data Transfer
REGISTER FILE REGISTER FILE MEMORY
PRIORITY LEVELS priority levels used interrupts also used prioritize requests, which arbitrated same arbitration phase interrupt requests. event occurrence requires transaction, this will take place current instruction execution. When interrupt request occur simultaneously, same priority level, request serviced before interrupt. interrupt priority request must strictly higher than value order acknowledged, whereas, transaction request, must equal higher than value order executed. Thus only transaction requests acknowledged when CPL=0. requests modify value, since transaction interruptable.
REGISTER FILE
GROUP PERIPHERAL PAGED REGISTERS
PERIPHERAL
COUNTER ADDRESS
DATA
COUNTER VALUE
TRANSFERRED DATA
START ADDRESS
VR001834
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ST90158 ON-CHIP DIRECT MEMORY ACCESS (DMA)
TRANSACTIONS purpose on-chip channel transfer block data between peripheral Register File, Memory. Each transfer consists three operations: load from/to peripheral data register from location Register File Memory) addressed through Address Register Register pair) post-increment Address Register Register pair) post-decrement transaction counter, which contains number transactions that have still performed. transaction carried between peripheral Register File (Figure 29), register required hold Address, hold transaction counter. These registers must located Register File: Address Register even addreregister, Transaction Counter next register (odd address). They pointed Transaction Counter Pointer Register (DCPR), located peripheral's paged registers. order select transaction with Register File, control DCPR.RM (bit DCPR) must set. transaction made between peripheral Memory, register pair bits) required Address Transaction Counter (Figure 30). Thus, register pairs must located Register File. Transaction Counter pointed Transaction Counter Pointer Register (DCPR), Address pointed Address Pointer Register (DAPR),both DCPR DAPR located paged registers peripheral.
Figure Between Register File Peripheral
IDCR DAPR DCPR DATA PERIPHERAL PAGED REGISTERS TRANSACTION
PAGED REGISTERS
0100h
BLOCK INTERRUPT SERVICE ROUTINE
SYSTEM REGISTERS
0000h
ADDRESS
VECTOR TABLE
MEMORY
TABLE
DATA ALREADY TRANSFERRED
COUNTER ADDRESS REGISTER FILE
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ST90158 ON-CHIP DIRECT MEMORY ACCESS (DMA)
TRANSACTIONS (Cont'd) When selecting transaction with memory, DCPR.RM (bit DCPR) must cleared. select between using DMASR register extend address, (see Memory Management Unit chapter), control DAPR.PS (bit DAPR) must cleared respectively. transaction Counter must initialized with number transactions perform will decremented after each transaction. Address must initialized with starting address table increased after each transaction. These registers must located between addresses Register File. Once channel initialized, transfer start. direction transfer automatically defined type peripheral programming mode. Once table completed (the transaction counter reaches value), Interrupt request generated. Figure Between Memory Peripheral
IDCR DAPR DCPR DATA PERIPHERAL PAGED REGISTERS
When Interrupt Pending (IP) hardware event software), Mask (DM) set, request generated. Priority Level source higher than, equal Current Priority Level (CPL), transfer executed current instruction. transfers read/write data from/to location pointed Address Register, Address register incremented Transaction Counter Register decremented. When contents Transaction Counter decremented zero, Mask (DM) cleared interrupt request generated, according Interrupt Mask (End Block interrupt). This End-of-Block interrupt request taken into account, depending value. WARNING. requests acknowledged level interrupt service progress.
TRANSACTION
PAGED REGISTERS TABLE SYSTEM REGISTERS
DATA ALREADY TRANSFERRED
TRANSACTION COUNTER
BLOCK INTERRUPT SERVICE ROUTINE
0100h
ADDRESS
0000h
ADDRESS MEMORY
VECTOR TABLE
REGISTER FILE
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ST90158 ON-CHIP DIRECT MEMORY ACCESS (DMA)
TRANSACTIONS (Cont'd) CYCLE TIME interrupt arbitration protocol functions completely asynchronously from instruction flow. Requests sampled every CPUCLK cycles. transactions executed their priority allows transfer with Register file requires CPUCLK cycles. transfer with memory requires CPUCLK cycles, plus required wait states. SWAP MODE extra feature which found channels some peripherals (e.g. MultiFunction Timer) Swap mode. This feature allown
transfer from tables alternatively. descriptors Register File thus doubled. transaction counters address pointers allow definition fully independent tables (they only have belong same space, Register File Memory). transaction programmed start tables (say table and, block, controller automatically swaps other table (table pointing other descriptors. this case, mask bit) control cleared, Block interrupt request generated allow optional updating first data table (table Until swap mode disabled, controller will continue swap between Table Table
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ST90158 ON-CHIP DIRECT MEMORY ACCESS (DMA)
REGISTERS each peripheral channel specific control registers, following register list should considered general example. names register allocations shown here different from those found peripheral chapters. COUNTER POINTER REGISTER (DCPR) Read/Write Address Peripheral Reset value: undefined
block Interrupt Mask. This cleared software. block interrupt request generated when Block interrupt generated when set. requests depend value shown table below.
Meaning request generated without Block interrupt when IP=1 request generated with Block terrupt when IP=1 block interrupt request generated when IP=1 block Interrupt generated without associated request (not used)
C[7:1]: Transaction Counter Pointer. Software should write pointer Transaction Counter these bits. Register File/Memory Selector. This cleared software. transactions with memory (see also DAPR.DP) transactions with Register File GENERIC EXTERNAL PERIPHERAL INTERRUPT CONTROL (IDCR) Read/Write Address Peripheral Reset value: undefined
PRL2 PRL1 PRL0
PRL[2:0]: Source Priority Level. These bits cleared software. Refer Section PRIORITY LEVELS description priority levels.
PRL2 PRL1 PRL0 Source Priority Level Highest Lowest
ADDRESS POINTER REGISTER (DAPR) Read/Write Address Peripheral Reset value: undefined
Interrupt Pending. This hardware when Trigger Event occurs. cleared hardware when request acknowledged. set/cleared software order generate/cancel pending request. interrupt pending Interrupt pending Request Mask. This cleared software. also cleared when transaction counter reaches zero (unless SWAP mode active). request generated when set. request generated when
A[7:1]: Address Register(s) Pointer Software should write pointer Address Register(s) these bits. Memory Segment Pointer Selector: This cleared software. only meaningful DAPR.RM=0. register used extend address data transferred (see chapter). DMASR register used extend address data transferred (see chapter).
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ST90158 RESET CLOCK CONTROL UNIT (RCCU)
RESET CLOCK CONTROL UNIT (RCCU)
INTRODUCTION Reset Clock Control Unit (RCCU) comprises distinct sections: Clock Control Unit, which generates manages internal clock signals. Reset/Stop Manager, which detects flags Hardware, Software Watchdog generated resets. devices where external Stop available, this circuit also detects manages externally triggered Stop mode, during which oscillators frozen order achieve lowest possible power consumption. CLOCK CONTROL UNIT multiplying clock frequency factor multiplied clock then divided programmable divider, factor this means, operate with cheaper, medium frequency (3-5 MHz) crystals, while still providing high frequency internal clock maximum system performance; range available multiplication division factors allow great number operating clock frequencies derived from single crystal frequency. power operation, especially Wait Interrupt mode, Clock Multiplier unit turned off, whereupon output clock signal programmed CLOCK2 divided further power reduction, frequency external clock connected CK_AF selected, whereupon crystal controlled main oscillator turned off. internal system clock, INTCLK, routed on-chip peripherals, well programmable Clock Prescaler Unit which generates clock core (CPUCLK). Clock Prescaler programmable slow clock factor allowing programmer reduce processing speed, thus power consumption, while maintaining high speed clock peripherals. This particularly useful when little actual processing being done peripherals doing most work.
Clock Control Unit generates internal clocks core (CPUCLK) onchip peripherals (INTCLK). Clock Control Unit driven external crystal circuit, connected OSCIN OSCOUT pins, external pulse generator, connected OSCIN (see Figure Figure 39). 6.2.1 Clock Control Unit Overview shown Figure programmable divider divide CLOCK1 input clock signal two. divide-by-two recommended order ensure duty cycle signal driving multiplier circuit. resulting signal, CLOCK2, reference input clock programmable Phase Locked Loop frequency multiplier, which capaFigure Clock Control Unit Simplified Block Diagram
1/16
CLOCK2/64 Standard Timer
Quartz oscillator
CLOCK1
CLOCK2
Clock Multiplier /Divider Unit
Clock Prescaler
CPUCLK Core
CK_AF source
INTCLK Peripherals CK_AF
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ST90158 RESET CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT various programmable features operating modes handled four registers: MODER (Mode Register) CLK_FLAG (Clock Flag Register) This System Register (R235, Group This Paged Register (R242, Page 55). input clock divide-by-two clock prescaler factors handled this register. CLKCTL (Clock Control Register) This Paged Register (R240, Page 55). power modes interpretation HALT instruction handled this register. This register contains various status flags, well control bits clock selection. PLLCONF (PLL Configuration Register) This Paged Register (R246, Page 55). multiplication division factors programmed this register.
Figure Clock Control Unit Programming
XTSTOP
(CLK_FLAG)
DIV2
(MODER)
CSU_CKSEL
(CLK_FLAG)
CKAF_SEL
(CLKCTL)
1/16
Quartz oscillator
CLOCK1
CLOCK2
6/8/10/14
INTCLK
Peripherals Clock Prescaler
CK_AF source
CK_AF
MX(1:0)
DX(2:0)
XT_DIV16
CKAF_ST
(PLLCONF)
(CLK_FLAG)
Wait Interrupt Power Modes: LPOWFI (CLKCTL) selects Power operation automatically entering mode. WFI_CKSEL (CLKCTL) selects CK_AF clock automatically, present, entering mode. XTSTOP (CLK_FLAG) automatically stops Xtal oscillator when CK_AF clock present selected.
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ST90158 RESET CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont'd) 6.3.1 Clock Multiplier Programming CLOCK1 signal generated oscillator drives programmable divide-by-two circuit. DIV2 control MODER (Reset Condition), CLOCK2, equal CLOCK1 divided two; DIV2 reset, CLOCK2 identical CLOCK1. Since input clock Clock Multiplier circuit requires duty cycle correct operation, divide circuit should enabled when crystal oscillator used, when external clock generator does provide duty cycle. practice, divide-by-two virtually always used order ensure duty cycle signal multiplier circuit. When active, multiplies CLOCK2 depending status bits PLLCONF. multiplied clock then divided factor range determined status DX0-2 bits; when these bits programmed 111, switched off. Following RESET phase, programming bits DX0-2 value different from will turn After allowing stabilisation period PLL, setting CSU_CKSEL CLK_FLAG Register selects multiplier clock. maximum frequency allowed INTCLK operation, operation. Care required, when programming multiplier divider factors, exceed maximum permissible operating frequency INTCLK, according supply voltage. being static machine, there lower limit INTCLK. However, below 1MHz, converter precision present) decreases. 6.3.2 Clock Prescaling system clock, INTCLK, which output clock multiplier, CLOCK2, CLOCK2/ CK_AF, drives programmable prescaler which generates basic time base, CPUCLK, instruction executer core. This allows user slow down program execution during processor intensive routines, thus reducing power dissipation. internal peripherals affected CPUCLK prescaler continue operate full INTCLK frequency. This particularly useful
when little processing being done peripherals doing most work. prescaler divides input clock value programmed control bits PRS2,1,0 MODER register. prescaler value zero, prescaling takes place, thus CPUCLK same period phase INTCLK. value different from prescaling equal value plus one, ranging thus from (PRS2,1,0 eight (PRS2,1,0 clock generated shown Figure will noted that prescaling clock does preserve duty cycle, since high level stretched replace missing cycles. This analogous introduction wait cycles access external memory. When External Memory Wait Request events occur, CPUCLK stretched high level whole period required function. Figure Clock Prescaling
INTCLK
VALUE CPUCLK VA00260
6.3.3 Peripheral Clock system clock, INTCLK, which output clock multiplier, CLOCK2, CLOCK2/ CK_AF, also routed on-chip peripherals acts central timebase timing functions.
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ST90158 RESET CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont'd) 6.3.4 Power Modes user select automatic slowdown clock frequency during Wait Interrupt operation, thus idling power mode while waiting interrupt. operation clock core (CPUCLK) stopped, thus suspending program execution, while clock peripherals (INTCLK) programmed described following paragraphs. examples Power operation illustrated Figure Figure power operation during disabled (LPOWFI CLKCTL Register), stopped INTCLK unchanged. power operation during Wait Interrupt enabled (LPOWFI CLKCTL Register), soon executes instruction, turned system clock will forced CLOCK2 divided external frequency clock, CK_AF, this been selected setting WFI_CKSEL, providing CKAF_ST set, thus indicating that external clock selected actually present CK_AF pin. external clock source used, crystal oscillator stopped setting XTSTOP bit, providing that CK_AK clock present selected, indicated CKAF_ST being set. crystal oscillator will stopped automatically
tering WFI_CKSEL been set. should noted that selecting non-existent CK_AF clock source impossible, since such selection requires that auxiliary clock source actually present selected. event non-existent clock source selected inadvertently. user program switch back faster clock occurrence interrupt, taking care respect oscillator stabilisation delays, appropriate. should noted that power modes also selected explicitly user program even when Wait Interrupt mode, setting appropriate bits. 6.3.5 Interrupt Generation System clock selection modifies CLKCTL CLK_FLAG registers. clock control unit generates external interrupt request when CK_AF CLOCK2/16 selected deselected system clock source, well when system clock restarts after hardware stop (when STOP MODE feature available specific device). This interrupt masked resetting INT_SEL CLKCTL register. Note that this only case where interrupt generated with high transition.
Table Summary Operating Modes using main Crystal Controlled Oscillator
MODE SLOW SLOW WAIT INTERRUPT POWER WAIT INTERRUPT RESET EXAMPLE XTAL=4.4 INTCLK XTAL/2 (14/D) XTAL/2 (10/D) XTAL/2 (8/D) XTAL/2 (6/D) XTAL/2 XTAL/32 CPUCLK INTCLK/N INTCLK/N INTCLK/N INTCLK/N INTCLK/N INTCLK/N DIV2 PRS0-2 CSU_CKSEL MX1-0 DX2-0 LPOWFI XT_DIV16
LPOWFI=0, changes occur INTCLK, CPUCLK stopped anyway. XTAL/32 XTAL/2 2.2*10/2 11MHz STOP INTCLK
11MHz
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ST90158 RESET CLOCK CONTROL UNIT (RCCU)
Figure Example Power mode programming using CK_AF external clock
PROGRAM FLOW INTCLK FREQUENCY
FXtal MHz,
Begi
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