PM4318 OCTLIU OCTAL E1/T1/J1 LINE INTERFACE DEVICE PM4318
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PM4318
OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
DATASHEET
PROPRIETARY CONFIDENTIAL PRELIMINARY ISSUE APRIL 2001
PMC-Sierra, Inc.
8555 Baxter Place Burnaby, Canada .415.6000
PRELIMINARY DATASHEET PMC- 2001578 ISSUE
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
CONTENTS FEATURES. EACH RECEIVER SECTION: EACH TRANSMITTER SECTION:.
APPLICATIONS. REFERENCES APPLICATION EXAMPLES. BLOCK DIAGRAM. DESCRIPTION DIAGRAM. DESCRIPTION. FUNCTIONAL DESCRIPTION 1.10 1.11 1.12 1.13 OCTANTS. RECEIVE INTERFACE CLOCK DATA RECOVERY (CDRC). RECEIVE JITTER ATTENUATOR (RJAT) INBAND LOOPBACK CODE DETECTOR (IBCD) PULSE DENSITY VIOLATION DETECTOR (PDVD) PERFORMANCE MONITOR COUNTERS (PMON). PSEUDO RANDOM BINARY SEQUENCE GENERATION DETECTION (PRBS) INBAND LOOPBACK CODE GENERATOR (XIBC). PULSE DENSITY ENFORCER (XPDE). TRANSMIT JITTER ATTENUATOR (TJAT) LINE TRANSMITTER. TIMING OPTIONS (TOPS)
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
1.14
SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE 1.14.1 INTERFACING OCTLIUS HIGH DENSITY FRAMER.
1.15 1.16 1.17 1.18 1.19 1.20
EXTRACTER PISO. INSERTER SIPO CLK/DATA CONVERTER SERIAL PROM INTERFACE. JTAG TEST ACCESS PORT. MICROPROCESSOR INTERFACE
NORMAL MODE REGISTER DESCRIPTION NORMAL MODE REGISTER MEMORY MAP.
TEST FEATURES DESCRIPTION. JTAG TEST PORT.
OPERATION. CONFIGURING OCTLIU FROM RESET. SERVICING INTERRUPTS. USING PERFORMANCE MONITORING FEATURES USING TRANSMIT LINE PULSE GENERATOR USING LINE RECEIVER USING PRBS GENERATOR DETECTOR LOOPBACK MODES 4.7.1 4.7.2 LINE LOOPBACK. DIAGNOSTIC DIGITAL LOOPBACK
JTAG SUPPORT 4.8.1 CONTROLLER
FUNCTIONAL TIMING INTERFACE TIMING
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
LINE CODE VIOLATION INSERTION ALARM INTERFACE.
ABSOLUTE MAXIMUM RATINGS D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS OCTLIU TIMING CHARACTERISTICS. 9.10 RSTB TIMING (FIGURE XCLK INPUT TIMING (FIGURE 34). TRANSMIT SERIAL INTERFACE (FIGURE RECEIVE SERIAL INTERFACE (FIGURE 36). INTERFACE (FIGURE FIGURE 39). SERIAL PROM (SPI) INTERFACE (FIGURE ALARM INTERFACE (FIGURE 41). INGRESS CLK/DATA INTERFACE (FIGURE 42). EGRESS CLK/DATA INTERFACE (FIGURE JTAG PORT INTERFACE (FIGURE
ORDERING THERMAL INFORMATION MECHANICAL INFORMATION
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
LIST FIGURES FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE T1/E1 FRAMER/TRANSCEIVER APPLICATION. HIGH DENSITY T1/E1 FRAMER/TRANSCEIVER APPLICATION HIGH DENSITY LEASED LINE CIRCUIT EMULATION APPLICATION. METRO OPTICAL ACCESS EQUIPMENT OCTLIU BLOCK DIAGRAM LIUS ENABLED OCTLIU BLOCK DIAGRAM CLK/DATA CONVERTER, LIUS DISABLED DIAGRAM. EXTERNAL ANALOGUE INTERFACE CIRCUITS JITTER TOLERANCE COMPLIANCE WITH ITU-T SPECIFICATION G.823 INPUT JITTER TJAT JITTER TOLERANCE TJAT MINIMUM JITTER TOLERANCE XCLK ACCURACY. TJAT JITTER TRANSFER. FRAMER LINE SIDE INTERFACE SERIAL PROM CASCADE INTERFACE SERIAL PROM COMMAND FORMAT TRANSMIT TIMING OPTIONS. LINE LOOPBACK. DIAGNOSTIC DIGITAL LOOPBACK. BOUNDARY SCAN ARCHITECTURE CONTROLLER FINITE STATE MACHINE INPUT OBSERVATION CELL (IN_CELL) OUTPUT CELL (OUT_CELL) ENABLE CELL (ENABLE). BIDIRECTIONAL CELL (IO_CELL)
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE
LAYOUT OUTPUT ENABLE BIDIRECTIONAL CELLS FUNCTIONAL TIMING B8ZS LINE CODE VIOLATION INSERTION HDB3 LINE CODE VIOLATION INSERTION. LINE CODE VIOLATION INSERTION ALARM SERIAL OUTPUT. MICROPROCESSOR INTERFACE READ TIMING. MICROPROCESSOR INTERFACE WRITE TIMING RSTB TIMING. XCLK INPUT TIMING TRANSMIT SERIAL INTERFACE TIMING DIAGRAM. RECEIVE SERIAL INTERFACE TIMING DIAGRAM FRAME PULSE TIMING. TIMING DROP TIMING INTERFACE TIMING ALARM INTERFACE TIMING. INGRESS CLK/DATA INTERFACE TIMING DIAGRAM. EGRESS CLK/DATA INTERFACE TIMING DIAGRAM. JTAG PORT INTERFACE TIMING
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE EXTERNAL COMPONENT DESCRIPTIONS SERIAL PROM COMMANDS CODE BITS SERIAL PROM SPECIAL COMMANDS NORMAL MODE REGISTER MEMORY CLOCK SYNTHESIS MODE TJAT FIFO OUTPUT CLOCK SOURCE TJAT SOURCE. INSBI TRIBUTARY CHARACTERISTICS EXSBI TRIBUTARY CHARACTERISTICS. EXSBI CLOCK GENERATION OPTIONS. TRANSMIT IN-BAND CODE LENGTH LOOPBACK CODE CONFIGURATIONS. LOSS SIGNAL THRESHOLDS TRANSMIT OUTPUT AMPLITUDE ALOS DETECTION/CLEARANCE THRESHOLDS. EQUALIZATION FEEDBACK FREQUENCIES. VALID PERIOD. BOUNDARY SCAN REGISTER. DEFAULT SETTINGS. T1.102 TRANSMIT WAVEFORM VALUES LONG HAUL (LBO DB)175 T1.102 TRANSMIT WAVEFORM VALUES LONG HAUL (LBO T1.102 TRANSMIT WAVEFORM VALUES LONG HAUL (LBO T1.102 TRANSMIT WAVEFORM VALUES LONG HAUL (LBO 22.5
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE
T1.102 TRANSMIT WAVEFORM VALUES SHORT HAUL FT.) T1.102 TRANSMIT WAVEFORM VALUES SHORT HAUL (110 FT.) T1.102 TRANSMIT WAVEFORM VALUES SHORT HAUL (220 FT.) T1.102 TRANSMIT WAVEFORM VALUES SHORT HAUL (330 FT.). T1.102 TRANSMIT WAVEFORM VALUES SHORT HAUL (440 FT.) T1.102 TRANSMIT WAVEFORM VALUES SHORT HAUL (550 FT.) TR62411 TRANSMIT WAVEFORM VALUES LONG HAUL (LBO TR62411 TRANSMIT WAVEFORM VALUES SHORT HAUL FT.)186 TR62411 TRANSMIT WAVEFORM VALUES SHORT HAUL (110 FT.) TR62411 TRANSMIT WAVEFORM VALUES SHORT HAUL (220 FT.) TR62411 TRANSMIT WAVEFORM VALUES SHORT HAUL (330 FT.) TR62411 TRANSMIT WAVEFORM VALUES SHORT HAUL (440 FT.) TR62411 TRANSMIT WAVEFORM VALUES SHORT HAUL (550 FT.) TRANSMIT WAVEFORM VALUES OHM. TRANSMIT WAVEFORM VALUES OHM. RLPS REGISTER PROGRAMMING. RLPS EQUALIZER TABLE MODE) RLPS EQUALIZER TABLE MODE) RLPS EQUALIZER TABLE (MONITOR MODE) ABSOLUTE MAXIMUM RATINGS
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE
D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE READ ACCESS MICROPROCESSOR INTERFACE WRITE ACCESS. RTSB TIMING. XCLK INPUT TIMING TRANSMIT SERIAL INTERFACE RECEIVE SERIAL INTERFACE. CLOCKS FRAME PULSE DROP INTERFACE. ALARM INTERFACE INGRESS CLK/DATA INTERFACE ENGRESS CLK/DATA INTERFACE. JTAG PORT INTERFACE. ORDERING INFORMATION OCTLIU THETA OCTLIU JUNCTION TEMPERATURE OCTLIU THETA AIRFLOW
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viii
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
FEATURES Monolithic device which integrates eight T1/J1 short haul long haul line interface circuits. Software switchable between T1/J1 operation per-device basis. Meets exceeds T1/J1 shorthaul longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T 62411, ITU-T G.703, G.704 well ETSI 300-011, CTR-4, CTR12 CTR-13. Provides encoding decoding B8ZS, HDB3 line codes. Provides receive equalization, clock recovery line performance monitoring. Provides transmit receive jitter attenuation. Provides digitally programmable long haul short haul line build out. Provides selectable, channel independent de-jittered recovered clock system timing redundancy. Provides PRBS generators detectors each tributary error testing rates recommended ITU-T O.151. Provides either serial clock/data parallel Scaleable Bandwidth Interconnect (SBI) interfaces system side. configured converter between interfaces serial clock/data. this mode, LIUs unused. Provides 8-bit microprocessor interface configuration, control, status monitoring. Provides hardware-only microprocessor) mode which configuration data read from SPIcompatible serial PROM. PROM interface cascaded such that multiple OCTLIU devices configured simultaneously from single PROM. Uses line rate system clock. Provides IEEE 1149.1 (JTAG) compliant Test Access Port (TAP) controller boundary scan test. Implemented power tolerant 1.8/3.3 CMOS technology. Available high density 288-pin Tape-SBGA package. Provides -40°C +85°C Industrial temperature operating range.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Each Receiver Section: Supports signal reception distances with cable attenuation nominal conditions using gauge cable emulation. Supports signal reception distances with cable attenuation nominal conditions using gauge cable emulation. Supports G.772 compliant non-intrusive protected monitoring points. Recovers clock data using digital phase locked loop high jitter tolerance. Tolerates more than peak-to-peak; high frequency jitter required AT&T 62411 Bellcore TR-TSY-000170. Outputs either dual rail recovered line pulses, single rail DS-1/E1 signal parallel data format. Performs B8ZS decoding when processing bipolar DS-1 signal HDB3 decoding when processing bipolar signal. Detects line code violations (LCVs), B8ZS/HDB3 line code signatures, (E1+HDB3), (T1+B8ZS) (AMI) successive zeros. Accumulates 8191 line code violations (LCVs), performance monitoring purposes, over accumulation intervals defined period between software write accesses register. Detects loss signal (LOS), which defined successive zeros. Detects programmable inband loopback activate deactivate code sequences received data stream when they present seconds. Optionally, enters loopback mode automatically detection inband loopback code. Detects violations ANSI T1.403 12.5% pulse density rule over moving 192-bit window. pseudo-random sequence user selectable from detected T1/E1 stream either receive transmit directions. detector counts pattern errors using 24-bit saturating PRBS error counter. Each Transmitter Section: Supports transfer transmitted single rail signaling data from 1.544 Mbit/s 2.048 Mbit/s backplane buses. Generates DSX-1 shorthaul DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI requirements. Generates pulses compliant G.703 recommendations.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Provides digitally programmable pulse shape extending transmitted periods custom long haul pulse shaping applications. Provides line outputs that current limited tristated protection redundant applications. Provides digital phase locked loop generation jitter transmit clock complying with jitter attenuation, jitter transfer residual jitter specifications AT&T 62411 ETSI Provides FIFO buffer jitter attenuation rate conversion transmit path. Allows bipolar violation (BPV) transparent operation error restoring regenerator applications. Allows bipolar violation (BPV) insertion diagnostic testing purposes. Supports ones transmission alarm indication signal (AIS) generation. Accepts either dual rail single rail DS-1/E1 signals parallel data from interface. Performs B8ZS encoding when processing single rail SBI-sourced DS-1 signal HDB3 encoding when processing single rail SBI-sourced signal. pseudo-random sequence user selectable from inserted into detected from stream either receive transmit directions. Detects violations ANSI T1.403 12.5% pulse density rule over moving 192-bit window optionally stuffs ones maintain minimum ones density. Supports transmission programmable unframed inband loopback code sequence.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
APPLICATIONS Metro Optical Access Equipment Edge Router Linecards Multiservice ASwitch Linecards Base Station Controllers (BSC) Base Transceiver Stations (BTS) Digital Private Branch Exchanges (PBX) Digital Access Cross-Connect Systems (DACS) Electronic Cross-Connect Systems (EDSX) T1/E1 Repeaters Test Equipment clk/data converter multi-service access equipment.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
REFERENCES ANSI T1.102-1993 American National Standard Telecommunications Digital Hierarchy Electrical Interfaces. ANSI T1.107-1995 American National Standard Telecommunications Digital Hierarchy Formats Specification. ANSI T1.403-1999 American National Standard Telecommunications Carrier Customer Installation DS-1 Metallic Interface Specification. ANSI T1.408-1990 American National Standard Telecommunications Integrated Services Digital Network (ISDN) Primary Rate Customer Installation Metallic Interfaces Layer Specification. AT&T 62411 Accunet T1.5 Service Description Interface Specification, December 1990. AT&T 62411 Accunet T1.5 Service Description Interface Specification, Addendum March 1991. AT&T 62411 Accunet T1.5 Service Description Interface Specification, Addendum October 1992. TR-TSY-000170 Bellcore Digital Cross-Connect System Requirements Objectives, Issue November 1985. TR-N1WT-000233 Bell Communications Research Wideband Broadband Digital Cross-Connect Systems Generic Criteria, Issue November 1993. TR-NWT-000303 Bell Communications Research Integrated Digital Loop Carrier Generic Requirements, Objectives, Interface, Issue December, 1992. TR-TSY-000499 Bell Communications Research Transport Systems Generic Requirements (TSGR): Common Requirement, Issue December, 1993. ETSI ISDN Primary Rate User-Network Interface Specification Test Principles, 1992. ETSI Access Digital Section ISDN Primary Rates. ETSI Integrated Services Digital Network (ISDN); Attachment requirements terminal equipment connect ISDN using ISDN primary rate access, November 1995. ETSI Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; kbit/s digital unstructured leased lines (D2048U) Attachment requirements terminal equipment interface, December 1993. ETSI Business Telecommunications (BTC); kbit/s digital structured leased lines (D2048S); Attachment requirements terminal equipment interface, January 1996.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Rules Part 68.308 Signal Power Limitations. ITU-T Recommendation G.703 Physical/Electrical Characteristics Hierarchical Digital Interface, Geneva, 1998. ITU-T Recommendation G.704 Synchronous Frame Structures Used Primary Hierarchical Levels, July 1998. ITU-T Recommendation G.772 Protected Monitoring Points Provided Digital Transmission Systems, 1992. ITU-T Recommendation G.775 Loss Signal (LOS), November 1998. ITU-T Recommendation G.823, Control Jitter Wander Within Digital Networks Which Based 2048 kbit/s Hierarchy, 1993. ITU-T Recommendation I.431 Primary Rate User-Network Interface Layer Specification, 1993. ITU-T Recommendation O.151, Error Performance Measuring Equipment Digital Systems Primary Rate Above, 1992. Standard JT-G703 Physical/Electrical Characteristics Hierarchical Digital Interfaces, 1995. Standard JT-G704 Frame Structures Primary Secondary Hierarchical Digital Interfaces, 1995. Standard JT-I431 ISDN Primary Rate User-Network Interface Layer Specification, 1995. Nippon Telegraph Telephone Corporation Technical Reference High-Speed Digital Leased Circuit Services, Third Edition, 1990.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
APPLICATION EXAMPLES Figure T1/E1 Framer/Transceiver Application
Clock Data lines
OCTLIU
PM4318
TOCTL
PM4388
Octal Framer
Backplane
Clock Data lines
OCTLIU
PM4318
EOCTL
PM6388
Octal Framer
Backplane
Figure
High Density T1/E1 Framer/Transceiver Application
H-MVIP
T1/J1 lines
OCTLIU OCTLIU OCTLIU OCTLIU PM4318
PM4318 PM4318 PM4318
TE32
PM4332
T1/J1/E1 Framer
4xOCTLIU
Figure
High Density Leased Line Circuit Emulation Application
T1/J1 lines
OCTLIU OCTLIU OCTLIU OCTLIU PM4318
PM4318 PM4318 PM4318
Utopia
AAL1gator
PM73122
AAL1
ABackbone
4xOCTLIU
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure
Metro Optical Access Equipment
Telecom
T1/J1 lines
OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU OCTLIU PM4318
PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318 PM4318
TEMAP-84
PM5366
T1/E1 VT/TU Mapper Cross Connect
11xOCTLIU 8xOCTLIU
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Figure BLOCK DIAGRAM
DATASHEET
PMC- 2001578
PRELIMINARY
TXTIP1[8:1] TXTIP2[8:1] TDN[8:1] TDP[8:1] TCLK[8:1] TJAT Digital Jitter Attenuator LCODE B8ZS HDB3 Line Encoder XPDE Pulse Density Enforcer XIBC Inband Loopback Code Generator
TXRING1[8:1] TXRING2[8:1]
XLPG Transmit
ISSUE
EXSBI-8 Extract PMON Performance Monitor (Line Loopback) PRBS Pattern Generator Detector
ADATA[7:0] REFCLK AC1FP DC1FP C1FPOUT
(Diagnostic Digital Loopback)
INSBI-8 Insert
DDATA[7:0] DACTIVE RDP[8:1] RDN/RLCV[8:1] RCLK[8:1]
RXTIP[8:1] CDRC Clk/Data Recovery PDVD Pulse Density Viol. Detector RJAT Digital Jitter Attenuator
OCTLIU Block Diagram LIUs Enabled
RXRING[8:1]
RLPS Receive
IBCD Inband Loop back Code Detector
Octant
SBI2CLK SBI_EN RSTB VCLK FBLOW only Auto-config
XCLK JTAG Interface
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TOPS Timing Options Serial Output INTB D[7:0] A[10:0] SRCEN SRCDO SRDI SREN SRDO TRSTB SRCLK SRCCLK LEN8[2:0] LEN7[2:0] LEN6[2:0] LEN5[2:0] LEN4[2:0] LEN3[2:0] LEN2[2:0] LEN1[2:0] LOS_L1 SRCASC SRCODE HW_ONLY
RSYNC
Clock Synthesis Distribution
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PM4318 OCTLIU
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure
OCTLIU Block Diagram Clk/Data Converter, LIUs Disabled
DDATA[7:0] ADATA[7:0]
C1FPOUT
DACTIVE
REFCLK AC1FP DC1FP
SBI2CLK
SBI_EN
VCLK
RSTB
_ONLY SRCODE Extract Insert EXSBI-8 INSBI-8 SRCEN only Auto-config SRCCLK SRCDO SRCASC SREN SRCLK SRDI SRDO Elastic Store ELST
INTB Interface A[10:0] D[7:0]
TRSTB Clock Synthesis Distribution JTAG
ECLK
ICLK_IN IFP_IN IDATA[8:1]
ICLK_OUT IFP_OUT
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EDATA[8:1]
XCLK
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
DESCRIPTION PM4318 Octal E1/T1/J1 Line Interface Device (OCTLIU) monolithic integrated circuit suitable long haul short haul systems with minimum external circuitry. OCTLIU configurable microprocessor control SPI-compatible serial PROM interface, allowing feature selection without changes external wiring. Analogue circuitry provided allow direct reception long haul compatible signals with cable loss 1.024 MHz) mode cable loss kHz) mode using minimum external components. Typically, only line protection, transformer line termination resistor required. OCTLIU recovers clock data from line. Decoding AMI, HDB3 B8ZS line codes supported. mode, OCTLIU also detects presence in-band loop back codes. OCTLIU supports detection loss signal, pulse density violation line code violation alarm conditions. Line code violations accumulated performance monitoring purposes. Internal analogue circuitry allows direct transmission long haul short haul compatible signals using minimum external components. Typically, only line protection, transformer optional line termination resistor required. Digitally programmable pulse shaping allows transmission DSX-1 compatible signals feet from cross-connect, short haul pulses into twisted pair coaxial cable, long haul pulses into twisted pair well long haul DS-1 pulses into twisted pair with integrated support filtering required rules. addition, programmable pulse shape extending over 5-bit periods allows customization short haul long haul line interface circuits application requirements. Each channel OCTLIU generate jitter transmit clock from input clock source also provide jitter attenuation receive path. jitter recovered clock routed outside OCTLIU network timing applications. Serial interfaces each T1/E1 allow 1.544 Mbit/s 2.048 Mbit/s backplane receive/backplane transmit system interfaces directly supported. Data transferred either dual rail line pulses single rail DS-1/E1 data. Alternatively, OCTLIU supports 8-bit parallel interface interfacing high-density framers. OCTLIU configured operate mode which LIUs disabled device acts converter between interface serial clock data. serial data streams (sharing common clock frame pulse) mapped this mode. OCTLIU configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. Alternatively, device operated `hardware only' mode which microprocessor required. this case, OCTLIU reads configuration information from SPI-compatible serial PROM interface power Multiple OCTLIUs configured from single serial PROM cascade interface OCTLIU.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
DIAGRAM OCTLIU packaged 288-pin Tape-SBGA package having body size 23mm 23mm. Figure Diagram
ALE/ LEN4[2]
D[1]/ LEN6[2]
D[2]/ LEN7[0]
D[4]/ LEN7[2]
VDD1V8
TAVS2[1]
TXRING2 TXRING1
TXTIP1[1]
TXTIP2[1]
TXTIP2
TXTIP1
TXRING1 TXRING2
RSTB
SRCCLK
SRCLK
VDD3V3
VDD3V3
VDD3V3
CSB/ LEN5[2]
D[0]/ LEN6[1]
D[3]/ LEN7[1]
D[6]/ LEN8[1]
SBI_EN
QAVS[4]
RES[5]
TAVD3[1]
TAVS3[8]
TAVD2[8]
QAVD[4]
VDD1V8
VDD3V3
RES[1]
RES[6]
SRCDO
SRDO
SRCASC
HW_ONLY
A[8]/ LEN3[2]
A[9]/ LEN4[0]
A[10]/ LEN4[1]
RDB/ LEN5[1]
VDD3V3
VDD3V3
D[7]/ LEN8[2]
CAVD
TAVD2[1]
TAVS3[1]
TAVD3[8]
TAVS2[8]
LOS_L1
SRCODE
SRCEN
SREN
SBI2CLK
A[4]/ LEN2[1]
A[5]/ LEN2[2]
A[6]/ LEN3[0]
WRB/ LEN5[0]
INTB/ LEN6[0]
D[5]/ LEN8[0]
CAVS
TAVS1[1]
TAVD1[1]
TAVD1[8]
TAVS1[8]
XCLK
RSYNC/ ICLK_OUT
VDD3V3
SRDI
VDD3V3
RAVS1[8]
A[0]/ LEN1[0]
A[1]/ LEN1[1]
A[2]/ LEN1[2]
A[7]/ LEN3[1]
TRSTB
RAVD2[8]
RAVD2[7]
RAVS1[1]
RAVD2[1]
QAVD[1]
A[3]/ LEN2[0]
QAVS[3]
RES[4]
RAVS2[7]
TXRING2
RAVD1[1]
RXTIP[1]
RAVS2[1]
VDD3V3
RAVS2[8]
RXTIP[8]
RAVS1[7]
TXRING1
TXRING2
RAVD2[2]
RAVS2[2]
RXRING[1]
RXRING
RAVD1[8]
RAVD1[7]
TXTIP1
TXRING1
RXTIP[2]
RAVS1[2]
RXRING
RXRING
RXTIP[7]
TAVS2[7]
TXTIP2
TXTIP1[2]
RAVD1[2]
TAVS2[2]
TAVS1[2]
TAVS1[7]
TAVD2[7]
TAVD3[7]
TXTIP2
TXTIP2
TAVD2[2]
TAVD3[2]
TAVD1[2]
Bottom View
TAVD1[7]
TAVS3[7]
TAVS3[6]
TXTIP1[6]
TXTIP2
TAVS3[2]
TAVS3[3]
TAVD1[3]
TAVD1[6]
TAVD3[6]
TAVD2[6]
TXRING1
TXTIP1
TAVD3[3]
TAVD2[3]
TAVS1[3]
TAVS1[6]
TAVS2[6]
RAVD1[6]
TXRING2
TXRING1
TAVS2[3]
RAVD1[3]
RXRING
RXRING
RAVS1[6]
RAVD2[6]
RXTIP[6]
TXRING2
RXTIP[3]
RAVD2[3]
RXTIP[4]
RXTIP[5]
RXRING
RAVD1[5]
RAVS2[6]
RAVS1[3]
RAVS2[3]
RAVD1[4]
RAVS2[4]
QAVD[3]
RAVS2[5]
RAVD2[5]
RAVS1[5]
RXRING
RAVS1[4]
RAVD2[4]
TCLK[1]/ IDATA[1]
TCLK[7]/ IDATA[7]
TDN[8]/ IFP_IN
TDP[8]/ ADATA[7]
RES[1]
QAVS[1]
TDP[2]/ ADATA[1] RDN[3]/ VDD3V3 TDN[4]/ VDD3V3 VDD3V3 RLCV[3]/ C1FPOUT TDP[4]/ ADATA[3] RDP[2]/ DDATA[1] RCLK[3]/ EDATA[3] RDN[4]/ VDD3V3 RLCV[4]/ RCLK[4]/ EDATA[4] TAVS2[4] TAVD3[4] TAVS3[5] TAVD2[5] RES[3] TAVS1[4] TAVD1[4] TAVD1[5] TAVS1[5] VDD1V8
TDN[6]/
TCLK[6]/ IDATA[6]
TDN[7]/ ICLK_IN
TCLK[8]/ IDATA[8]
TDP[1]/ ADATA[0]
TDN[1]/ REFCLK
TCLK[2]/ IDATA[2]
RDP[5]/ DDATA[4] RDN[5]/ RLCV[5]/
RCLK[6]/ EDATA[6]
RCLK[7]/ EDATA[7]
RDP[8]/ DDATA[7]
VDD3V3
TCLK[5]/ IDATA[5]
TDP[7]/ ADATA[6]
TDN[2]/ AC1FP
TDP[3]/ ADATA[2]
VDD3V3
VDD3V3
RDP[7]/ DDATA[6]
RDN[8]/ RLCV[8]/ DACTIVE RDN[7]/ RLCV[7]/ ECLK VDD3V3
TDP[5]/ ADATA[4]
TDP[6]/ ADATA[5]
TCLK[3]/ IDATA[3]
TDN[3]/ DC1FP
TCLK[4]/ IDATA[4]
RCLK[1]/ EDATA[1]
RCLK[2]/ EDATA[2] RDN[1]/ RLCV[1]/ IFP_OUT
VDD1V8
QAVD[2]
TAVD2[4]
TAVS3[4]
TAVD3[5]
TAVS2[5]
QAVS[2]
RDP[6]/ DDATA[5] RDN[6]/ RLCV[6]/
TDN[5]/
RDP[1]/ DDATA[0]
RDN[2]/ RLCV[2]/
RDP[3]/ DDATA[2]
RDP[4]/ DDATA[3]
TXRING2 TXRING1
TXTIP1[4]
TXTIP2
TXTIP2
TXTIP1[5]
TXRING1 TXRING2
RCLK[5]/ EDATA[5]
VDD3V3
RCLK[8]/ EDATA[8]
VDD3V3
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
DESCRIPTION convention, where eight pins indexed [8:1] present, index indicates which octant applies. With TCLK[8:1], example, TCLK[1] applies octant TCLK[2] applies octant etc.
Name
Type
Function
System Side Serial Clock Data Interface TCLK[1]/IDATA[1] TCLK[2]/IDATA[2] TCLK[3]/IDATA[3] TCLK[4]/IDATA[4] TCLK[5]/IDATA[5] TCLK[6]/IDATA[6] TCLK[7]/IDATA[7] TCLK[8]/IDATA[8] TDP[1]/ADATA[0] TDP[2]/ADATA[1] TDP[3]/ADATA[2] TDP[4]/ADATA[3] TDP[5]/ADATA[4] TDP[6]/ADATA[5] TDP[7]/ADATA[6] TDP[8]/ADATA[7] Input AA22 AA20 Transmit Clock inputs (TCLK[8:1]) should 1.544 2.048 data streams used sample corresponding TDP[8:1] TDN[8:1] signals. TCLK[8:1] share same pins IDATA[8:1] inputs. TCLK[8:1] selected when SBI2CLK tied low.
Input
Transmit Positive Data (TDP[8:1]). When single-rail mode, these inputs data signals transmitted. These inputs configured active high active low. When dual-rail mode, these inputs positive data signals transmitted. TDP[8:1] sampled either rising falling edges corresponding TCLK[8:1]. TDP[8:1] share same pins ADATA[7:0] inputs. TDP[8:1] selected when SBI_EN SBI2CLK both tied low.
TDN[1]/REFCLK TDN[2]/AC1FP TDN[3]/DC1FP TDN[4]/ADP TDN[5]/APL TDN[6]/AV5 TDN[7]/ICLK_IN TDN[8]/IFP_IN
Input
AA21
Transmit Negative Data (TDN[8:1]). When dual-rail mode, these inputs negative data signals transmitted. These inputs sampled either rising falling edges corresponding TCLK[8:1]. These input pins ignored device configured single-rail (unipolar) transmit mode. TDN[8:1] share same pins REFCLK, AC1FP, DC1FP, ADP, APL, AV5, ICLK_IN IFP_IN inputs. TDN[8:1] selected when SBI_EN SBI2CLK both tied low.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name RCLK[1]/EDATA[1] RCLK[2]/EDATA[2] RCLK[3]/EDATA[3] RCLK[4]/EDATA[4] RCLK[5]/EDATA[5] RCLK[6]/EDATA[6] RCLK[7]/EDATA[7] RCLK[8]/EDATA[8] RDP[1]/DDATA[0] RDP[2]/DDATA[1] RDP[3]/DDATA[2] RDP[4]/DDATA[3] RDP[5]/DDATA[4] RDP[6]/DDATA[5] RDP[7]/DDATA[6] RDP[8]/DDATA[7]
Type Output
AA19 AA18 AA15 AB19 AB16 AB15
Function Recovered Clock Output (RCLK[8:1]). RCLK[8:1] clock recovered from RXTIP[8:1] RXRING[8:1] input signals. RCLK[8:1] share same pins EDATA[8:1] outputs. RCLK[8:1] selected when SBI2CLK tied low.
Output
Receive Digital Positive Data (RDP[8:1]). When single rail mode, RDP[8:1] output sampled DS-1 data which been decoded AMI, B8ZS, HDB3 line code rules. When dual rail mode, RDP[8:1] output sampled bipolar positive pulses. RDP[8:1] updated either falling rising RCLK[8:1] edge. RDP[8:1] share same pins DDATA[7:0] outputs. RDP[8:1] selected when SBI_EN SBI2CLK both tied low.
RDN/RLCV[1]/IFP_OUT RDN/RLCV[2]/EFP RDN/RLCV[3]/C1FPOUT RDN/RLCV[4]/DDP RDN/RLCV[5]/DPL RDN/RLCV[6]/DV5 RDN/RLCV[7]/ECLK RDN/RLCV[8]/DACTIVE
Output
AB18 AB17
Receive Digital Negative Data/Line Code Violation Indication (RDN/RLCV[8:1]). When dual rail mode, RDN/RLCV[8:1] output sampled bipolar negative pulses. When single rail mode, RDN/RLCV[8:1] output pulse whenever line code violation excess zeros condition detected. RDN/RLCV[8:1] updated either falling rising RCLK[8:1] edge. RDN/RLCV[8:1] share same pins IFP_OUT, EFP, C1FPOUT, DDP, DPL, DV5, ECLK DACTIVE outputs. RDN/RLCV[8:1] selected when SBI_EN SBI2CLK both tied low.
System Side Interface REFCLK/TDN[1] Input reference clock signal (REFCLK) provides reference timing DROP busses. REFCLK nominally duty cycle clock frequency 19.44 ±50ppm. REFCLK shares same TDN[1] input. REFCLK selected when SBI_EN SBI2CLK tied high.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name AC1FP/TDN[2]
Type Input
Function octet frame pulse signal (AC1FP) provides frame synchronisation devices connected interface. AC1FP must asserted REFCLK cycle every multiples thereof (i.e. every 9720 REFCLK cycles, where positive integer). devices connected must synchronised AC1FP signal from single source. AC1FP sampled rising edge REFCLK. AC1FP shares same TDN[2] input. AC1FP selected when SBI_EN SBI2CLK tied high.
DC1FP/TDN[3]
Input
AA21
DROP octet frame pulse signal (DC1FP) provides frame synchronisation devices connected interface. DC1FP must asserted REFCLK cycle every multiples thereof (i.e. every 9720 REFCLK cycles, where positive integer). devices connected DROP must synchronised DC1FP signal from single source. DC1FP sampled rising edge REFCLK. DC1FP shares same TDN[3] input. DC1FP selected when SBI_EN SBI2CLK tied high.
C1FPOUT/RDN/RLCV[3]
Output
octet frame pulse output signal (C1FPOUT) used provide frame synchronisation devices interconnected interface. C1FPOUT asserted REFCLK cycle every (i.e. every 9720 REFCLK cycles). C1FPOUT used synchronisation, must connected A/DC1FP inputs devices connected DROP bus. C1FPOUT updated rising edge REFCLK. C1FPOUT shares same RDN/RLCV[3] output. C1FPOUT selected when SBI_EN SBI2CLK tied high.
ADATA[0]/TDP[1] ADATA[1]/TDP[2] ADATA[2]/TDP[3] ADATA[3]/TDP[4] ADATA[4]/TDP[5] ADATA[5]/TDP[6] ADATA[6]/TDP[7] ADATA[7]/TDP[8]
Input
data signals (ADATA[7:0]) contain time division multiplexed transmit data from independently timed links. Link data transported tributaries within structure. OCTLIU configured extract data from tributaries within structure. ADATA[7:0] sampled rising edge REFCLK. ADATA[7:0] share same pins TDP[8:1] inputs. ADATA[7:0] selected when SBI_EN SBI2CLK tied high.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name ADP/TDN[4]
Type Input
Function parity signal (ADP) carries even parity signals. parity calculation encompasses ADATA[7:0], signals. Multiple devices drive uniquely assigned tributary column positions. This parity signal intended detect accidental driver clashes column assignment. sampled rising edge REFCLK. shares same TDN[4] input. selected when SBI_EN SBI2CLK tied high.
APL/TDN[5]
Input
payload signal (APL) indicates valid data within structure. This signal asserted during octets making tributary. This signal asserted during octet within tributary accommodate negative timing adjustments between tributary rate fixed structure. This signal deasserted during octet following octet within tributary accommodate positive timing adjustments between tributary rate fixed structure. sampled rising edge REFCLK. shares same TDN[5] input. selected when SBI_EN SBI2CLK tied high.
AV5/TDN[6]
Input
payload indicator signal (AV5) locates position floating payloads each tributary within structure. Timing differences between port timing timing indicated adjustments this payload indicator relative fixed structure. movements indicated this signal must accompanied appropriate adjustments signal. sampled rising edge REFCLK. shares same TDN[6] input. selected when SBI_EN SBI2CLK tied high.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name DDATA[0]/RDP[1] DDATA[1]/RDP[2] DDATA[2]/RDP[3] DDATA[3]/RDP[4] DDATA[4]/RDP[5] DDATA[5]/RDP[6] DDATA[6]/RDP[7] DDATA[7]/RDP[8]
Type Tristate Output
AB19 AB16 AB15
Function DROP data signals (DDATA[7:0]) contain time division multiplexed receive data from independently timed links. Link data transported tributaries within structure. OCTLIU configured insert data into tributaries within structure. Multiple devices drive DROP uniquely assigned tributary column positions. DDATA[7:0] tristated when OCTLIU outputting data particular tributary column. DDATA[7:0] updated rising edge REFCLK. DDATA[7:0] share same pins RDP[8:1] outputs. DDATA[7:0] selected when SBI_EN SBI2CLK tied high.
DDP/RDN/RLCV[4]
Tristate Output
DROP parity signal (DDP) carries even parity DROP signals. parity calculation encompasses DDATA[7:0], signals. Multiple devices drive this signal uniquely assigned tributary column positions. tristated when OCTLIU outputting data particular tributary column. This parity signal intended detect accidental source clashes column assignment. updated rising edge REFCLK. shares same RDN/RLCV[4] output. selected when SBI_EN SBI2CLK tied high.
DPL/RDN/RLCV[5]
Tristate Output
DROP payload signal (DPL) indicates valid data within structure. This signal asserted during octets making tributary. This signal asserted during octet within tributary accommodate negative timing adjustments between tributary rate fixed structure. This signal deasserted during octet following octet within tributary accommodate positive timing adjustments between tributary rate fixed structure. Multiple devices drive this signal uniquely assigned tributary column positions. tristated when OCTLIU outputting data particular tributary column. updated rising edge REFCLK. shares same RDN/RLCV[5] output. selected when SBI_EN SBI2CLK tied high.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name DV5/RDN/RLCV[6]
Type Tristate output
Function DROP payload indicator signal (DV5) locates position floating payloads each tributary within structure. Timing differences between port timing timing indicated adjustments this payload indicator relative fixed structure. Multiple devices drive this signal uniquely assigned tributary column positions. tristated when OCTLIU outputting data particular tributary column. updated rising edge REFCLK. shares same RDN/RLCV[6] output. selected when SBI_EN SBI2CLK tied high.
DACTIVE/RDN/RLCV[8]
Output
DROP active indicator signal (DACTIVE) asserted whenever OCTLIU driving DROP signals, DDATA[7:0], DDP, DV5. DACTIVE updated rising edge REFCLK. DACTIVE shares same RDN/RLCV[8] output. DACTIVE selected when SBI_EN SBI2CLK tied high.
Transmit Line Interface TXTIP1[1] TXTIP1[2] TXTIP1[3] TXTIP1[4] TXTIP1[5] TXTIP1[6] TXTIP1[7] TXTIP1[8] TXTIP2[1] TXTIP2[2] TXTIP2[3] TXTIP2[4] TXTIP2[5] TXTIP2[6] TXTIP2[7] TXTIP2[8] Analogue Output AB12 AB11 AB10 Transmit Analogue Positive Pulse (TXTIP1[8:1] TXTIP2[8:1]). When transmit analogue line interface enabled, TXTIP1[x] TXTIP2[x] analogue outputs drive transmit line pulse signal through external matching transformer. Both TXTIP1[x] TXTIP2[x] normally connected positive lead transformer primary. outputs provided better signal integrity must shorted together board. After reset, TXTIP1[x] TXTIP2[x] high impedance. HIGHZ octant's XLPG Line Driver Configuration register must programmed logic remove high impedance state.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name TXRING1[1] TXRING1[2] TXRING1[3] TXRING1[4] TXRING1[5] TXRING1[6] TXRING1[7] TXRING1[8] TXRING2[1] TXRING2[2] TXRING2[3] TXRING2[4] TXRING2[5] TXRING2[6] TXRING2[7] TXRING2[8] Receive Line Interface RXTIP[1] RXTIP[2] RXTIP[3] RXTIP[4] RXTIP[5] RXTIP[6] RXTIP[7] RXTIP[8] RXRING[1] RXRING[2] RXRING[3] RXRING[4] RXRING[5] RXRING[6] RXRING[7] RXRING[8]
Type
Function Transmit Analogue Negative Pulse (TXRING1[8:1] TXRING2[8:1]). When transmit analogue line interface enabled, TXRING1[x] TXRING2[x] analogue outputs drive transmit line pulse signal through external matching transformer. Both TXRING1[x] TXRING2[x] normally connected negative lead transformer primary. outputs provided better signal integrity must shorted together board. After reset, TXRING1[x] TXRING2[x] high impedance. HIGHZ octant's XLPG Line Driver Configuration register must programmed logic remove high impedance state.
Analogue Output AB13 AB14
Analogue Input Analogue Input
Receive Analogue Positive Pulse (RXTIP[8:1]). When analogue receive line interface enabled, RXTIP[x] samples received line pulse signal from external isolation transformer. RXTIP[x] normally connected directly positive lead receive transformer secondary.
Receive Analogue Negative Pulse (RXRING[8:1]). When analogue receive line interface enabled, RXRING[x] samples received line pulse signal from external isolation transformer. RXRING[x] normally connected directly negative lead receive transformer secondary.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name
Type
Function
Clk/Data Converter Interface SBI_EN SBI2CLK Input interface enable signals (SBI_EN, SBI2CLK) select between serial clock/data system side interfaces allow selection operating mode which LIUs disabled OCTLIU functions converter between interface serial clk/data. signals select device operating mode follows: SBI_EN IDATA[1]/TCLK[1] IDATA[2]/TCLK[2] IDATA[3]/TCLK[3] IDATA[4]/TCLK[4] IDATA[5]/TCLK[5] IDATA[6]/TCLK[6] IDATA[7]/TCLK[7] IDATA[8]/TCLK[8] ICLK_IN/TDN[7] Input AA22 AA20 SBI2CLK Mode LIUs enabled, clk/data selected system side. LIUs enabled, interface selected system side. LIUs disabled, converter mode. Unused
Ingress Data inputs (IDATA[8:1]) carry eight serial 1.544 Mbps 2.048 Mbps data streams mapped interface when device operating clk/data converter. eight serial data streams sampled rising edge ICLK_IN. IDATA[8:1] share same pins TCLK[8:1] inputs. IDATA[8:1] selected when SBI2CLK tied high. Ingress Input Clock (ICLK_IN) should 1.544 2.048 data streams used sample IDATA[8:1] IFP_IN signals. ICLK_IN shares same TDN[7] input. ICLK_IN selected when SBI_EN SBI2CLK tied high.
Input
IFP_IN/TDN[8]
Input
Ingress Frame Pulse input (IFP_IN) should high during framing bits streams during first framing octet data streams. IFP_IN sampled rising edge ICLK_IN. IFP_IN shares same TDN[8] input. IFP_IN selected when SBI_EN SBI2CLK tied high.
ICLK_OUT/RSYNC
Output
Ingress Output Clock (ICLK_OUT) nominal 1.544 (for DS1) 2.048 (for clock used source ICLK_IN clock desired. ICLK_OUT shares same RSYNC output. ICLK_OUT selected when SBI2CLK tied high.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name
Type Output
AB18
Function Ingress Frame Pulse output (IFP_OUT) pulsed high every ICLK_OUT cycles every ICLK_OUT cycles used framing reference source IFP_IN desired. IFP_OUT updated falling edge ICLK_OUT. IFP_OUT shares same RDN/RLCV[1] output. IFP_OUT selected when SBI_EN SBI2CLK tied high.
IFP_OUT/RDN/RLCV[1]
EDATA[1]/RCLK[1] EDATA[2]/RCLK[2] EDATA[3]/RCLK[3] EDATA[4]/RCLK[4] EDATA[5]/RCLK[5] EDATA[6]/RCLK[6] EDATA[7]/RCLK[7] EDATA[8]/RCLK[8] ECLK/RDN/RLCV[7]
Output
AA19 AA18 AA15
Egress Data outputs (EDATA[8:1]) carry eight serial 1.544 Mbps 2.048 Mbps data streams de-mapped from interface when device operating clk/data converter. eight serial data streams updated falling edge ECLK. EDATA[8:1] share same pins RCLK[8:1] outputs. EDATA[8:1] selected when SBI2CLK tied high. Egress Clock output (ECLK) 1.544 (for DS1) 2.048 (for clock, recovered from tributaries. tributary used recover timing selectable. ECLK shares same RDN/RLCV[7] output. ECLK selected when SBI_EN SBI2CLK tied high.
Output
EFP/RDN/RLCV[2]
Output
AB17
Egress Frame Pulse output (EFP) high during framing bits streams during first framing octet data streams. updated falling edge ECLK. shares same RDN/RLCV[2] output. selected when SBI_EN SBI2CLK tied high.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name Timing Options Control XCLK
Type
Function
Input
Crystal Clock Input (XCLK). This signal provides stable, global timing reference OCTLIU internal circuitry internal clock synthesizer. XCLK nominally jitter free clock 1.544 mode 2.048 mode. mode, 2.048 clock used reference. When used this way, however, intrinsic jitter specifications AT&T TR62411 met.
RSYNC/ICLK_OUT
Output
Recovered Clock Synchronization Signal (RSYNC). This output signal recovered, jitter attenuated, receiver line rate clock (1.544 2.048 MHz) eight channels optionally, recovered, jitter attenuated clock synchronously divided mode) mode) create timing reference signal. default source RSYNC from octant When OCTLIU loss signal state, RSYNC derived from XCLK input optionally, held high. RSYNC shares same ICLK_OUT output. RSYNC selected when SBI2CLK tied low.
Alarm Interface Output Loss Signal Alarm (LOS). This signal outputs status octants serial format which repeats every XCLK cycles. presence status this output indicated LOS_L1 output pulsing high. following XCLK cycle, status output, then This signal intended Hardware Only mode. When microprocessor interface enabled, status alarm also determined reading LOSV CDRC Interrupt Status register. updated falling edge XCLK. LOS_L1 Output Loss Signal indicator (LOS_L1). This signal pulsed high XCLK cycle every XCLK cycles indicates that status being output LOS. LOS_L1 updated falling edge XCLK.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name Misc. Control Signals RSTB
Type
Function
Input
Active Reset (RSTB). This signal provides asynchronous OCTLIU reset. RSTB Schmidt triggered input with internal pull resistor. This must tied normal operation. These pins must connected analogue ground normal operation.
RES[1] RES[2] RES[3] RES[4] RES[5] RES[6]
Input
Analogue Input
This must tied ground normal operation.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name
Type
Function
Microprocessor Interface A[0]/LEN1[0] A[1]/LEN1[1] A[2]/LEN1[2] A[3]/LEN2[0] A[4]/LEN2[1] A[5]/LEN2[2] A[6]/LEN3[0] A[7]/LEN3[1] A[8]/LEN3[2] A[9]/LEN4[0] A[10]/LEN4[1] ALE/LEN4[2] Input Address (A[10:0]). This selects specific registers during OCTLIU register accesses. Signal A[10] selects between normal mode test mode register access. A[10] internal pull down resistor. A[10:0] share same pins some LENx[2:0] inputs. A[10:0] selected when HW_ONLY tied low.
Input
Address Latch Enable (ALE). This signal active high latches address contents, A[10:0], when low. When high, internal address latches transparent. allows OCTLIU interface multiplexed address/data bus. input internal pull resistor. shares same LEN4[2] input. selected when HW_ONLY tied low.
WRB/LEN5[0]
Input
Active Write Strobe (WRB). This signal during OCTLIU register write access. D[7:0] contents clocked into addressed register rising edge while low. shares same LEN5[0] input. selected when HW_ONLY tied low.
RDB/LEN5[1]
Input
Active Read Enable (RDB). This signal during OCTLIU register read accesses. OCTLIU drives D[7:0] with contents addressed register while low. shares same LEN5[1] input. selected when HW_ONLY tied low.
CSB/LEN5[2]
Input
Active Chip Select (CSB). must enable OCTLIU register accesses. must high least once after power clear internal test modes. used, should tied inverted version RSTB, which case, determine register accesses. shares same LEN5[2] input. selected when HW_ONLY tied low.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name INTB/LEN6[0]
Type Opendrain Output
Function Active Open-Drain Interrupt (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source which time, INTB will tristate. INTB shares same LEN6[0] input. INTB selected when HW_ONLY tied low.
D[0]/LEN6[1] D[1]/LEN6[2] D[2]/LEN7[0] D[3]/LEN7[1] D[4]/LEN7[2] D[5]/LEN8[0] D[6]/LEN8[1] D[7]/LEN8[2]
Bidirectional Data (D[7:0]). This provides OCTLIU register read write accesses. D[7:0] share same pins some LENx[2:0] inputs. D[7:0] selected when HW_ONLY tied low.
Hardware-Only Control Interface HW_ONLY Input Hardware Only mode enable signal (HW_ONLY) selects between microprocessor-controlled hardware-only modes operation. When HW_ONLY tied low, microprocessor interface enabled. When HW_ONLY tied high, hardwareonly control interface enabled microprocessor interface unused. Serial PROM Cascade Control (SRCASC). When SRCASC tied low, OCTLIU acts Serial PROM master controller SREN, SRCLK, SRDI SRDO pins should connected serial PROM. When SRCASC tied high, OCTLIU acts Serial PROM cascade slave SREN, SRCLK SRDO pins should connected SRCEN, SRCCLK SRCDO pins another OCTLIU device upstream cascade. Serial PROM Enable (SREN). When operating Serial PROM master (SRCASC tied low), SREN functions output generates active chip select signal serial PROM. When operating Serial PROM slave (SRCASC tied high), SREN functions input indicates validity cascade data SRDO input. When configured output, SREN updated falling edge SRCLK. When configured input, SREN sampled rising edge SRCLK.
SRCASC
Input
SREN
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name SRCLK
Type
Function Serial PROM Clock (SRCLK). When operating Serial PROM master (SRCASC tied low), SRCLK functions output generates clock serial PROM. When operating Serial PROM slave (SRCASC tied high), SRCLK functions input connected SRCCLK output OCTLIU device upstream serial PROM cascade. Serial PROM Data (SRDI). When operating Serial PROM master (SRCASC tied low), SRDI output used send read commands serial PROM. When operating Serial PROM slave (SRCASC tied high), SRDI unused. SRDI updated falling edge SRCLK.
SRDI
Output
SRDO
Input
Serial PROM Data (SRDO). When operating Serial PROM master (SRCASC tied low), SRDO input receives data from serial PROM. When operating Serial PROM slave (SRCASC tied high), SRDO input receives data from SRCDO output OCTLIU device upstream serial PROM cascade. SRDO sampled rising edge SRCLK.
SRCEN
Output
Serial PROM Cascade Enable (SRCEN). SRCEN output asserted when valid data being output SRCDO. SRCEN updated falling edge SRCCLK.
SRCCLK
Output
Serial PROM Cascade Clock (SRCCLK). When operating Serial PROM master (SRCASC tied low), SRCCLK output copy SRCLK output. When operating Serial PROM slave (SRCASC tied high), SRCCLK output copy SRCLK input. Serial PROM Cascade Data (SRCDO). SRCDO output buffered, retimed copy SRDO input. SRCDO updated falling edge SRCCLK.
SRCDO
Output
SRCODE
Input
Serial PROM Code (SRCODE). SRCODE input provides means controlling execution configuration instructions stored serial PROM. Instructions coded execute only SRCODE logic only SRCODE logic unconditionally. SRCODE input thus allows selection different configuration sequences within single PROM load. This could used, example, store configurations operation within serial PROM.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name LEN1[0]/A[0] LEN1[1]/A[1] LEN1[2]/A[2] LEN2[0]/A[3] LEN2[1]/A[4] LEN2[2]/A[5] LEN3[0]/A[6] LEN3[1]/A[7] LEN3[2]/A[8] LEN4[0]/A[9] LEN4[1]/A[10] LEN4[2]/ALE LEN5[0]/WRB LEN5[1]/RDB LEN5[2]/CSB LEN6[0]/INTB LEN6[1]/D[0] LEN6[2]/D[1] LEN7[0]/D[2] LEN7[1]/D[3] LEN7[2]/D[4] LEN8[0]/D[5] LEN8[1]/D[6] LEN8[2]/D[7]
Type Input
Function Line Length Build-out Select (LENn[2:0]). These signals preset select eight different pulse templates used line transmitters, depending line length, etc. LENn[2:0] selects pulse template line transmitter octant LENn[2:0] share same pins microprocessor interface signals. LENn[2:0] selected when HW_ONLY tied high. LENn[2:0] inputs latched following reset OCTLIU changes their value will have effect operation OCTLIU until subsequent reset.
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name JTAG Interface
Type
Function
Tristate Output
Test Data Output (TDO). This signal carries test data OCTLIU IEEE 1149.1 test access port. updated falling edge TCK. tri-state output that tristated except when scanning data progress. Test Data Input (TDI). This signal carries test data into OCTLIU IEEE 1149.1 test access port. sampled rising edge TCK. internal pull resistor. Test Clock (TCK). This signal provides timing test operations that carried using IEEE 1149.1 test access port. Test Mode Select (TMS). This signal controls test operations that carried using IEEE 1149.1 test access port. sampled rising edge TCK. internal pull resistor. Active Test Reset (TRSTB). This signal provides asynchronous OCTLIU test access port reset IEEE 1149.1 test access port. TRSTB Schmidt triggered input with internal pull resistor. TRSTB must asserted during power sequence. Note that used, TRSTB should connected RSTB input.
Input
Input Input
TRSTB
Input
Analogue Power Ground Pins TAVD1[1] TAVD1[2] TAVD1[3] TAVD1[4] TAVD1[5] TAVD1[6] TAVD1[7] TAVD1[8] Analogue Power Transmit Analogue Power (TAVD1[8:1]). TAVD1[8:1] provide power transmit analogue circuitry. TAVD1[8:1] should connected analogue +3.3
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name TAVD2[1] TAVD2[2] TAVD2[3] TAVD2[4] TAVD2[5] TAVD2[6] TAVD2[7] TAVD2[8] TAVD3[1] TAVD3[2] TAVD3[3] TAVD3[4] TAVD3[5] TAVD3[6] TAVD3[7] TAVD3[8] CAVD
Type
Function Transmit Analogue Power (TAVD2[8:1], TAVD3[8:1]). TAVD2[8:1] TAVD3[8:1] supply power transmit current DACs. They should connected analogue +3.3
Analogue Power AA12 AA10 Analogue Power Analogue Ground
Clock Synthesis Unit Analogue Power (CAVD). CAVD supplies power transmit clock synthesis unit. CAVD should connected analogue +3.3 Transmit Analogue Ground (TAVS1[8:1]). TAVS1[8:1] provide ground transmit analogue circuitry. TAVS1[8:1] should connected analogue GND.
TAVS1[1] TAVS1[2] TAVS1[3] TAVS1[4] TAVS1[5] TAVS1[6] TAVS1[7] TAVS1[8]
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name TAVS2[1] TAVS2[2] TAVS2[3] TAVS2[4] TAVS2[5] TAVS2[6] TAVS2[7] TAVS2[8] TAVS3[1] TAVS3[2] TAVS3[3] TAVS3[4] TAVS3[5] TAVS3[6] TAVS3[7] TAVS3[8] CAVS
Type
Function Transmit Analogue Ground (TAVS2[8:1], TAVS3[8:1]). TAVS2[8:1] TAVS3[8:1] supply ground transmit current DACs. They should connected analogue GND.
Analogue Ground AA11 Analogue Ground Analogue Power Analogue Power
Clock Synthesis Unit Analogue Ground (CAVS). CAVS supplies ground transmit clock synthesis unit. CAVS should connected analogue GND. Receive Analogue Power (RAVD1[8:1]). RAVD1[8:1] supplies power receive input equalizer. RAVD1[8:1] should connected analogue +3.3
RAVD1[1] RAVD1[2] RAVD1[3] RAVD1[4] RAVD1[5] RAVD1[6] RAVD1[7] RAVD1[8] RAVD2[1] RAVD2[2] RAVD2[3] RAVD2[4] RAVD2[5] RAVD2[6] RAVD2[7] RAVD2[8]
Receive Analogue Power (RAVD2[8:1]). RAVD2[8:1] supplies power receive peak detect slicer. RAVD2[8:1] should connected analogue +3.3
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name RAVS1[1] RAVS1[2] RAVS1[3] RAVS1[4] RAVS1[5] RAVS1[6] RAVS1[7] RAVS1[8] RAVS2[1] RAVS2[2] RAVS2[3] RAVS2[4] RAVS2[5] RAVS2[6] RAVS2[7] RAVS2[8] QAVD[1] QAVD[2] QAVD[3] QAVD[4] QAVS[1] QAVS[2] QAVS[3] QAVS[4]
Type
Function Receive Analogue Ground (RAVS1[8:1]). RAVS1[8:1] supplies ground receive input equalizer. RAVS1[8:1] should connected analogue GND.
Analogue Ground Analogue Ground Analogue Power AA13 Analogue Ground
Receive Analogue Ground (RAVS2[8:1]). RAVS2[8:1] supplies ground receive peak detect slicer. RAVS2[8:1] should connected analogue GND.
Quiet Analogue Power (QAVD[4:1]). QAVD[4:1] supplies power core analogue circuitry. QAVD[4:1] should connected analogue +3.3 Quiet Analogue Ground (QAVS[4:1]). QAVS[4:1] supplies ground core analogue circuitry. QAVS[4:1] should connected analogue GND.
Digital Power Ground Pins VDD1V8[1] VDD1V8[2] VDD1V8[3] VDD1V8[4] Power AA14 Core Power (VDD1V8[4:1]). VDD1V8[4:1] pins should connected well decoupled +1.8V power supply.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name VDD3V3[1] VDD3V3[2] VDD3V3[3] VDD3V3[4] VDD3V3[5] VDD3V3[6] VDD3V3[7] VDD3V3[8] VDD3V3[9] VDD3V3[10] VDD3V3[11] VDD3V3[12] VDD3V3[13] VDD3V3[14] VDD3V3[15] VDD3V3[16] VDD3V3[17] VDD3V3[18] VDD3V3[19]
Type Power
Function Power (VDD3V3[19:1]). VDD3V3[19:1] pins should connected well decoupled +3.3V power supply.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25]
Type Ground
AA16 AA17 AB20 AB21 AB22
Function Ground (VSS [25:1]). VSS[25:1] pins should connected Ground.
Open
These pins must left unconnected.
NOTES DESCRIPTIONS: OCTLIU inputs bi-directionals present minimum capacitive loading. OCTLIU inputs bi-directionals, when configured inputs, tolerate logic levels. OCTLIU outputs bi-directionals have least drive capability, except LOS, LOS_L1, serial PROM interface outputs, which have least drive capability. transmit analogue outputs (TXTIP TXRING) have built-in short circuit current limiting. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. Inputs A[10], RES[1], RES[6] have internal pull-down resistors. unused inputs should connected GROUND.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, VDD3V3) will collectively referred VDDall33 this document. Power VDDall33 should applied before power VDD1V8 pins applied. Similarly, power VDD1V8 pins should removed before power VDDall33 removed. VDDall33 voltage level should allowed drop below VDD1V8 voltage level except when VDD1V8 powered.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
FUNCTIONAL DESCRIPTION Octants OCTLIU's eight E1/T1 line interface units operate independently configured operate uniquely. octants share common XCLK clock input internal clock synthesizer; hence only single Configuration register present. Additionally, octants share common E1/T1B mode register select between operation.
Receive Interface analogue receive interface configurable operate both short-haul longhaul applications. Short-haul defined transmission over less than cable. Shorthaul defined transmission cable that attenuates signal less than long-haul signals, unequalized long- short-haul bipolar alternate mark inversion (AMI) signals received differential voltage between RXTIP RXRING inputs. OCTLIU typically accepts unequalized signals that attenuated both signals non-linearly distorted typical cables. short-haul, slicing threshold fraction input signal's peak amplitude, adapts changes this amplitude. slicing threshold programmable, typically DSX-1 applications, respectively. Abnormally input signals detected when input level below programmable threshold, which typically Figure External Analogue Interface Circuits
TTip TXTIP TXRING outB center outA TRing Phantom Feed Circuit Vsupply required RTip RXTIP RXRING outB center outA RRing Eight LIUs chassis chassis
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure gives recommended external protection circuitry designs required meet major surge immunity electrical safety standards including Part UL1950, Bellcore TR-NWT-001089. This circuit been tested December, 1999. Please refer upcoming application note more details. systems requiring phantom feed inter-building line protection, Bi-directional Transient Surge Suppressors (Z1-Z4), their associated ground connection center transformer removed from circuit. Table descriptions components Figure Note that crowbar devices required transformer's isolation rating exceeded. Table External Component Descriptions Description 36.0 ±1%, 0.25W Resistor 27.0 ±1%, 0.25W Resistor Surge Protector Diode Array 1:1.58 Transformers cable) Transformers (otherwise) Bi-directional Transient Surge Suppressors Bi-directional Transient Surge Suppressors Dual Choke, 27µH Telecom/Time Fuses P1800SC P0720SC PE-68624 F1250T SRDA3.3-4 Semtech Pulse Teccor Teccor Pulse Teccor Part Source
Component
When operating mode with cable, 1:1.58 turns ratio transformer specified above table. fact also possible turns ratio transformer, which case value must changed 22.0 value must changed 18.0 ±1%. Clock Data Recovery (CDRC) Clock Data Recovery function provided Clock Data Recovery (CDRC) block. CDRC provides clock data recovery, B8ZS HDB3 decoding, line code violation detection, loss signal detection. recovers clock from incoming data pulses using digital phase-locked-loop reconstructs data. Loss signal indicated after programmable threshold consecutive periods absence pulses both positive negative line pulse inputs cleared after occurrence single line pulse. alternate loss signal indication provided which cleared upon meeting 1-in-8 pulse density criteria 1-in-4 pulse density criteria enabled, microprocessor interrupt generated when loss signal detected when signal returns. line code violation defined bipolar violation (BPV) AMI-coded signals,
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
defined that part zero substitution code B8ZS-coded signals, defined bipolar violation same polarity last bipolar violation HDB3-coded signals. mode, input jitter tolerance OCTLIU complies with Bellcore Document TA-TSY-000170 with AT&T specification TR62411, shown Figure tolerance measured with QRSS sequence (220-1 with zero restriction). CDRC block provides algorithms clock recovery that result differing jitter tolerance characteristics. first algorithm (when ALGSEL register logic provides good frequency jitter tolerance, high frequency tolerance close TR62411 limit. second algorithm (when ALGSEL logic provides much better high frequency jitter tolerance expense frequency tolerance; frequency tolerance second algorithm approximately that first algorithm. Figure Jitter Tolerance
Acceptable Range Sine Jitter plitude (UI) Scale
Bellcore Spec. AT&T Spec.
0.30 0.31
Sine Jitter Frequency (kHz) Scale
applications, input jitter tolerance complies with ITU-T Recommendation G.823 "The Control Jitter Wander Within Digital Networks Which Based 2048 kbit/s Hierarchy." Figure illustrates this specification performance phase-locked loop when ALGSEL register logic
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure Compliance with ITU-T Specification G.823 Input Jitter
SINEWAVE JITTER AMPLITUDE (UI) SCALE
DPLL TOLERANCE WITH ENCODED PRBS
SPEC REGION
DPLL TOLERANCE WITH HDB3 ENCODED 15-1 PRBS
REC. G823 JITTER TOLERANCE SPECIFICATION
SINEWAVE JITTER FREQUENCY, SCALE
Receive Jitter Attenuator (RJAT) Receive Jitter Attenuator (RJAT) digital attenuates jitter present RXTIP/RXRING inputs. attenuation only performed when RJATBYP register logic jitter characteristics Receive Jitter Attenuator (RJAT) same Transmit Jitter Attenuator (TJAT).
Inband Loopback Code Detector (IBCD) Inband Loopback Code Detection function provided IBCD block. This block detects presence either programmable INBAND LOOPBACK ACTIVATE DEACTIVATE code sequences receive data stream. Each INBAND LOOPBACK code sequence defined repetition programmed code stream least seconds. code sequence detection timing compatible with specifications defined T1.403-1993, TA-TSY-000312, TR-TSY-000303. LOOPBACK ACTIVATE DEACTIVATE code indication provided through internal register bits. interrupt generated indicate when either code status changed.
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pulse Density Violation Detector (PDVD) Pulse Density Violation Detection function provided PDVD block. block detects pulse density violations requirement that there ones each every time window 8(N+1) data bits (where equal through 23). PDVD also detects periods consecutive zeros incoming data. Pulse density violation detection provided through internal register bit. interrupt generated signal consecutive zero event, and/or change state pulse density violation indication.
Performance Monitor Counters (PMON) Performance Monitor block accumulates line code violation events with saturating counter over consecutive intervals defined period between writes trigger registers (typically second). When trigger applied, PMON transfers counter value into holding registers resets counter begin accumulating events interval. counter reset such manner that error events occurring during reset missed. holding registers read between successive triggers, overrun register asserted. Triggering counter transfer within octant performed writing counter register location within octant writing "Line Interface Interrupt Source PMON Update" register.
Pseudo Random Binary Sequence Generation Detection (PRBS) Pseudo Random Binary Sequence Generator/Detector (PRBS) block software selectable PRBS generator checker PRBS polynomials links. PRBS patterns generated detected either transmit receive directions. PRBS block perform auto synchronization expected PRBS pattern accumulates total number errors 24-bit counters. error count accumulates over interval defined successive writes Line Interface Interrupt Source PMON Update register. When accumulation forced, holding register updated, counter reset begin accumulating next interval. counter reset such that events missed. data then available Error Count registers until next accumulation.
Inband Loopback Code Generator (XIBC) Inband Loopback Code Generator (XIBC) block generates stream inband loopback codes (IBC) inserted into data stream. stream consists continuous repetitions specific code. contents code length programmable from bits.
9.10 Pulse Density Enforcer (XPDE) Pulse Density Enforcer function provided XPDE block. Pulse density enforcement enabled register within XPDE.
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
This block monitors digital output transmitter detects when stream about violate ANSI T1.403 12.5% pulse density rule over moving 192-bit window. density violation detected, block enabled insert logic into digital stream ensure resultant output longer violates pulse density requirement. When XPDE disabled from inserting logic digital stream from transmitter passed through unaltered. 9.11 Transmit Jitter Attenuator (TJAT) Transmit Jitter Attenuation function provided digital phase lock loop 80-bit deep FIFO. TJAT receives jittery, dual-rail data format separate inputs, which allows bipolar violations pass through block uncorrected. incoming data streams stored FIFO timed transmit clock. respective input data emerges from FIFO timed jitter attenuated clock. jitter attenuator generates jitter-free 1.544 2.048 Transmit clock output adjusting Transmit clock's phase 1/96 increments minimize phase difference between generated Transmit clock input data clock TJAT. Jitter fluctuations phase input data clock attenuated phase-locked loop within TJAT that frequency Transmit clock equal average frequency input data clock. applications, best jitter attenuation transfer function recommended 62411, phase fluctuations with jitter frequency above attenuated octave jitter frequency. Wandering phase fluctuations with frequencies below tracked generated Transmit clock. applications, corner frequency provide smooth flow data TJAT, Transmit clock used read data FIFO. FIFO read pointer (timed Transmit clock) comes within write pointer (timed input data clock), TJAT will track jitter input clock. This permits phase jitter pass through unattenuated, inhibiting loss data. Jitter Characteristics TJAT Block provides excellent jitter tolerance jitter attenuation while generating minimal residual jitter. accommodate Uipp input jitter jitter frequencies above (7.6 E1). jitter frequencies below (7.6 E1), more correctly called wander, tolerance increases decade. most applications TJAT Block will limit jitter tolerance lower jitter frequencies only. high frequency jitter, above example, other factors such clock data recovery circuitry limit jitter tolerance must considered. frequency wander, below example, other factors such slip buffer hysteresis limit wander tolerance must considered. TJAT block meets stringent frequency jitter tolerance requirements AT&T 62411 thus allows compliance with this standard other less stringent jitter tolerance standards cited references. TJAT exhibits negligible jitter gain jitter frequencies below (7.6 E1), attenuates jitter frequencies above (7.6 decade. most applications, TJAT block will determine jitter attenuation higher jitter frequencies only. Wander, below example, will essentially passed unattenuated through TJAT. Jitter, above example, will attenuated specified, however, outgoing jitter
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
dominated generated residual jitter cases where incoming jitter insignificant. This generated residual jitter directly related 1/96 phase adjustment quantum. TJAT meets jitter attenuation requirements AT&T 62411. block allows implied jitter attenuation requirements given ANSI Standard T1.408, implied jitter attenuation requirements type customer interface given ANSI T1.403 met. Jitter Tolerance Jitter tolerance maximum input phase jitter given jitter frequency that device accept without exceeding linear operating range, corrupting data. TJAT, input jitter tolerance Unit Intervals peak-to-peak (Uipp) with worst case frequency offset Uipp with frequency offset. frequency offset difference between frequency XCLK that input data clock. Figure TJAT Jitter Tolerance
JITTER AMPLITUDE,
MIN.TOLER ANCE
unacceptable
acceptable
0.01
100k
JITTER FREQUENCY,
accuracy XCLK frequency that TJAT reference input clock used generate jitter-free Transmit clock output have effect minimum jitter tolerance. Given that TJAT reference clock accuracy ±200 that XCLK input accuracy ±100 ppm, minimum jitter tolerance various differences between frequency reference clock XCLK shown Figure
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure TJAT Minimum Jitter Tolerance XCLK Accuracy
MIN. JITTER TOLERANCE,
MAX. FREQUENCY OFFSET XCLK ACCURACY
Jitter Transfer applications, output jitter jitter frequencies from (7.6 more than greater than input jitter, excluding residual jitter. Jitter frequencies above (7.6 attenuated level octave, shown Figure figure valid case where TJAT Jitter Attenuator Divider Control register TJAT Divider Control register.
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure TJAT Jitter Transfer
JITTER GAIN
62411 response 62411 43802
JITTER FREQUENCY
non-attenuating mode, when FIFO within overrunning underrunning, tracking range 1.48 1.608 MHz. guaranteed linear operating range jittered input clock 1.544 with worst case jitter Uipp), maximum system clock frequency offset ppm). nominal range 1.544 with jitter system clock frequency offset. non-attenuating mode, when FIFO within overrunning underrunning, tracking range 2.13 1.97 MHz. guaranteed linear operating range jittered input clock 2.048 with worst case jitter Uipp), maximum system clock frequency offset ppm). nominal range 2.048 1277 with jitter system clock frequency offset. Jitter Generation absence input jitter, output jitter shall less than 0.025 Uipp. This complies with AT&T 62411 requirement less than 0.025 Uipp jitter generation.
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
9.12 Line Transmitter line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable DSX-1 (short haul T1), short haul long haul long haul environments. voltage pulses produced applying current known termination (termination resistor plus line impedance). current (instead voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) transmit tri-stating. output pulse shape synthesized digitally with current digital-to-analogue (DAC) converters, which produce samples symbol. current DAC's produce differential bipolar outputs that directly drive TXTIP1[x], TXTIP2[x], TXRING1[x] TXRING2[x] pins. current output applied terminating resistor line-coupling transformer differential manner, which when viewed from line side transformer produce output pulses required levels ensures small positive negative pulse imbalance. pulse shape user programmable. short haul, cable length between OCTLIU cross-connect (where pulse template specifications given) greatly affects resulting pulse shapes. Hence, data applied converter must account different cable lengths. CEPT applications pulse template specified transmitter, thus only setting required. long haul with previous bits effect what transmitter must drive compensate inter-symbol interference; LBO's 22.5 previous bits effect what transmitter must send out. Refer Operation section details creating synthesized pulse shape. 9.13 Timing Options (TOPS) Timing Options block provides means selecting source internal input clock TJAT block, reference clock TJAT digital PLL. 9.14 Scaleable Bandwidth Interconnect (SBI) Interface Scaleable Bandwidth Interconnect synchronous, time-division multiplexed designed transfer, pin-efficient manner, data belonging number independently timed links varying bandwidth. timed reference 19.44MHz clock fraction thereof) frame pulse. sources sinks data timed reference clock frame pulse. Timing communicated across Scaleable Bandwidth Interconnect floating data structures. Payload indicator signals control position floating data structure therefore timing. When sources running faster than floating payload structure advanced octet passing extra octet octet locations octet mappings which used OCTLIU). When source slower than floating payload retarded leaving octet after octet unused. Both these rate adjustments indicated control signals.
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OCTAL E1/T1/J1 LINE INTERFACE DEVICE
multiplexing structure modeled SONET/SDH standards. SONET/SDH virtual tributary structure used carry T1/J1 links. Unchannelized payloads (not used OCTLIU) follow byte synchronous structure modeled SONET/SDH format. structure uses locked SONET/SDH structure fixing position TUG-3/TU-3 relative STS-3/STM-1 transport frame. also fixed frequency alignment determined reference clock (REFCLK) frame indicator signal (C1FP). Frequency deviations compensated adjusting location T1/J1/E1/DS3 channels using floating tributaries determined indicator payload signals (DV5, AV5, APL). Note that OCTLIU always operates clock slave clock master DROP bus, i.e. does support AJUST_REQ DJUST_REQ timing adjustment request signals defined specification. multiplexed links separated into three Synchronous Payload Envelopes (SPE). Each envelope configured independently carry T1/J1s, DS3. OCTLIU configured eight T1/J1 tributaries eight tributaries from three SPE's. eight tributaries need selected from same SPE. single OCTLIU device cannot, however, T1/J1 tributaries simultaneously. 9.14.1 Interfacing OCTLIUs High Density Framer Figure Framer Line Side Interface
19.44MHz LREFCLK LAC1 LAC1J1V1 LADATA[7:0] LADP LATPL LAV5 LAPL LDC1J1V1 LDDATA[7:0] LDDP LDTPL LDV5 LDPL LDAIS Framer REFCLK C1FPOUT AC1FP ADATA[7:0] DC1FP DDATA[7:0]
OCTLIUs
Figure shows interfaces multiple OCTLIU's connected line side interface high density framer. With exception C1FPOUT, signals OCTLIU side simply bussed parallel multiple devices. C1FPOUT port single OCTLIU used provide frame reference devices. Alternatively, frame pulse generated external circuitry desired. framer's interface must configured such that pointer processors bypassed, VT's byte synchronously mapped, that STS-1 SPE's locked STS-3 transport envelope with fixed pointer offset 522.
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9.15 Extracter PISO Extract block receives data from converts serial streams transmission. Extract block configured enable disable extraction individual tributaries within bus. also configured generate all-1s output transmit when alarm indication signalled particular tributary bus. 9.16 Inserter SIPO Insert block receives serial data from octants inserts DROP BUS. Insert block configured enable disable transmission individual tributaries DROP bus. 9.17 Clk/Data Converter OCTLIU configured setting SBI_EN SBI2CLK inputs) operate mode which LIUs disabled device performs conversion between interface serial clock data (see Figure eight tributaries converted serial format. serial data streams required share common clock frame pulse. egress direction (from egress clk/data), elastic stores provided align tributary outputs common clock frame alignment. 9.18 Serial PROM Interface serial PROM interface used configure OCTLIU absence microprocessor. single SPI-compatible serial PROM used configure number OCTLIU devices simultaneously (provided such devices intended configured identically) connecting devices cascade shown Figure Figure Serial PROM Cascade Interface
SRCASC HOLD
SRCASC
SREN SRCLK SRDI SRDO
SRCEN SRCCLK n.c. SRCDO
SREN SRCLK SRDI SRDO
SRCEN SRCCLK SRCDO
PROM
OCTLIU Cascade Master
OCTLIU Cascade Slave
SPI-compatible PROMs organised 8-bit words. contents PROM read sequentially starting address continuing until specially coded stop command encountered. Each configuration command coded 3-bytes follows:
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Figure Serial PROM Command Format
Code1
Code0
Reg[13:8] Reg[7:0] Data[7:0]
Reg[13:0] specifies OCTLIU registers defined Table Data[7:0] value written specified register. Commands interpreted depending Code1 Code0 bits follows: Table Serial PROM Commands Code Bits Code0 Special Command Write Data[7:0] Reg[13:0] only SRCODE Write Data[7:0] Reg[13:0] only SRCODE Write Data[7:0] Reg[13:0] regardless value SRCODE Action
Code1
SRCODE input OCTLIU provides means execute configuration instructions conditionally. different configuration sequences stored single PROM (for operation, example) SRCODE input used select which will applied. Different OCTLIU devices cascade have their SRCODE inputs different values. When Code1 Code0 `0', Reg[13:0] Data[7:0] fields interpreted special command, register/data pair. following special commands defined: Table Serial PROM Special Commands Action Resume acting upon register write commands. Only meaningfull 3FFD command (see below) previously been received. No-op. Ignore subsequent register write commands. This command only acted upon first OCTLIU cascade which receives which already ignoring register write commands. OCTLIU which acts upon this command does propagate command down cascade, instead substitutes 3FFC special command.
Reg[13:0] 3FFB 3FFC 3FFD
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Reg[13:0] 3FFE 3FFF
Action Pause Data[7:0] 4096 XCLK periods before reading next PROM command. Stop, i.e. configuration OCTLIU finished.
`ignore subsequent register write commands' command used configure multiple OCTLIU's cascade individually (for example, allocate different tributaries different OCTLIU devices). provides means progressively `switch off' each device cascade once been configured. Consider example following sequence configuration commands: Command (hex) C00102 3FFD00 C00103 3FFD00 C00104 Explanation Write register devices cascade, regardless SRCODE. (Subsequent configuration commands acted upon devices cascade.) First device cascade ignores further register writes. Write register devices cascade except first, regardless SRCODE. (Subsequent configuration commands acted upon devices cascade except first.) Second device cascade ignores further register writes. Write register devices cascade except first two, regardless SRCODE. (Subsequent configuration commands acted upon devices cascade except first second.)
pause command used, example, allow clock synthesis circuitry within block time stablise before configuring rest device. 9.19 JTAG Test Access Port JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported. 9.20 Microprocessor Interface Microprocessor Interface Block provides normal test mode registers, interrupt logic, logic required connect Microprocessor Interface. normal mode registers required normal operation, test mode registers used enhance testability OCTLIU.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation OCTLIU. Normal mode registers opposed test mode registers) selected when A[10] low. Register Memory Table below shows where normal mode registers accessed. OCTLIU contains master configuration, SBI, registers sets T1/E1 registers. Where only present, registers apply entire device. Where sets present, each registers apply single octant OCTLIU. convention, where sets registers present, address space 000H 07FH applies octant 080H 0FFH applies octant etc, 380H 3FFH octant reset OCTLIU defaults mode. proper operation some register configuration expected. default interrupts will enabled, automatic alarm generation disabled. Notes Normal Mode Register Bits: Writing values into unused register bits effect. Reading back unused bits produce either logic logic hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling OCTLIU determine programming state chip. Writeable normal mode register bits cleared zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect OCTLIU operation unless otherwise noted. Certain register bits reserved. These bits associated with functions that unused this application. ensure that OCTLIU operates intended, reserved register bits must only written with their default values unless otherwise stated. Similarly, writing reserved registers should avoided unless otherwise stated.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
10.1 Normal Mode Register Memory Table Addr 000H 080H, 100H, 180H, 200H, 280H, 300H, 380H 001H 081H, 101H, 181H, 201H, 281H, 301H, 381H 002H 082H, 102H, 182H, 202H, 282H, 302H, 382H 003H 083H, 103H, 183H, 203H, 283H, 303H, 383H 004H 084H, 104H, 184H, 204H, 284H, 304H, 384H 005H 085H, 105H, 185H, 205H, 285H, 305H, 385H 006H 086H, 106H, 186H, 206H, 286H, 306H, 386H 007H 087H, 107H, 187H, 207H, 287H, 307H, 387H 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH Normal Mode Register Memory Register Reset Revision Device Reserved Global Configuration Clock Monitor Reserved Master Interrupt Source Reserved Master Interrupt Source Reserved Master Test Control Reserved Master Test Control Reserved Configuration Reserved Reserved Reserved Receive Line Interface Configuration Receive Line Interface Configuration Transmit Line Interface Configuration Transmit Line Interface Timing Options Clock Monitor Pulse Template Selection
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH 010H 03FH 090H 0BFH 110H 13FH 190H 1BFH 210H 23FH 290H 2BFH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H
Register Line Interface Interrupt Source PMON Update Line Interface Interrupt Source Line Interface Diagnostics Line Interface PRBS Position Reserved Reserved Reserved Reserved Reserved Reserved INSBI Control INSBI FIFO Underrun Interrupt Status INSBI FIFO Overrun Interrupt Status INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping INSBI Page Octant Tributary Mapping
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 322H 323H 324H 325H 326H 327H 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 33FH 390H 391H 392H 393H 394H 395H 396H 397H 398H 399H 39AH 39FH 3A0H 3A1H
Register INSBI Page Octant Tributary Mapping INSBI Link Enable INSBI Link Enable Busy INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Tributary Control INSBI Minimum Depth INSBI FIFO Thresholds INSBI Reserved INSBI Depth Check Interrupt Status INSBI Master Interrupt Status INSBI Reserved EXSBI Control EXSBI FIFO Underrun Interrupt Status EXSBI FIFO Overrun Interrupt Status EXSBI Parity Error Interrupt Reason EXSBI Depth Check Interrupt Status EXSBI Master Interrupt Status EXSBI Minimum Depth EXSBI FIFO Thresholds EXSBI Link Enable EXSBI Link Enable Busy EXSBI Reserved EXSBI Tributary Control EXSBI Tributary Control
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 3A2H 3A3H 3A4H 3A5H 3A6H 3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH 3AFH 3B0H 3B1H 3B2H 3B3H 3B4H 3B5H 3B6H 3B7H 3B8H 3BFH 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H
Register EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Tributary Control EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Page Octant Tributary Mapping EXSBI Reserved ELST Configuration ELST Interrupt Enable/Status PDVD Reserved PDVD Interrupt Enable/Status
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H 048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH 04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H
Register XPDE Reserved XPDE Interrupt Enable/Status XIBC Control XIBC Loopback Code RJAT Interrupt Status RJAT Reference Clock Divisor (N1) Control RJAT Output Clock Divisor (N2) Control RJAT Configuration TJAT Interrupt Status TJAT Reference Clock Divisor (N1) Control TJAT Output Clock Divisor (N2) Control TJAT Configuration IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code IBCD Deactivate Code CDRC Configuration CDRC Interrupt Control
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H 059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H 05AH, 0DAH, 15AH, 1DAH, 25AH, 2DAH, 35AH, 3DAH 05BH, 0DBH, 15BH, 1DBH, 25BH, 2DBH, 35BH, 3DBH 05CH, 0DCH, 15CH, 1DCH, 25CH, 2DCH, 35CH, 3DCH 05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH 05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H 063H, 0E3H, 163H, 1E3H, 263H, 2E3H, 363H, 3E3H 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H 065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H 067H, 0E7H, 167H, 1E7H, 267H, 2E7H, 367H, 3E7H
Register CDRC Interrupt Status CDRC Alternate Loss Signal PMON Interrupt Enable/Status PMON Reserved PMON Reserved PMON Reserved PMON Reserved PMON Reserved PMON Count (LSB) PMON Count (MSB) PRBS Generator/Checker Control PRBS Checker Interrupt Enable/Status PRBS Pattern Select PRBS Reserved PRBS Error Count PRBS Error Count PRBS Error Count PRBS Reserved
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH 06EH, 0EEH, 16EH, 1EEH, 26EH, 2EEH, 36EH, 3EEH 06FH, 0EFH, 16FH, 1EFH, 26FH, 2EFH, 36FH, 3EFH 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H 071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H 075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H 076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H 079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H
Register XLPG Control/Status XLPG Pulse Waveform Scale XLPG Pulse Waveform Storage Write Address XLPG Pulse Waveform Storage Write Address XLPG Pulse Waveform Storage Data XLPG Reserved XLPG Reserved XLPG Reserved RLPS Configuration Status RLPS ALOS Detection/Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Period RLPS Equalization Indirect Address RLPS Equalization Read/WriteB Select RLPS Equalizer Loop Status Control RLPS Equalizer Configuration RLPS Equalization Indirect Data Register RLPS Equalization Indirect Data Register
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Addr 07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH 07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH 07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH 07EH, 0FEH, 17EH, 1FEH, 27EH, 2FEH, 37EH, 3FEH 07FH, 0FFH, 17FH, 1FFH, 27FH, 2FFH, 37FH, 3FFH 400H 7FFH
Register RLPS Indirect Data Register RLPS Indirect Data Register RLPS Voltage Thresholds RLPS Voltage Thresholds RLPSReserved RLPS Reserved Reserved Test
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 000H: Reset Revision Device RESET: RESET implements software reset. RESET logic OCTLIU held reset. This self-clearing; therefore, logic must written bring OCTLIU reset. Holding OCTLIU reset state effectively puts into low-power, stand-by mode. hardware reset clears RESET bit, thus deasserting software reset. TYPE: device identification bits, TYPE[2:0], fixed value "100" version identification bits, ID[3:0], fixed value representing version number OCTLIU. Type Function RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0] Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 001H: Global Configuration Clock Monitor XCLKA: XCLK active (XCLKA) detects high transitions XCLK input. XCLKA high rising edge XCLK, when this register read. lack transitions indicated register reading low. This register read periodic intervals detect clock failures. REFCLKA: REFCLK active (REFCLKA) detects high transitions REFCLK input. REFCLKA high rising edge REFCLK, when this register read. lack transitions indicated register reading low. This register read periodic intervals detect clock failures. SIMUL_REGWR: Simultaneous Register Write (SIMUL_REGWR) enables registers octants written simultaneously. When SIMUL_REGWR high, write octant register will result same data also being written simultaneously corresponding registers belonging other octants. When SIMUL_REGWR low, write register will result addressed register, that register only, being written. Note SIMUL_REGWR must prior reading OCTLIU register. SBI_SYNCH: Synchronous Mode (SBI_SYNCH) configures INSBI operate Synchronous mode when Synchronous mode should only selected when device operating clk/data converter (SBI2CLK input tied high). When operating synchronous mode, ICLK_OUT IFP_OUT outputs must used clock Type Function XCLKA REFCLKA SIMUL_REGWR SBI_SYNCH RSYNC_SEL[2] ELST_SEL[2] RSYNC_SEL[1] ELST_SEL[1] RSYNC_SEL[0] ELST_SEL[0] E1/T1B Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
frame pulse references, need looped back ICLK_IN IFP_IN inputs. synchronous mode, loopback done internally ICLK_IN IFP_IN inputs ignored.) RSYNC_SEL[2:0]: When SBI2CLK input tied low, RSYNC Select register bits, RSYNC_SEL[2:0], select source RSYNC OCTLIU output. When RSYNC_SEL[2:0] "000", octant selected source. When RSYNC_SEL[2:0] "001", octant selected source. When RSYNC_SEL[2:0] "010", octant selected source. When RSYNC_SEL[2:0] "011", octant selected source. When RSYNC_SEL[2:0] "100", octant selected source. When RSYNC_SEL[2:0] "101", octant selected source. When RSYNC_SEL[2:0] "110", octant selected source. When RSYNC_SEL[2:0] "111", octant selected source. ELST_SEL[2:0]: When SBI2CLK input tied high, Elastic Store Select register bits, ELST_SEL[2:0], select source clock frame pulse used read data from Elastic Stores. clock frame pulse derived from tributaries de-mapped from output ECLK respectively. When ELST_SEL[2:0] "000", EXSBI link selected source. When ELST_SEL[2:0] "001", EXSBI link selected source. When ELST_SEL[2:0] "010", EXSBI link selected source. When ELST_SEL[2:0] "011", EXSBI link selected source. When ELST_SEL[2:0] "100", EXSBI link selected source. When ELST_SEL[2:0] "101", EXSBI link selected source. When ELST_SEL[2:0] "110", EXSBI link selected source. When ELST_SEL[2:0] "111", EXSBI link selected source. E1/T1B: global E1/T1B selects operating mode eight OCTLIU octants. E1/T1B logic 2.048 Mbit/s mode selected eight octants. E1/T1B logic 1.544 Mbit/s mode selected eight octants.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 002H: Master Interrupt Source LIU[8:1]: LIU[8:1] register bits allow software determine which octant's LIU(s) is/are producing interrupt INTB output pin. logic indicates interrupt being produced from corresponding octant. Reading this register does remove interrupt indication; within corresponding octant, corresponding block's interrupt status register must read remove interrupt indication. Type Function LIU[8] LIU[7] LIU[6] LIU[5] LIU[4] LIU[3] LIU[2] LIU[1] Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 003H: Master Interrupt Source INSBI, EXSBI: INSBI EXSBI register bits allow software determine whether INSBI and/or EXSBI blocks producing interrupt INTB output pin. logic indicates interrupt being produced from corresponding block. Reading this register does remove interrupt indication; corresponding block's interrupt status register must read remove interrupt indication. Type Function Unused Unused Unused Unused Unused Unused EXSBI INSBI Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 004H: Master Test Control Type Function Reserved Reserved Reserved Reserved Reserved Reserved HIZDATA HIZIO Default
This register used select OCTLIU test features. bits, except 7,6,5 reset zero hardware reset OCTLIU, software reset OCTLIU does affect state bits this register. HIZIO, HIZDATA: HIZIO HIZDATA bits control tri-state modes OCTLIU. While HIZIO logic output pins OCTLIU except data held highimpedance state. microprocessor interface still active. While HIZDATA logic data held high-impedance state which inhibits microprocessor read cycles.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 005H: Master Test Control Reserved: These bits must correct operation. Type Function Reserved Reserved Reserved Reserved Unused Unused Unused Unused Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 006H: Configuration MODE[2:0]: MODE[2:0] selects mode CSU. Table indicates required XCLK frequency, output frequencies each mode. Table Clock Synthesis Mode MODE[2:0] CSU_LOCK: CSU_LOCK used determine whether embedded clock synthesis unit (CSU) achieved phase frequency lock XCLK. CSU_LOCK polled repetitively persistently logic then divided down synthesized clock frequency within XCLK frequency. persistent logic indicate mismatch between actual expected XCLK frequency problem with analogue supplies (CAVS CAVD). IDDQ_EN: IDDQ enable (IDDQ_EN) used configure embedded IDDQ tests. When IDDQ_EN logic IDDQEN Master Test Control register XCLK frequency 2.048 1.544 Reserved Reserved Reserved 2.048 Transmit clock frequency 2.048 1.544 Reserved Reserved Reserved 1.544 Type Function CSU_RESET IDDQ_EN Unused Unused CSU_LOCK MODE[2] MODE[1] MODE[0] Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
logic digital outputs pulled ground. When either IDDQ_EN IDDQEN logic HIGHZ XLPG Line Driver Configuration register must also logic CSU_RESET: Setting CSU_RESET logic causes embedded forced frequency much lower than normal operation.
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H: Receive Line Interface Configuration LLB_AIS: When LLB_AIS logic will generate receive data output whenever line loopback active. When LLB_AIS logic receive path will operate normally, regardless whether line loopback active. LLB_AIS logic inserted manually RAIS register bit. AUTO_LLB: When AUTO_LLB logic will activate deactivate line loopback automatically upon detection line loopback activate/deactivate codes IBCD. AUTO_LLB only valid mode must logic mode. LOS_SBI: LOS_SBI enables indication loss signal over interface. When LOS_SBI logic loss signal will result (alarm) affected tributary being asserted interface. When LOS_SBI logic tributary's will LOS_AIS: LOS_AIS logic inserted receive path duration loss signal condition. [ref: T1.403-1995 Annex LOS_AIS logic inserted manually RAIS register bit. RDUAL: RDUAL configures receive path dual-rail (bipolar) operation. When RDUAL logic sampled bipolar positive negative pulses output RDP[n] RDN[n] respectively. When RDUAL logic sampled unipolar data Type Function LLB_AIS AUTO_LLB LOS_SBI LOS_AIS RDUAL RINV RFALL Default
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PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
output RDP[n] (decoded according AMI, B8ZS HDB3) line code violations excessive zeros signalled RLCV[n]. RDUAL logic PDVD, IBCD PRBS blocks, also ability generate AIS, disabled receive path. BPV: mode, enables only bipolar violations indicate line code violations accumulated PMON Count Registers. When logic BPVs (provided they part valid B8ZS signature B8ZS line coding used) generate indication increment PMON counter. When logic both BPVs (provided they part valid B8ZS signature B8ZS line coding used) excessive zeros (EXZ) generate indication increment PMON counter. Excessive zeros sequence zeros greater than fifteen bits long AMI-coded signal greater than seven bits long B8ZS-coded signal. mode, enables only bipolar violations indicate line code violations accumulated PMON Count Registers. (The O162 CDRC Configuration register provides definitions.) When logic BPVs (provided they part valid HDB3 signature HDB3 line coding used) generate indication increment PMON counter. When logic both BPVs (provided they part valid HDB3 signature HDB3 line coding used) excessive zeros (EXZ) generate indication increment PMON counter. Excessive zeros sequence zeros greater than fifteen bits long AMI-coded signal greater than four bits long HDB3-coded signal. RINV: When RINV logic receive digital outputs RDP[n] RDN/RLCV[n] assumed active output data indications inverted. When RINV logic receive digital outputs RDP[n] RDN/RLCV[n] assumed active high. RINV must when interface enabled (SBI_EN RFALL: When RFALL logic RDP[n] RDN/RLCV[n] outputs updated falling edges RCLK[n]. When RFALL logic outputs updated rising edges RCLK[n]. RFALL must when interface enabled (SBI_EN
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PRELIMINARY DATASHEET PMC- 2001578 ISSUE
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H: Receive Line Interface Configuration RJATBYP: RJATBYP disables jitter attenuation receive direction. When receive jitter attenuation being used, setting RJATBYP logic will reduce latency through receiver section typically bits. When RJATBYP logic LIU's RSYNC output jitter attenuated. When RJAT bypassed, octant's RSYNC jitter attenuated. RSYNC_ALOSB: RSYNC_ALOSB controls source loss signal condition used control behaviour receive reference presented RSYNC output. RSYNC_ALOSB logic analogue loss signal used. RSYNC_ALOSB logic digital loss signal used. When loss signal state, RSYNC output derived from XCLK held high, determined RSYNC_MEM bit. When loss signal state, RSYNC output derived from receive recovered clock selected octant. octant used source RSYNC determined RSYNC_SEL[2:0] bits. RSYNC_MEM: RSYNC_MEM controls octant's RSYNC output under loss signal condition determined RSYNC_ALOSB register bit). When RSYNC_MEM logic octant's RSYNC output held high during loss signal condition. When RSYNC_MEM logic octant's RSYNC output derived from line rate clock during loss signal condition. RSYNCSEL: RSYNCSEL selects frequency receive reference presented octant's RSYNC output. RSYNCSEL logic octant's RSYNC will clock. Type Function RJATBYP Unused Unused Unused Unused RSYNC_ALOSB RSYNC_MEM RSYNCSEL Default
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY DATASHEET PMC- 2001578 ISSUE
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
RSYNCSEL logic octant's RSYNC will 1.544 (T1) 2.048 (E1) clock.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY DATASHEET PMC- 2001578 ISSUE
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH: Transmit Line Interface Configuration TJATBYP: TJATBYP enables transmit jitter attenuator removed from transmit data path. When transmit jitter attenuator bypassed, latency through transmitter section reduced typically bits. TAISEN: TAISEN enables interface generate unframed all-ones alarm TXTIP[n] TXRING[n]. When TAISEN logic bipolar TXTIP[n] TXRING[n] outputs forced pulse alternately, creating all-ones signal. transition transmitting TXTIP[n] TXRING[n] outputs done such avoid introducing bipolar violations. diagnostic digital loopback point prior insertion point. (Implementation note. TAISEN priority over TAUXP, which turn priority over TDATINV.). TAUXP: TAUXP enables interface generate unframed alternating zeros ones (i.e. 010101.) auxiliary pattern (AUXP) TXTIP[n] TXRING[n]. When TAUXP logic bipolar TXTIP[n] TXRING[n] outputs forced pulse alternately every other cycle. transition transmitting AUXP TXTIP[n] TXRING[n] outputs done such avoid introducing bipolar violations. diagnostic digital loopback point prior AUXP insertion point. SBI_AIS: SBI_AIS enables insertion transmit path response alarm indication from interface. When SBI_AIS logic setting (alarm) Type Function TJATBYP TAISEN TAUXP SBI_AIS TDUAL TINV TRISE Default
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY DATASHEET PMC- 2001578 ISSUE
PM4318 OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
tributary interface causes bipolar TXTIP[n] TXRING[n] outputs forced pulse alternately, creating all-ones signal. transition transmitting TXTIP[n] TXRING[n] outputs done such avoid introducing bipolar violations. diagnostic digital loopback point prior insertion point. TDUAL: TDUAL configures transmit path dual-rail (bipolar) operation. When TDUAL logic bipolar positive negative data input TDP[n] TDN[n] respectively. When TDUAL logic unipolar data input TDP[n] TDN[n] ignored. TDUAL must logic when operating mode (i.e. when SBI_EN input logi
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