NOMENCLATURE Address Inputs Data Data Chip Enable Output Enable Intern
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
NOMENCLATURE Address Inputs Data Data Chip Enable Output Enable Internal Connection Power Supply Ground Write Enable
description
TMS29F002T/B 8-bit 152-bit), single-supply, programmable read-only memory device that electrically erased reprogrammed. This device organized bits, divided into seven sectors: 16K-byte protected-boot sector 8K-byte sectors 32K-byte sector Three 64K-byte sectors
combination sectors marked read-only erased. Full chip erasure also supported. Sector data protection afforded methods that disable combination sectors from write read operations using standard programming equipment. on-chip state machine provides on-board algorithm that automatically pre-programs erases sector before automatically programs verifies program data specified address. command compatible with that Joint Electronic Device Engineering aware that important notice compatible with warranty, 2M-byte electrically erasable Please Council (JEDEC) standards concerning availability, standard JEDEC critical applications Texas Instruments semiconductor (EEPROM) command set. suspend/resume data sheet. programmable read-only memoryproducts disclaimers thereto appears thisfeature allows access
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 1997, Texas Instruments Incorporated
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Single Power Supply Supports Read/Write Operation Organization: Bits Array-Blocking Architecture 16K-Byte Protected-Boot Sector 8K-Byte Parameter-Sectors 32K-Byte Sector Three 64K-Byte Sectors Combination Sectors Erased. Supports Full-Chip Erase Combination Sectors Marked Read-Only Boot-Code Sector Architecture Sector Bottom Sector Sector Protection Hardware Protection Method That Disables Combination Sectors From Write Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms Automatically Pre-Programs Erases Sector Automatically Programs Verifies Program Data Specified Address JEDEC Standards Compatible With JEDEC Byte Pinouts Compatible With JEDEC EEPROM Command Fully Automated On-Chip Erase Program Operations
Program/Erase Cycles Power Dissipation Current Consumption 40-mA Typical Active Read 60-mA Typical Program/Erase Current Less Than 100-µA Standby Current Inputs/Outputs TTL-Compatible Erase Suspend/Resume Supports Reading Data From, Programming Data Sector Being Erased 40-Pin Thin Small Outline Package (TSOP) (DCD Suffix) Detection Program/Erase Operation Data Polling Toggle Feature Program/Erase Cycle Completion High-Speed Data Access Commercial 70°C Extended -40°C 85°C
TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
description (continued)
unaltered memory blocks during section-erase operation. outputs this device TTL-compatible. Additionally, erase/suspend/resume feature supports reading data from, programming data sector that being erased. Device operations selected writing JEDEC-standard commands into command register using standard microprocessor write timings. command register acts input internal-state machine which interprets commands, controls erase programming operations, outputs status device, outputs data stored device, outputs device algorithm-selection code. initial power device defaults read mode. device power dissipation with 40-mA active read byte mode, 60-mA typical program/erase current mode, less than 100-mA standby current. These devices offered with access times. Table Table show sector-address ranges. TMS29F002T/B offered 40-pin (DCD suffix) thin small-outline package.
device symbol nomenclature
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TMS29Fxxx
Temperature Range Commercial (0°C 70°C) Extended 40°C 85°C) Package Type Thin Small-Outline Package Program/Erase Endurance Speed Option Boot Code Selection Architecture Sector Bottom Sector Device Number Description
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logic symbol
FLASH MEMORY
[PWR DWN] (READ) (WRITE)
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. numbers shown package.
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
block diagram
Erase Voltage Generator Input/Output Buffers
State Control
Command Registers
Voltage Generator
Data Latch
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Chip-Enable Output-Enable Logic
Detector Timer X-Decoder Cell Matrix Y-Decoder Y-Gating
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operation
Table Table sector-address ranges TMS29F002T/B. Table Top-Boot Sector-Address Ranges
SECTOR SIZE 16K-Byte 8K-Byte 8K-Byte 32K-Byte 64K-Byte 64K-Byte 64K-Byte ADDRESS RANGE 30000H-3FFFFH 3A000H-3BFFFH 38000H-39FFFH 30000H-37FFFH 20000H-2FFFFH 10000H-1FFFFH 00000H-0FFFFH
address range
Table Bottom-Boot Sector-Address Ranges
SECTOR SIZE 64K-Byte 64K-Byte 64K-Byte 32K-Byte 8K-Byte 8K-Byte 16K-Byte ADDRESS RANGE 30000H-3FFFFH 20000H-2FFFFH 10000H-1FFFFH 08000H-0FFFFH 06000H-07FFFH 04000H-05FFFH 00000H-03FFFH
address range
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operation (continued)
Table operation modes TMS29F002T/B. Table Operation Mode
MODE Algorithm-selection mode power supply Read Output disable Standby write inhibit FUNCTIONS DQ0-DQ7 Manufacturer-Equivalent Code (TMS29F002) Data Hi-Z Hi-Z Data Data
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Verify sector protect Legend: Logic Logic high 12.0 VIH. VIL, then VIL. permits write operations. Table valid address data during write.
read mode logic-low signal applied pins allows reading output TMS29F002T/B When more '29F002T/B devices connected parallel, output device read without interference. device selection. gates data output onto from selected device. address-access time (tAVQV) delay from stable address valid output data. chip-enable (CE) access time (tELQV) delay from stable addresses valid output data. output-enable access time (tGLQV) delay from valid output data, when addresses stable least duration tAVQV-tGLQV. standby mode supply current reduced applying logic-high level enter standby mode. standby mode, outputs placed high-impedance state. Applying CMOS logic-high level reduces current Applying logic-high level reduces current '29F002T/B deselected during erasure programming, device continues draw active current until operation complete. output disable When either high, output from device disabled output pins (DQ0-DQ7) placed high-impedance state. automatic sleep mode '29F002 built-in feature called automatic sleep mode minimize device energy consumption. mode, which independent enabled when addresses remain stable Typical sleep-mode current Sleep mode does affect output data, which remains latched available system.
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algorithm selection mode algorithm-selection mode provides access binary code that matches device with proper programming erase command operations. This mode activated when (11.5 12.5 placed address Address pins must logic low. bytes code accessed toggling address from VIH. Address pins other than logic logic high. algorithm-selection mode also read using command register, which useful when available placed address Table shows binary algorithm-selection codes. Table Algorithm-Selection Codes (5-V Single Power Supply)
CODE Manufacturer equivalent code TMS29F002T TMS29F008B Sector protection
VIL, VIL, VIL,
erasure programming Erasure programming '29F002 accomplished writing sequence commands using standard-microprocessor-write timings. commands written command register input command-state machine. command-state machine interprets command entered initiates program, erase, suspend, resume operations instructed. command-state machine acts interface between write-state machine external-chip operations. write-state machine controls voltage generation, pulse generation, preconditioning, verification contents memory. Program block-/chip-erase functions fully automatic. Once program erase operation reached, device resets internally read mode. drops below low-voltage-detect level, programming erase operation aborted subsequent writes ignored until level greater than VLKO. control pins must correct logically prevent unintentional command writes programming erasing. command definitions Device operating modes selected writing specific address data sequences into command register. Table defines valid command sequences. Writing incorrect address data values writing them incorrect sequence causes device reset read mode. command register does occupy addressable memory location. register stores command sequence, along with address data needed memory array. Commands written setting low, high, bringing from high low. Addresses latched falling edge data latched rising edge Holding toggling used alternative. switching characteristics write/erase/program-operations section specific timing information.
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command definitions (continued) Table Command Definitions
COMMAND Read/reset Read/reset Algorithm selection Program CYCLES CYCLE ADDR DATA XXXH 555H 555H 555H 555H 2AAH 2AAH 2AAH 2AAH 2AAH 555H 555H 555H 555H 555H 555H 555H
CYCLE ADDR DATA
CYCLE ADDR DATA
CYCLE ADDR DATA
CYCLE ADDR DATA
CYCLE ADDR DATA
2AAH 2AAH 555H
Chip erase
Sector erase Sector-erase suspend Sector-erase resume
555H
XXXH XXXH
Erase suspend valid during sector-erase operation Erase resume valid only after erase suspend
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LEGEND: Address location read Address location programmed Address sector erased Addresses A13:A17 select seven sectors. Data read selected address location Data programmed selected address location Unless otherwise noted, address bits don't care.
read/reset command
read reset mode activated writing either read/reset command sequences into command register. device remains this mode until other valid command sequences input command register. Memory data available read mode read with standard microprocessor read-cycle timing. power device defaults read/reset mode. read/reset command sequence required memory data available.
algorithm-selection command
algorithm-selection command allows access binary code that matches device with proper programming erase command operations. After writing three-bus-cycle command sequence, first byte algorithm-selection code read from address XX00h. second byte code read from address XX01h (see Table This mode remains effect until another valid command sequence written device.
program command
Programming four-bus-cycle command sequence. first three cycles device into program-setup state. fourth cycle loads address location data programmed into device. addresses latched falling edge data latched rising edge fourth cycle. rising edge starts program operation. embedded programming function automatically provides needed voltage timing program verify cell margin. further commands written device during program operation ignored.
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program command (continued)
Programming performed address location sequence. When erased, bits logic-high state. Logic lows programmed into device. Only erase operation change bits from logic lows logic highs. Attempting program into that been programmed previously causes internal-pulse counter exceed pulse-count limit, which sets exceed-time-limit indicator (DQ5) logic-high state. automatic-programming operation complete when data (DQ7) equivalent data written this bit, which time device returns read mode addresses longer latched. Figure shows flowchart typical device-programming operation.
chip-erase command
Chip erase six-bus-cycle command sequence. first three cycles device into erase-setup state. next cycles unlock erase mode. sixth cycle loads chip-erase command. This command sequence required ensure that memory contents erased accidentally. rising edge starts chip-erase operation. further commands written device during chip-erase operation ignored. embedded chip-erase function automatically provides voltage timing needed program verify memory cells prior electrical erase then erases verifies cell margin automatically without programming memory cells prior erase. Figure shows flow chart typical chip-erase device operation.
sector-erase command
Sector erase six-bus-cycle command sequence. first three cycles cause device into erase-setup state. next cycles unlock erase mode. sixth cycle loads sector-erase command sector-address location erased. address location within desired sector used. addresses latched falling edge sector-erase command (30h) latched rising edge sixth cycle. After delay from rising edge sector-erase operation begins selected sector(s). Additional sectors selected erased concurrently during sector-erase command sequence. each additional sector selected erase, another cycle issued. cycle loads next sector-address location sector-erase command. time between previous cycle start next cycle must less than otherwise sector location loaded. time delay from rising edge last starts sector-erase operation. there falling edge within time delay, timer reset. seven sector-address locations loaded sequence. state delay timer monitored using sector-erase delay indicator (DQ3). logic low, time delay expired. operation status section description. command other than erase suspend (B0h) sector erase (30h) written device during sector-erase operation causes device exit sector-erase mode. contents sector(s) selected erase valid. complete sector-erase operation, sector-erase command sequence must repeated. embedded sector-erase function automatically provides needed voltage timing program verify memory cells prior electrical erase then erases verifies cell margin automatically. Programming memory cells prior erase required. operation status section full description. Figure shows flow chart typical sector-erase device operation.
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erase-suspend command
erase-suspend command (B0h) allows interruption sector-erase operation read data from unaltered sectors device. Erase-suspend one-bus-cycle command. addresses high erase-suspend command (B0h) latched rising edge Once sector-erase operation progress, erase-suspend command requests internal-write-state machine halt operation predetermined breakpoints. erase-suspend command valid only during sector-erase operation invalid during programming chip-erase operations. sector-erase delay timer expires immediately erase-suspend command issued while delay active. After erase suspend issued, device takes between suspend operation. toggle must monitored determine when suspend been executed. When toggle-bit stops toggling, data read from sectors that selected erase. operation status section full description. Reading from sector selected erase result invalid data. Once sector-erase operation suspended, reads program sector being erased performed. This command applicable only during sector-erase operation. other command written during erase-suspend mode suspended sector ignored. erase-resume command
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erase-resume command (30h) restarts suspended sector-erase operation from point where halted. Erase resume one-bus-cycle command. addresses erase-resume command (30h) latched rising edge When erase-suspend/erase-resume command combination written, internal-pulse counter (exceed timing limit) reset. erase-resume command valid only erase-suspend state. After erase-resume command executed, device returns valid sector-erase state further writes erase-resume command ignored. After device resumed sector-erase operation, another erase-suspend command issued device.
operation status
status device during automatic-programming algorithm, chip-erase, automatic-erase algorithm determined three ways:
DQ7: Data polling DQ6: Toggle
status-bit definitions During operation automatic embedded program erase functions, status device determined reading data state designated outputs. data-polling (DQ7) toggle (DQ6) require multiple successive reads observe change state designated output. Table defines values status flags.
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status-bit definitions (continued) Table Operation Status Flags
DEVICE OPERATION Programming Program/erase auto-erase progress Erase-suspend Erase suspend mode Program erase suspend Programming Exceeded time limits Program/erase auto erase Program erase suspend Successful operation complete Programming complete Sector/chip erase complete Erase-sector address Non-erase sector address
data-polling (DQ7) data-polling-status function outputs complement data latched into data register while write-state machine engaged program erase operation. Data changing from complement true indicates operation. Data-polling available only during programming, chip-erase, sector-erase, sector-erase-timing delay. Data-polling valid after rising edge last cycle command sequence loaded into command register. Figure shows flow chart data-polling. During program operation, reading outputs complement data programmed selected address location. Upon completion, reading outputs true data loaded into program-data register. During erase operations, reading outputs logic low. Upon completion, reading outputs logic high. Also, data-polling must performed sector address that within sector that being erased. Otherwise, status invalid. When using data-polling, address must remain stable throughout operation. During data-polling read, while logic low, data change asynchronously. Depending read timing, system read valid data DQ7, while other pins still invalid. subsequent read device valid. Figure data-polling timing diagram. toggle-bit (DQ6) toggle-bit status function outputs data which toggles between logic high logic while write-state machine engaged program erase operation. When stops toggling after consecutive reads same address, operation complete. toggle-bit available only during programming, chip erase, sector erase, sector-erase-timing delay. Toggle-bit data valid after rising edge last cycle command sequence loaded into command register. Figure shows flow chart toggle-bit-status-read algorithm. Depending read timing, stop toggling while other pins still invalid. subsequent read device valid.
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toggle, data, Tog= toggle DQ4, DQ1, reserved future use. toggled when sector-address applied erasing sector. cannot toggled when sector-address applied non-erasing sector. used determine which sectors erasing which not. Status flags apply when outputs read from address non-erase-suspend operation. high (exceeded timing limits), successive reads from problem sector causes toggle.
TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
exceed time limit (DQ5) program erase operations internal-pulse counter limit number pulses applied. pulse-count limit exceeded, logic-high data state, indicating that program erase operation failed. does change from complemented data true data does stop toggling when read. continue operation, device must reset. This condition occurs when attempting program logic-high state into that been programmed previously logic low. Only erase operation change bits from logic logic high. After reset, device functional erased reprogrammed. sector-load-timer (DQ3) sector-load-timer status bit, DQ3, used determine whether time load additional sector addresses expired. After completion sector erase command sequence, remains logic This indicates that another sector-erase command sequence issued. logic high, indicates that delay expired attempts issue additional sector-erase commands ignored. sector-erase command section description. data-polling toggle valid during 100-µs time delay used determine valid sector-erase command been issued. ensure additional sector-erase commands have been accepted, status should read before after each additional sector-erase command. logic both reads, additional sector-erase command accepted. toggle (DQ2) state determines whether device algorithmic erase mode erase-suspend mode. toggles successive reads issued erasing erase-suspended sector, assuming case latter that device erase suspend read mode. also toggles when becomes logic high timer-exceed limit reads issued failed sector. does toggle other sector fail. When device erase-suspend program mode, successive reads from non-erase-suspended sector causes logic high DQ2. sector-protect programming sector-protect programming mode activated when VIL, address control forced VID. Address VIH.The sector-select-address pins used select sector protected. Address pins A12-A0 pins must stable either high. Once addresses stable, pulsed causing programming begin falling edge terminate rising edge Figure flow chart sector-protect algorithm. Commands program erase protected sector change data contained sector. Attempts program erase protected sector causes data-polling toggle-bit (DQ6) operate from 2-µs 100-µs then return valid data.
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sector-protect verify Verification sector-protection programming activated when high, low, low, address VID. Address pins VIL, VIH. sector-address pins select sector that verified. other addresses VIL. sector that selected protected, output 01h. sector protected, output 00h. Sector-protect verify also read using algorithm-selection command. After issuing three-bus-cycle command sequence, sector-protection status read DQ0. address pins VIL, VIH, VIL. sector address pins select sector verified. remaining addresses VIL. sector selected protected, outputs logic-high state. sector selected protected, outputs logic-low state. This mode remains effect until another valid command sequence written device. Figure shows timing diagram sector-protect operation Figure flowchart sector-protect algorithm. sector unprotect Prior sector unprotect, sectors must protected using sector-protect programming mode. sector unprotect activated when address control forced VID. Address pins while VIL. sector-select address pins VIH. sectors unprotected parallel. Once inputs stable, pulsed causing unprotect operation begin falling edge terminate rising edge Figure flow chart sector-unprotect algorithm Figure shows timing diagram sector-unprotect operation. sector-unprotect verify Verification sector unprotect activated when VIH, VIL, =VIL address VID. Select sector verified. Address pins VIH, VIL. other addresses VIL. sector selected protected, output 01h. sector protected, output 00h. Sector unprotect also read using algorithm-selection command. write lockout During power power down operations, write cycles locked less than VLKO. VLKO, command input disabled device reset read mode. power low, low, high, device does accept commands rising edge device automatically powers read mode. glitching Pulses less than five (typical) issue write cycle. power supply considerations Each device should have 0.1-µF ceramic capacitor connected between suppress circuit noise. Printed circuit traces should appropriate handle current demand minimize inductance.
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range inputs except (see Note 13.5 Output voltage range (see Note Operating free-air temperature range during read erase program, 70°C 40°C 85°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect VSS. voltage input output undershoot periods less than Figure voltage input output overshoot periods less than Figure
recommended operating conditions
VCC+0.5 VCC+0.5 12.5 UNIT
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VLKO
Supply voltage High-level High level input voltage level input voltage Low-level Algorithm selection sector protect input voltage lock-out voltage Operating free temperature free-air version version CMOS CMOS
VCC-0.5 -0.5 -0.5 11.5
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electrical characteristics over recommended ranges supply voltage operating free-air temperature
PARAMETER TTL-input level ICC1 ICC2 ICC3 ICC5 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) High-voltage current (standby) supply current (standby) TTL-input level CMOS-input level CMOS-input level CMOS-input level TEST CONDITIONS MIN, MIN, MIN, MIN, -2.5 -2.5 VCC-0.4 0.85*VCC 0.45 UNIT
MAX, =VSS VCC, VIH,VCC 0.2, VIL, VIL,
supply current (see Notes supply current (see Note Automatic sleep mode (see Notes
capacitance over recommended ranges supply voltage operating free-air temperature,
PARAMETER Input capacitance (All inputs except Input capacitance (A9, Output capacitance TEST CONDITIONS UNIT
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NOTES:
current read mode, switching IOUT current while erase program operation progress Automatic sleep mode entered when addresses remain stable
TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
PARAMETER MEASUREMENT INFORMATION
(see Note
Output Under Test
NOTE includes probe fixture capacitance.
testing input/output waveforms
0.45
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NOTE testing inputs driven logic high 0.45 logic low. Timing measurements made logic high logic both inputs outputs. Each device should have 0.1-µF ceramic capacitor connected between closely possible device pins.
Figure Test Output Load Circuit
+0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
Figure Maximum Positive Overshoot Waveform
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switching characteristics over recommended ranges supply voltage operating free-air temperature, read-only operation
PARAMETER tc(R) ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) Cycle time, read Access time, address Access time, Access time, Disable time, high impedance Disable time, high impedance Enable time, impedance Enable time, impedance ALTERNATE SYMBOL tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX '29F002-70 '29F002-80 UNIT
th(D) Hold time, output from address change tREADY RESET read
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switching characteristics over recommended ranges supply voltage operating free-air temperature, controlled
PARAMETER tc(W) tc(W)ER th(A) th(D) th(E) Cycle time, write Cycle time, sector-erase operation Cycle time, chip-erase operation Hold time, address Hold time, data valid after high Hold time, Hold time, read Hold time, toggle, data tw(WL) tw(WH) Pulse duration, Pulse duration, high Pulse duration, (see Note Pulse duration, (see Note trec(R) tsu(A) tsu(D) tsu(E) Recovery time, read before write Setup time, address Setup time, data Setup time, Setup time, Setup time, (see Note Setup time, (see Notes Transition time, (see Notes tc(W)PR Programming operation NOTES: Sector-protect timing Sector unprotect timing ALTERNATE SYMBOL tAVAV tWHWH2 tWHWH3 tWLAX tWHDX tEHWH tWHGL1 tWHGL2 tWLWH1 tWHWL tWLWH2 tWLWH3 tGHWL tAVWL tDVWH tELWL tVCEL tEHVWL tGHVWL tHVT tWHWH1 '29F002-70 '29F002-80 UNIT
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switching characteristics over recommended ranges supply voltage operating free-air temperature, controlled
PARAMETER tc(W) Cycle time, write Cycle time, sector-erase operation Cycle time, chip-erase operation th(A) th(D) th(W) th(C) tw(EL) tw(EH) trec(R) tsu(A) tsu(D) tsu(W) Hold time, address Hold time, data Hold time, Hold time, read Hold time, toggle, data Pulse duration, Pulse duration, high Recovery time, read before write Setup time, address Setup time, data Setup time, Setup time, Programming operation ALTERNATE SYMBOL tAVAV tEHEH2 tEHEH3 tELAX tEHDX tEHWH tEHGL1 tEHGL2 tELEH1 tEHEL tGHEL tAVEL tDVEH tWLEL tGLEL tEHEH1 '29F002-70 '29F002-80 UNIT
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erase program performance
PARAMETER Sector erase time Program time Chip programming time Erase/program cycles TEST CONDITIONS Excludes programming prior erasure Excludes system-level overhead Excludes system-level overhead UNIT cycles
internal algorithms allow byte program time. only after byte takes theoretical maximum time program. minimal number bytes require signficantly more programming pulses than typical byte. majority bytes program within pulses. This demonstrated typical maximum programming time listed above. 25°C, cycles, typical pattern Under worst case conditions, 90°C, cycles
latchup characteristics (see Note
PARAMETER Input voltage with respect pins except pins (including Input voltage with respect pins UNIT
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Current NOTE Includes pins except test conditions: time
capacitance, packages (see Note
PARAMETER COUT CIN2 Input capacitance Output capacitance Control capacitance TEST CONDITIONS VOUT UNIT
NOTE Test conditions 25°C,
data retention
PARAMETER Minimum pattern data retention time TEST CONDITIONS 150°C 125°C UNIT Years
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read operation
tAVAV Addresses Valid Addresses
tAVQV tEHQZ tELQV tGHQZ tGLQV
tGLQX tAXQX tELQX
Valid Data
Figure Waveform Read Operation
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write operation
Start
Write Cycle 555H
Write Cycle 2AAH
Write Cycle 555H
Write Cycle Program Address Program Data
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Poll Device Status
Operation Complete
Next Address
Last Address
Figure Program Algorithm Flow Chart
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write operation (continued)
tAVAV Addresses 555H tWLAX tAVWL tELWL tWHEH tGHWL tWLWH1 tWHWH1 tDVWH DOUT tWHDX tWHWL 2AAH 555H
NOTES: Address programmed Data programmed Complement data written
Figure Waveform Program Operation
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write operation (continued)
tAVAV Addresses 555H tAVEL tELEH tGHEL tDVEH tWLEL tEHDX DOUT tEHWH tWHWH1 tEHEL tELAX 2AAH 555H
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NOTES: Address programmed Data programmed Complement data written
Figure Waveform Alternate CE-Controlled Write Operation
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chip-erase operation
Start
Write Cycle 555H
Write Cycle 2AAH
Write Cycle 555H
Write Cycle 555H
Write Cycle 2AAH
Write Cycle 555H
Poll Device Status
Operation Complete
Figure Chip-Erase Algorithm Flow Chart
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chip-erase operation (continued)
tAVAV Addresses 555H 555H 2AAH tWLAX tAVWL tELWL tWHEH tWHDX tGHWL tWHWL tWLWH1 tWHWH3 tDVWH DQ7=0 DOUT=FFH 555H
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NOTES: valid address Figure details last four cycles six-bus-cycle operation
Figure Waveform Chip-Erase Operation
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sector-erase operation
Start
Write Cycle 555H
Write Cycle 2AAH
Write Cycle 555H
Write Cycle 555H/AAH
Write Cycle 2AAH
Write Cycle Sector Address
Load Additional Sectors Poll Device Status
Operation Complete
Figure Sector-Erase Algorithm
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
sector-erase operation (continued)
tAVAV Addresses 555H tWLAX tAVWL tELWL tWHEH tGHWL tWLWH1 tWHWH2 tDVWH DQ7=0 DOUT=FFH tWHDX tWHWL 555H 2AAH
PRODUCT PREVIEW
NOTES: Sector address erased Figure details last four cycles six-bus-cycle operation.
Figure Waveform Sector-Erase Operation
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
data-polling operation
Start
Read Addr
Data
Read Addr
Data
Fail Pass
NOTES: Polling status bits change asynchronously. Read after changes states. Program address byte programming Selected sector address sector erase valid address chip erase
Figure Data-Polling Algorithm
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PRODUCT PREVIEW
TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
data-polling operation (continued)
Addresses tAVQV tELQV tGLQV tWHGL1 tGHQX tWHWH1, tGHQZ tAXQX tAVQV tELQV
tGLQV
PRODUCT PREVIEW
NOTES:
DOUT
DOUT
Last command data written device Complement data written Valid data output Valid address byte-program, sector-erase, chip-erase operation
Figure Waveform Data-Polling Operation
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
toggle-bit operation
Start
Read Addr
Read Addr
Toggle
Read
Toggle
Fail Pass
NOTE Polling status bits change asynchronously. Read after changes states.
Figure Toggle-Bit Algorithm
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PRODUCT PREVIEW
TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
toggle-bit operation (continued)
Addresses
tELQV
tAVQV tELQV
tGLQV tGLQV
tWHGL2 tWHWH1,
PRODUCT PREVIEW
TOGGLE TOGGLE TOGGLE STOP TOGGLE
DOUT
NOTES:
DOUT
Last command data written device Toggle output Valid data output Valid address byte-program, sector-erase, chip-erase operation
Figure Waveform Toggle-Bit Operation
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
sector-protect operation
Start
Select Sector Address
VIL,
Apply Pulse VIL, VIH,
Read Data
Data
Sector Protect Failed
Protect Additional Sectors Write Reset Command
Figure Sector-Protect Algorithm
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
sector-protect operation (continued)
tHVT tAVQV Sector Address
tGHVWL tHVT tGLQV NOTE DOUT selected sector protected, sector protected DOUT tWLWH2 tHVT
PRODUCT PREVIEW
Figure Waveform Sector-Protect Operation
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
sector-unprotect operation
Start
Protect Sectors
VIL,
Apply Pulse VIL, VIH,
Select Sector Address
Read Data
1000
Data
Next Sector Address
Sector Unprotect Failed
Last Sector Write Reset Command
Figure Sector-Unprotect Algorithm
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PRODUCT PREVIEW
TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
sector-unprotect operation (continued)
tHVT tAVQV Sector Address
PRODUCT PREVIEW
tHVT tWLWH3 tGLQV NOTE DOUT selected sector protected, sector protected DOUT tGHVWL tHVT
Figure Waveform Sector-Unprotect Operation
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TMS29F002T, TMS29F002B 262144 8-BIT FLASH MEMORIES
MECHANICAL DATA
(R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER
Seating Plane 0.004 (0,10) 0.140 (3,56) 0.132 (3,35) 0.495 (12,57) 0.485 (12,32) 0.453 (11,51) 0.447 (11,35) 0.129 (3,28) 0.123 (3,12) 0.049 (1,24) 0.043 (1,09) 0.008 (0,20)
0.020 (0,51) 0.015 (0,38) 0.595 (15,11) 0.585 (14,86) 0.553 (14,05) 0.547 (13,89) 0.030 (0,76)
0.050 (1,27)
4040201-4 03/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-016
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PRODUCT PREVIEW
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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