Single Power Supply Organization Bits Eight Equal Sectors Bytes Combin
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TMS29F010 131072 8-BIT FLASH MEMORY
Single Power Supply Organization Bits Eight Equal Sectors Bytes Combination Sectors Erased Combination Sectors Marked Read-Only Compatible With JEDEC EEPROM Command Fully Automated On-Chip Erase Byte-Program Operations Program Erase Cycles Compatible With JEDEC Byte-Wide Pinouts Low-Current Consumption Active Read Typical Active Program Erase Typical Inputs/Outputs TTL-Compatible
PACKAGE VIEW
NOMENCLATURE A[0:16] DQ[0:7] Address Inputs Inputs (programming) Outputs Chip Enable Output Enable Power Supply Ground Write Enable Connection
description
TMS29F010 8-bit (1048 576-bit), single-supply, programmable read-only memory device that electrically erased reprogrammed. This device organized eight independent 16K-byte sectors offered with access times between
on-chip state machine controls program erase operations. embedded byte-program sector chip-erase functions fully automatic. command compatible with that JEDEC 1M-bit EEPROMs. Data-protection sector combination accomplished using hardware sector-protection feature. Device operations selected writing JEDEC-standard commands into command register using standard microprocessor write timings. command register acts input internal-state machine that interprets commands, controls erase programming operations, outputs status device, outputs data stored device, outputs device algorithm-selection code. initial power-up operation, device defaults read mode. TMS29F010 offered 32-pin plastic leaded chip carrier suffix) using 1.27-mm (50-mil) lead pitch.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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device symbol nomenclature
TMS29F010
Temperature Range Designator Commercial (0°C 70°C) Extended 40°C 85°C) Automotive 40°C 125°C) Package Designator Plastic Leaded Chip Carrier Program Erase Endurance Cycles Speed Designator
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block diagram
Detector
Timer Input/Output Buffers
Command Register Erase-Voltage Generator Program-Voltage Generator Data Latch
State Control
Chip-Enable Output-Enable Logic
Column Decoder
Column-Gating 8-Bit Array 8-Bit Array 8-Bit Array 8-Bit Array
Row-Decoder
8-Bit Array 8-Bit Array 8-Bit Array 8-Bit Array
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memory sector architecture
1FFFFh 16K-Byte Sector 1C000h 1BFFFh 16K-Byte Sector 18000h 17FFFh 16K-Byte Sector 14000h 13FFFh 16K-Byte Sector 10000h 0FFFFh 16K-Byte Sector 0C000h 0BFFFh 16K-Byte Sector 08000h 07FFFh 16K-Byte Sector 04000h 03FFFh 16K-Byte Sector 00000h
Sector Sector Sector Sector Sector Sector Sector Sector
Address 00000h 04000h 08000h 0C000h 10000h 14000h 18000h 1C000h
Range 03FFFh 07FFFh 0BFFFh 0FFFFh 13FFFh 17FFFh 1BFFFh 1FFFFh
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operation
Table summarizes operation modes. Table Operation Modes
FUNCTIONS MODE Read Output disable Standby write inhibit Algorithm-selection mode Write Sector-protect (see Note Sector-unprotect Erase operations Note Note Note Note Data Hi-Z Hi-Z Manufacturer-equivalent code Device-equivalent code Note Data Data Data Note
VIH. Table valid address data during write (byte program). Operation 25°C. NOTES: Address pins VIH. Figure through Figure
read mode read output TMS29F010, low-level logic signal applied pins. When more TMS29F010 devices connected parallel, output device read without interference. power control used device selection. output control used gate data output onto from selected device. address-access time (tAVQV) delay from stable address valid output data. chip-enable access time (tELQV) delay from stable addresses valid output data. output-enable access time (tGLQV) delay from valid output data when addresses stable least duration tAVQV tGLQV. standby mode supply current reduced applying logic-high level enter standby mode. standby mode, outputs placed high-impedance state. Applying CMOS logic-high level reduces current maximum. Applying logic-high level reduces current maximum. TMS29F010 deselected during erasure programming, device continues draw active current until operation complete. output disable When either VIH, output from device disabled output pins (DQ0 DQ7) placed high-impedance state.
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algorithm-selection mode algorithm-selection mode provides access binary code that matches device with proper programming- erase-command operations. This mode activated when (11.5 12.5 placed address Address must logic-low. bytes code accessed toggling address from VIH. other address pins logic-low logic-high. algorithm-selection code also read using command register. This useful when available placed address Table shows binary algorithm-selection codes TMS29F010. Table Algorithm-Selection Codes
ALGORITHM SELECTION Byte Byte VIL,
erasure programming Erasure programming TMS29F010 accomplished writing sequence commands using standard microprocessor-write timings. commands written command register input command-state machine (CSM). interprets command entered initiates program erase operations instructed. acts interface between write-state machine (WSM) external chip operations. controls voltage generation, pulse generation, preconditioning, verification memory contents. Program sector/chip-erase functions fully automatic. Once program erase operation reached, device internally resets read mode. drops below low-voltage-detect level (VLKO), operation progress aborted device resets read mode. byte-program chip-erase operation progress, additional program/erase commands ignored until operation ends. command definitions Device operating modes selected writing specific address data sequences into command register. Table defines valid command sequences. Writing incorrect address data values writing them incorrect sequence causes device reset read mode. command register does occupy addressable memory location. register stores command sequence, along with address data needed memory array. Commands written setting VIH, bringing from VIL. Addresses latched falling edge data latched rising edge Holding toggling alternative method. byte-program chip/sector-erase sections more complete description.
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command definitions (continued) Table Command Definitions
COMMAND Read Algorithm selection Byte program Chip erase Sector erase CYCLES CYCLE ADDR DATA 5555h 5555h 5555h 5555h 5555h 2AAAh 2AAAh 5555h 2AAAh 2AAAh 2AAAh 2AAAh 2AAAh CYCLE ADDR DATA CYCLE ADDR DATA CYCLE ADDR DATA CYCLE ADDR DATA CYCLE ADDR DATA
XXXXh 5555h 5555h 5555h 5555h 5555h
5555h 5555h
Address location read Address location programmed Address sector erased Addresses A14, A15, select eight sectors Data read selected address location Data programmed selected address location Address pins bus-cycle addresses except program address (PA), sector address (SA), read address (RA). command cycles required when device read mode. reset command required return read mode when device algorithm-selection mode goes high.
reset/read command
read mode activated writing either reset command sequences into command register. device remains this mode until another valid command sequence input into command register. Memory data available read mode read with standard microprocessor read-cycle timing. power device defaults read mode; therefore, reset command sequence required memory data available.
algorithm-selection command
algorithm-selection command allows access binary code that matches device with proper programming- erase-command operations. After writing three-bus-cycle command sequence, first byte algorithm-selection code (01h) read from address XX00h. second byte code (20h) read from address XX01h (see Table This mode remains effect until another valid command sequence written device. Sector protection determined using algorithm-selection command. After issuing three bus-cycle command sequence, sector-protection status read DQ0. address pins VIH, then sector address pins A14, A15, select sector checked. remaining address pins VIH. sector that selected protected, outputs state, and, sector selected protected, outputs state. This mode remains effect until another valid command sequence written device.
byte-program command
Byte programming four-bus-cycle command sequence. first three cycles device into program-setup state, fourth cycle loads address location data programmed into device. addresses latched falling edge data latched rising edge fourth cycle. rising edge starts byte-program operation. embedded byte-programming function automatically provides needed voltage timing program verify cell margin. further commands written device during program operation ignored.
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byte-program command (continued)
Programming performed address location order, resulting logic being programmed into device. Attempting program logic into that been previously programmed logic causes internal pulse counter exceed pulse-count limit. This sets exceed-timing-limit indicator (DQ5) logic-high state. Only erase operation change bits from logic logic When erased, bits become logic Figure shows flow chart typical byte-programming operation. status device during automatic programming operation monitored completion using data-polling feature toggle-bit feature. operation-status section full description.
chip-erase command
Chip erase six-bus-cycle command sequence. first three cycles device into erase-setup state, next cycles unlock erase mode. sixth cycle loads chip-erase command. This command sequence required ensure that memory contents erased accidentally. rising edge starts chip-erase operation. further commands written device during chip-erase operation ignored. embedded chip-erase function automatically provides voltage timing needed program verify memory cells prior electrical erase then erases verifies cell margin automatically. user required program memory cells prior erase. status device during automatic chip-erase operation monitored completion using data-polling feature toggle-bit feature. operation status section full description. Figure shows flow chart typical chip-erase operation.
sector-erase command
Sector erase six-bus-cycle command sequence. first three cycles cause device into erase-setup state, next cycles unlock erase mode. sixth cycle loads sector-erase command sector-address location erased. address location within desired sector used. addresses latched falling edge sector-erase command (30h) latched rising edge sixth cycle. After delay from rising edge sector-erase operation begins selected sector(s). Additional sectors selected erased concurrently during sector-erase command sequence. each additional sector selected erase, another cycle issued. cycle loads next sector-address location sector-erase command. time between previous cycle start next cycle must less than µs-otherwise, sector location loaded. time delay from rising edge last cycle starts sector-erase operation. there falling edge within 80-µs time delay, timer reset. eight sector-address locations loaded order. state delay timer monitored using sector-erase-delay indicator (DQ3). logic low, time delay expired. operation-status section full description. command other than sector-erase (30h) written device during sector-erase operation causes device exit sector-erase mode; meanwhile, contents sector(s) selected erase longer valid. complete sector-erase operation, sector-erase command sequence must repeated. embedded sector-erase function automatically provides needed voltage timing program verify memory cells prior electrical erase then erases verifies cell margin automatically. Programming memory cells prior erase required. status device during automatic sector-erase operation monitored completion using data-polling feature toggle-bit feature. operation-status section full description. Figure shows flow chart typical sector-erase operation.
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operation status
status definitions During operation embedded program erase functions, status device determined reading data state designated outputs. data-polling (DQ7) toggle-bit (DQ6) require multiple successive reads observe change state designated output. Table defines values status flags. Table Operation Status Flags
Device Operation Byte-programming progress Byte-programming exceed time limit Byte-programming complete Sector chip-erase progress Sector chip-erase exceed time limit
Sector chip-erase complete toggle, data, data undefined, complement data written DQ4, DQ2, DQ1, reserved future use.
data-polling (DQ7)
data-polling status function outputs complement data latched into data register while write-state machine (WSM) engaged program erase operation. Data changes from complement true indicate operation. Data polling available only during byte-programming, chip-erase, sector-erase, sector-erase timing delay. Data polling valid after rising edge last cycle command sequence loaded into command register. Figure shows flow chart data-polling operation. During byte-program operation, reading outputs complement data programmed selected address location. Upon completion, reading outputs true data loaded into program data register. During erase operations, reading outputs logic upon completion, reading outputs logic Also, data polling must performed sector address that within sector being erased; otherwise, status valid. When using data polling, address must remain stable throughout operation. During data-polling read, while low, change asynchronously with other DQs. Depending read timing, system read valid data DQ7, while other pins still invalid. data DQ0-DQ7 valid with subsequent read device. Figure data-polling timing diagram.
toggle-bit (DQ6)
toggle-bit status function outputs data that toggles between logic logic while engaged program erase operation. When toggle-bit stops toggling after consecutive reads same address, operation complete. toggle available only during byte-programming, chip-erase, sector-erase, sector-erase timing delay. Toggle data valid after rising edge last cycle command sequence loaded into command register. Figure shows flow chart toggle-bit status-read algorithm. Depending read timing, stop toggling while other pins still invalid. data DQ0-DQ7 valid with subsequent read device. Figure shows toggle-bit timing diagram.
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exceed-time-limit (DQ5)
program erase operations internal pulse counter limit number pulses applied. pulse count limit exceeded, logic indicating that program erase operation failed. will change from complemented data true data will stop toggling when read. continue operation, device must reset. exceed-time-limit condition occurs when attempting program logic into that been programmed previously logic Only erase operation change bits from logic logic After reset, device functional erased reprogrammed.
sector-load-timer (DQ3)
sector-load-timer status bit, DQ3, used determine time load additional sector addresses expired. After completion sector-erase command sequence, remains logic This indicates that another sector-erase command sequence issued. logic indicates that delay expired attempts issue additional sector-erase commands ignored. sector-erase command section description. data-polling toggle valid during 80-µs time delay used determine valid sector-erase command been issued. ensure additional sector-erase commands have been accepted, status should read before after each additional sector-erase command. logic both reads, then additional sector-erase command accepted.
data protection
hardware-sector protect feature This feature disables both programming erase operations combination eight sectors. Commands program erase protected sector change data contained sector. data-polling toggle bits operate then return valid data. This feature enabled using high-voltage (11.5 12.5 address control control Figure shows flow chart sector-protect operation. device delivered with sectors unprotected; however, sector-unprotect mode available unprotect protected sectors. Figure flow chart sector-unprotect operation. sector-protect operation sector-protect mode activated when (and operation 25°C), VIH, VIL, address control forced VID. sector-select address pins A14, A15, used select sector protected. Address pins A0-A8, A10-A13, pins must stable VIH. Once addresses stable, pulsed operation begins falling edge terminates rising edge Figure shows timing diagram sector-protect operation. sector-protect verify Verification sector protection activated when (and operation 25°C), VIH, VIL, VIL, address VID. Address pins VIL, VIH. sector-address pins A14, A15, select sector verified. other address pins VIH. sector selected protected, output 01h, sector selected protected, output 00h.
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sector unprotect operation Prior sector-unprotect operation, sectors should protected using sector-protect mode. Sector unprotect activated when (and operation 25°C), VIH, address control pins forced VID. Address VIL, pins VIH. sector-select address pins A14, A15, VIH. eight sectors unprotected parallel, once inputs stable, pulsed unprotect operation begins falling edge terminates rising edge Figure shows timing diagram sector-unprotect operation. sector-unprotect verify Verification sector-unprotect accomplished when (and operation 25°C), VIH, VIL, VIL, address VID, then select sector verified. Address pins while VIL. other address pins VIL. sector that selected protected, output sector protected, output 00h. write lockout During power power down, write operations locked less than VLKO. VLKO, command input disabled device reset read mode. power VIL, VIL, VIH, device does accept commands rising edge device automatically powers read mode.
glitching
Pulses less than (typical) issue write cycle.
power supply considerations
Each device should have 0.1-µF ceramic capacitor connected between suppress circuit noise. Printed circuit traces should appropriate handle current demand minimize inductance.
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absolute maximum ratings over operating ambient temperature range (unless otherwise noted)
Voltage range with respect ground: Supply voltage range, (see Note -2.0 pins except (see Note -2.0 (see Note -2.0 14.0 Ambient temperature range during read erase program, Commercial 70°C Extended -40°C 85°C Automotive -40°C 125°C Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: Minimum voltage input pins -0.5 During voltage transitions, input pins undershoot -2.0 periods Maximum voltage input pins During voltage transitions, input pins overshoot periods Minimum input voltage pins -0.5 During voltage transitions, undershoot -2.0 periods Maximum input voltage pins +12.5 which overshoot +14.0 periods
recommended operating conditions
Supply voltage Commercial Ambient temperature during read erase program Extended Automotive UNIT
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electrical characteristics over recommended ranges supply voltage ambient temperature
PARAMETER VLKO High-level High level input voltage Low-level level input voltage CMOS CMOS TEST CONDITIONS 0.7*VCC -0.5 -0.5 11.5 VIL, VIL, TTL-input level =VSS 12.5 0.85*VCC 0.45 0.45 12.5 UNIT
Algorithm-selection sector-protect/unprotect input voltage lock-out voltage (see Note High-level output voltage CMOS CMOS CMOS
ICC1 ICC2 ICC3
Low-level output voltage (see Note Input current (leakage) Output current (leakage) High-voltage load current active current (see Note active current (see Note supply current (standby)
CMOS input level recommended operating conditions table NOTES: Typical value nominal condition 25°C) 12-mA also available current read mode, switching MHz, IOUT current while erase program operation progress
capacitance over recommended ranges supply voltage ambient temperature
PARAMETER Input capacitance (All inputs except Input capacitance (A9, Output capacitance TEST CONDITIONS UNIT
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switching characteristics over recommended ranges supply voltage ambient temperature, read-only operation (see Figure Figure Figure Figure Figure
PARAMETER tAVQV tELQV tGLQV tAVAV tEHQZ tGHQZ tAXQX tWHGL1 tWHGL2 Access time, address Access time, Access time, Cycle time, read Disable time, high impedance Disable time, high impedance Hold time, output from address, change Hold time, read Hold time, toggle data polling ALTERNATE SYMBOL ta(A) ta(E) ta(G) tc(R) tdis(E) tdis(G) th(D) '29F010-70 '29F010-90 '29F010-10 '29F010-12 UNIT
Figure test output load circuit voltage waveforms.
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timing requirements controlled (see Figure Figure Figure Figure Figure Figure Figure
ALTERNATE SYMBOL tAVAV tWHWH1 tWHWH2 tWHWH3 tWLAX tWHDX tWHEH tWHWL tWLWH1 tWLWH2 tWLWH3 tGHWL tAVWL tDVWH tAVGH tAVGEH tELWL tGHWH tVCEL tEHVWL tGHVWL tWHAH Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation Cycle time, chip-erase operation Hold time, address Hold time, data valid after high Hold time, Pulse duration, high Pulse duration, Pulse duration, (see Note Pulse duration, (see Note Recovery time, read-before-write Setup time, address Setup time, data Setup time, high high (see Note Setup time, high high (see Note Setup time, Setup time, Setup time, Setup time, (see Note Setup time, (see Notes Setup time, high going high (see Note tsu(E) trec(R) tsu(A) tsu(D) th(A) th(D) th(E) tw(WH) tw(WL) tc(W) tc(W)PR '29F010-70 '29F010-90 UNIT
tHVT Transition time, (see Notes NOTES: Sector-protect timing (see Figure Sector-unprotect timing (see Figure
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timing requirements controlled (see Figure Figure Figure Figure Figure Figure Figure (continued)
ALTERNATE SYMBOL tAVAV tWHWH1 tWHWH2 tWHWH3 tWLAX tWHDX tWHEH tWHWL tWLWH1 tWLWH2 tWLWH3 tGHWL tAVWL tDVWH tAVGH tAVGEH tELWL tGHWH tVCEL tEHVWL tGHVWL tWHAH Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation Cycle time, chip-erase operation Hold time, address Hold time, data valid after high Hold time, Pulse duration, high Pulse duration, Pulse duration, (see Note Pulse duration, (see Note Recovery time, read-before-write Setup time, address Setup time, data Setup time, high high (see Note Setup time, high high (see Note Setup time, Setup time, Setup time, Setup time, (see Note Setup time, (see Notes Setup time, high going high (see Note tsu(E) trec(R) tsu(A) tsu(D) th(A) th(D) th(E) tw(WH) tw(WL) tc(W) tc(W)PR '29F010-10 '29F010-12 UNIT
tHVT Transition time, (see Notes NOTES: Sector-protect timing (see Figure Sector-unprotect timing (see Figure
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timing requirements controlled (see Figure
ALTERNATE SYMBOL tAVAV tEHEH1 tEHEH2 tEHEH3 tELAX tEHDX tEHWH tELEH tEHEL tGHEL tAVEL tDVEH Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation (see Note Cycle time, chip-erase operation (see Note Hold time, address Hold time, data Hold time, Pulse duration, Pulse duration, high Recovery time, read-before-write Setup time, address Setup time, data th(A) th(D) th(W) tw(EL) tw(EH) trec(R) tsu(A) tsu(D) tc(W) '29F010-70 '29F010-90 UNIT
tWLEL Setup time, tsu(W) NOTES: Timing diagram E-controlled sector-erase operation enclosed. Timing diagram E-controlled chip-erase operation enclosed.
ALTERNATE SYMBOL tAVAV tEHEH1 tEHEH2 tEHEH3 tELAX tEHDX tEHWH tELEH tEHEL tGHEL tAVEL tDVEH Cycle time, write Cycle time, programming operation Cycle time, sector-erase operation (see Note Cycle time, chip-erase operation (see Note Hold time, address Hold time, data Hold time, Pulse duration, Pulse duration, high Recovery time, read-before-write Setup time, address Setup time, data th(A) th(D) th(W) tw(EL) tw(EH) trec(R) tsu(A) tsu(D) tsu(W) tc(W)
'29F010-10
'29F010-12
UNIT
tWLEL Setup time, NOTES: Timing diagram E-controlled sector-erase operation enclosed. Timing diagram E-controlled chip-erase operation enclosed.
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PARAMETER MEASUREMENT INFORMATION
1.50
Output Under Test (see Note Note Note
0.45 Conditions:
VOLTAGE WAVEFORMS Conditions:
VOLTAGE WAVEFORMS -90, -10, 0.45
Measurements taken logic high logic Input rise fall
Measurements taken logic high logic Input rise fall
NOTES: includes probe fixture capacitance. testing inputs voltage waveforms driven logic high logic low. Timing measurements voltage waveforms made logic high logic both inputs outputs. testing inputs -90, -10, voltage waveforms driven logic high 0.45 logic low. Timing measurements -90, -10, voltage waveforms made logic high logic both inputs outputs. Each device should have 0.1-µF ceramic capacitor connected between VSS, closely possible device pins.
Figure Test Output Load Circuit Voltage Waveforms
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read operation
tAVAV Addresses Valid Addresses
tAVQV tEHQZ tELQV tGHQZ tGLQV
tAXQX tWHGL1 Valid Data
Figure Waveform Read Operation
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write operation
Start
Write Cycle 5555H Write Cycle 2AAAH Write Cycle 5555H Write Cycle Program Address Program Data
Poll Device Status
Operation Complete
Next Address
Last Address
Figure Byte-Program Algorithm
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write operation (continued)
tAVAV Addresses 5555H tWLAX tAVWL tELWL tWHEH tGHWL tWLWH1 tWHWH1 tDVWH DOUT tWHDX tWHWL 2AAAH 5555H
NOTES: Address location programmed Data programmed Complement data written
Figure Waveform Byte-Program (W-Controlled) Operation
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write operation (continued)
tAVAV Addresses 5555H tAVEL tELEH tELAX 2AAAH 5555H
tGHEL
tEHEL tDVEH tWLEL tEHEH1 tEHWH
tEHDX DOUT
NOTES: Address location programmed Data programmed Complement data written
Figure Waveform Byte-Program (Alternate E-Controlled) Operation
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chip-erase operation
Start
Write Cycle 5555H
Write Cycle 2AAAH
Write Cycle 5555H
Write Cycle 5555H
Write Cycle 2AAAH
Write Cycle 5555H
Poll Device Status
Operation Complete
Figure Chip-Erase Algorithm
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chip-erase operation (continued)
tAVAV Addresses 5555H tAVWL tWLAX tELWL tWHEH tGHWL tWHWL tWLWH1 tDVWH tWHDX tVCEL NOTE valid address DQ7=0 DOUT=FFH 2AAAH 5555H 5555H 2AAAH 5555H
tWHWH3
Figure Waveform Chip-Erase Operation
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sector-erase operation
Start
Write Cycle 5555H
Write Cycle 2AAAH
Write Cycle 5555H
Write Cycle 5555H
Write Cycle 2AAAH Write Cycle Sector Address
Load Additional Sectors Poll Device Status
Operation Complete
Figure Sector-Erase Algorithm
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sector-erase operation (continued)
tAVAV Addresses 5555H tAVWL tWLAX tELWL tWHEH tGHWL tWHWL tWLWH1 tDVWH tWHDX tVCEL DQ7=0 DOUT=FFH 2AAAH 5555H 5555H 2AAAH
tWHWH2
NOTE Sector address erased
Figure Waveform Sector-Erase Operation
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data-polling operation
Start
Read Addr
Data
Read Addr
Data Fail
Pass
NOTES: checked again after checked, even Program address byte-programming Selected sector address sector-erase valid address chip-erase
Figure Data-Polling Algorithm
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data-polling operation (continued)
Addresses tAVQV tELQV tGLQV tGHQZ tWHGL2 tWHWH1, NOTES: DOUT tAXQX tAVQV tELQV
tGLQV
Last command data written device Complement data written DOUT Valid data output Valid address byte-program, sector-erase, chip-erase operation data-polling operation valid both E-controlled byte-program, sector-erase, chip-erase operations.
Figure Waveform Data-Polling Operation
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toggle-bit operation
Start
Read Addr
Read Addr
Toggle
Read
Toggle Fail
Pass
NOTE checked again after checked, even
Figure Toggle-Bit Algorithm
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toggle-bit operation (continued)
Addresses
tELQV
tAVQV tELQV
tGLQV tGLQV tGHWH tWHGL2 tWHWH1,
Toggle
Toggle
Toggle
Stop Toggle
DOUT
NOTES:
Last command data written device Toggle output DOUT Valid data output Valid address byte-program, sector-erase, chip-erase operation toggle-bit operation valid both E-controlled byte-program, sector-erase, chip-erase operations.
Figure Waveform Toggle-Bit Operation
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sector-protect operation
Start
Select Sector Address A16, A15,
Apply 100-µs Pulse
Read Data
Data
Sector Protect Failed
Protect Additional Sectors Write Reset Command
Figure Sector-Protect Algorithm
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sector-protect operation (continued)
tHVT Sector Address
tAVGH tHVT tGLQV NOTE DOUT selected sector protected, sector protected DOUT tGHVWL tWLWH2 tHVT
Figure Waveform Sector-Protect Operation
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sector-unprotect operation
Start
Protect Sectors
VIL, Apply 10-ms Pulse
Select Sector Address A16, A15,
Read Data
1000
Data
Next Sector Address
Sector unprotect Failed
Last Sector Write Reset Command
Figure Sector-Unprotect Algorithm
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TMS29F010 131072 8-BIT FLASH MEMORY
sector-unprotect operation (continued)
Sector Address
tAVQV tHVT tWHAH
tAVGEH tHVT tHVT tWLWH3 tHVT tGHVWL tGLQV DOUT tEHVWL
NOTE DOUT selected sector protected, sector protected
Figure Waveform Sector-Unprotect Operation
POST OFFICE 1443
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TMS29F010 131072 8-BIT FLASH MEMORY
MECHANICAL DATA
(R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER
Seating Plane 0.004 (0,10) 0.140 (3,56) 0.132 (3,35) 0.495 (12,57) 0.485 (12,32) 0.453 (11,51) 0.447 (11,35) 0.129 (3,28) 0.123 (3,12) 0.049 (1,24) 0.043 (1,09) 0.008 (0,20)
0.020 (0,51) 0.015 (0,38) 0.595 (15,11) 0.585 (14,86) 0.553 (14,05) 0.547 (13,89) 0.030 (0,76)
0.050 (1,27)
4040201-4 03/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-016
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