Single Power Supply Supports Read/Write Operation Organization 048576

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Single Power Supply Supports Read/Write Operation Organization 048576

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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
Single Power Supply Supports Read/Write Operation Organization 048576 Bits Bits Array-Blocking Architecture 16K-Byte/One 8K-Word Boot Sector 8K-Byte/4K-Word Parameter Sectors 32K-Byte/16K-Word Sector Fifteen 64K-Byte/32K-Word Sectors Combination Sectors Erased. Supports Full-Chip Erase Combination Sectors Marked Read-Only Boot-Code Sector Architecture Sector Bottom Sector Sector Protection Hardware Protection Method That Disables Combination Sectors From Write Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms Automatically Pre-Programs Erases Sector Automatically Programs Verifies Program Data Specified Address JEDEC Standards Compatible With JEDEC Byte Pinouts Compatible With JEDEC EEPROM Command Fully Automated On-Chip Erase Program Operations Program/Erase Cycles Power Dissipation 40-mA Typical Active Read Byte Mode 50-mA Typical Active Read Word Mode 60-mA Typical Program/Erase Current Less Than 100-µA Standby Current Deep Power-Down Mode Inputs/Outputs TTL-Compatible
NOMENCLATURE A[0:18] BYTE DQ[0:14] DQ15/A-1 RESET Address Inputs Byte/Word Enable Data Data Data In/Out (Word-Wide Mode) Low-Order Address (Byte-Wide Mode) Chip Enable Output Enable Internal Connection Reset Deep Power Down Ready Busy Output Power Supply Ground Write Enable
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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Erase Suspend/Resume Supports Reading Data From, Programming Data Sector Being Erased Hardware-Reset Initializes Internal-State Machine Read Operation Package Options 44-Pin Plastic Small-Outline Package (PSOP) (DBJ Suffix) 48-Pin Thin Small-Outline Package (TSOP) (DCD Suffix) Detection Program/Erase Operation Data Polling Toggle Feature Program/Erase Cycle Completion Hardware Method Detection Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output High-Speed Data Access Three Temperature Ranges Commercial 70°C Commercial 70°C Extended -40°C 85°C Automotive -40°C 125°C
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
44-PIN PSOP PACKAGE (TOP VIEW)
PRODUCT PREVIEW
RY/BY DQ10 DQ11
RESET BYTE DQ15/A-1 DQ14 DQ13 DQ12
description
TMS29F800T/B 8-bit 16-bit 608-bit), single-supply, programmable read-only memory device that electrically erased reprogrammed. This device organized bits bits, divided into sectors: 16K-byte/8K-word boot sector 8K-byte/4K-word sectors 32K-byte/16K-word sector Fifteen 64K-byte/32K-word sectors
combination sectors marked read-only erased. Full-chip erasure also supported. Sector data protection afforded methods that disable combination sectors from write read operations using standard programming equipment. on-chip state machine provides on-board algorithm that automatically pre-programs erases sector before automatically programs verifies program data specified address. command compatible with that Joint Electronic Device Engineering Council (JEDEC) standards compatible with JEDEC 8M-bit electrically erasable, programmable read-only memory (EEPROM) command set. suspend/resume feature allows access unaltered memory blocks during section-erase operation. outputs this device TTL-compatible. Additionally, erase/suspend/resume feature supports reading data from, programming data sector that being erased.
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
48-PIN TSOP PACKAGE (TOP VIEW)
description (continued)
Device operations selected writing JEDEC-standard commands into command register using standard microprocessor write timings. command register acts input internal-state machine which interprets commands, controls erase programming operations, outputs status device, outputs data stored device, outputs device algorithm-selection code. initial power device defaults read mode. hardware-reset initializes internal-state machine read operation. device power dissipation with 40-mA active read byte mode, 50-mA active read word mode, 60-mA typical program/erase current mode, less than 100-mA standby current with 5-mA deep-power-down mode. These devices offered with 80-, 90-, 100-, 120-ns access times. Table Table show sector-address ranges. TMS29F800T/B offered 44-pin plastic small-outline package (PSOP) (DBJ suffix) 48-pin thin small-outline package (TSOP) (DCD suffix).
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RESET
BYTE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
device symbol nomenclature
TMS29F800
Temperature Range Commercial (0°C 70°C) Extended 40°C 85°C) Automotive 40°C 125°C) Package Designator 48-Pin Plastic Dual Small-Outline Package 44-Pin Plastic Small-Outline Package Program/Erase Endurance Cycles Cycles Speed Option
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Boot Code Selection Architecture Sector Bottom Sector Device Number Description Bits
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
logic symbol 44-pin package
RESET BYTE FLASH MEMORY 524288
[PWR DWN] (READ) (WRITE)
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. numbers shown package.
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
logic symbol 48-pin package
FLASH MEMORY 524288
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RESET BYTE
[PWR DWN] (READ) (WRITE)
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. numbers shown package.
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
block diagram
DQ15 Buffer Erase Voltage Generator Input/Output Buffers
BYTE RESET
State Control
Command Registers
Voltage Generator
Data Latch
Chip-Enable Output-Enable Logic
Detector
Timer
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
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address range byte mode. address range A0-A18 word mode.
operation
SA10
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA11
Table Table sector-address ranges TMS29F800T/B.
Table Top-Boot Sector-Address Ranges
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SECTOR SIZE 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 32K-Byte 16K-Byte 8K-Byte 8K-Byte (x8) ADDRESS RANGE C0000H-CFFFFH D0000H-DFFFFH FC000H-FFFFFH A0000H-AFFFFH B0000H-BFFFFH E0000H-EFFFFH FA000H-FBFFFH F0000H-F7FFFH F8000H-F9FFFH 00000H-0FFFFH 10000H-1FFFFH 20000H-2FFFFH 30000H-3FFFFH 40000H-4FFFFH 50000H-5FFFFH 60000H-6FFFFH 70000H-7FFFFH 80000H-8FFFFH 90000H-9FFFFH (x16) ADDRESS RANGE 7C000H-7CFFFH 7D000H-7DFFFH 7E000H-7FFFFH 78000H-7BFFFH 08000H-0FFFFH 18000H-1FFFFH 28000H-2FFFFH 38000H-3FFFFH 48000H-4FFFFH 58000H-5FFFFH 68000H-6FFFFH 10000H-17FFFH 20000H-27FFFH 30000H-37FFFH 40000H-47FFFH 50000H-57FFFH 60000H-67FFFH 70000H-77FFFH 00000H-07FFFH
address range byte mode. address range A0-A18 word mode.
operation (continued)
SA10
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA11
Table Bottom-Boot Sector-Address Ranges
SECTOR SIZE
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
(x8) ADDRESS RANGE
C0000H-CFFFFH
D0000H-DFFFFH
A0000H-AFFFFH
B0000H-BFFFFH
E0000H-EFFFFH
F0000H-FFFFFH
30000H-3FFFFH
40000H-4FFFFH
50000H-5FFFFH
60000H-6FFFFH
70000H-7FFFFH
80000H-8FFFFH
90000H-9FFFFH
(x16) ADDRESS RANGE
18000H-1FFFFH
28000H-2FFFFH
38000H-3FFFFH
48000H-4FFFFH
58000H-5FFFFH
68000H-6FFFFH
78000H-7FFFFH
20000H-27FFFH
30000H-37FFFH
40000H-47FFFH
50000H-57FFFH
60000H-67FFFH
70000H-77FFFH
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16K-Byte 32K-Byte 64K-Byte 64K-Byte 8K-Byte 8K-Byte 08000H-0FFFFH 10000H-1FFFFH 20000H-2FFFFH 00000H-03FFFH 04000H-05FFFH 06000H-07FFFH 08000H-0FFFFH 00000H-01FFFH 02000H-02FFFH 03000H-03FFFH 04000H-07FFFH 10000H-17FFFH
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
operation (continued)
Table Table operation modes TMS29F800T/B. Table Byte-Operation Mode (BYTE VIL)
MODE Algorithm-selection mode FUNCTIONS power supply Read Output disable Standby write inhibit Write Temporary sector unprotect RESET DQ0-DQ7 Manufacturer-Equivalent Code (TMS29F800T/B Byte) Device-Equivalent Code (TMS29F800T Byte) Device-Equivalent Code (TMS29F800B Byte) Data Hi-Z Hi-Z Data Data Hi-Z
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Verify sector protect Hardware reset
Legend: Logic Logic 12.0 VIH. Table valid address data during write.
Table Word-Operation Mode (BYTE =VIH)
MODE Algorithm-selection mode FUNCTIONS power supply Read Output disable Standby write inhibit Write Temporary sector unprotect Verify sector protect Hardware reset RESET DQ0-DQ15 DQ15 Manufacturer-Equivalent Code (TMS29F800T/B Word) Device-Equivalent Code 22D6h (TMS29F800T Word) Device-Equivalent Code 2258h (TMS29F800B Word) Data Hi-Z Hi-Z Data Data Hi-Z
Legend: Logic Logic 12.0 VIH. Table valid address data during write.
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
read mode logic-low signal applied pins allows output TMS29F800T/B read. When more '29F800T/B devices connected parallel, output device read without interference. power control must used device selection. output control used gate data output onto from selected device. address-access time (tAVQV) delay from stable address valid output data. chip-enable (CE) access time (tELQV) delay from stable addresses valid output data. output-enable access time (tGLQV) delay from valid output data when equals logic addresses stable least duration tAVQV-tGLQV. standby mode supply current reduced applying logic-high level RESET enter standby mode. standby mode, outputs placed high-impedance state. Applying CMOS logic-high level RESET reduces current Applying logic-high level RESET reduces current '29F800T/B deselected during erasure programming, device continues draw active current until operation complete. output disable When equals equals VIH, output from device disabled output pins (DQ0-DQ15) placed high-impedance state. automatic-sleep mode '29F800 built-in feature called automatic-sleep mode minimize device energy consumption which independent enabled when addresses remain stable Typical sleep-mode current Sleep mode does affect output data, which remains latched available system.
algorithm selection
algorithm-selection mode provides access binary code that matches device with proper programming erase command operations. This mode activated when (11.5 12.5 placed address Address pins must logic low. bytes code accessed toggling address from VIH. Address pins other than logic logic high. algorithm-selection mode also read using command register, which useful when available placed address Table shows binary algorithm-selection codes. Table Algorithm-Selection Codes (5-V Single Power Supply)
CODE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
Manufacturerequivalent code
TMS29F800T-Byte
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
TMS29F800B-Byte TMS29F800T
22D6H 2258H
TMS29F800B
Sector protection
VIL, VIL, VIL,
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
erasure programming Erasure programming '29F800 accomplished writing sequence commands using standard microprocessor write timing. commands written command register input command-state machine (CSM). interprets command entered initiates program, erase, suspend, resume operations instructed. acts interface between write-state machine (WSM) external-chip operations. controls voltage generation, pulse generation, preconditioning, verification memory contents. Program block-/chip-erase functions fully automatic. Once program erase operation been reached, device resets internally read mode. drops below low-voltage-detect level (VLKO), programming erase operation aborted subsequent writes ignored until level greater than VLKO. control pins must logically correct prevent unintentional command writes programming erasing. command definitions Device operating modes selected writing specific address data sequences into command register. Table defines valid command sequences. Writing incorrect address data values writing them incorrect sequence causes device reset read mode. command register does occupy addressable memory location. register used store command sequence, along with address data needed memory array. Commands written setting VIL, VIH, bringing from logic high logic low. Addresses latched falling edge data latched rising edge Holding toggling alternative method. switching characteristics write/erase/program-operations section specific timing information.
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command definitions (continued)
Sector-erase resume (byte) Sector-erase resume (word) Sector-erase suspend (byte) Sector-erase suspend (word) Sector erase (byte) Sector erase (word) Chip erase (byte)
LEGEND: Address location read Address location programmed Address sector erased Addresses select sectors. Data read selected address location Data programmed selected address location
Algorithm selection (byte)
Algorithm selection (word)
Read/reset (byte)
Read/reset (word)
Read/reset (byte)
Read/reset (word)
COMMAND
CYCLES
ADDR
xxxxH
2AAH
2AAH
555H
555H
CYCLE
xxAAH
xxAAH
xxF0H
DATA
ADDR
Table Command Definitions
2AAH
2AAH
555H
555H
CYCLE
xx55H
xx55H
DATA
ADDR
2AAH
2AAH
555H
555H
CYCLE
xxF0H
xx90H
DATA
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
ADDR
CYCLE
22D6H
2258H
DATA
ADDR
CYCLE
DATA
ADDR
CYCLE
DATA
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Chip erase (word)
Program (byte)
Program (word)
XXXXH
XXXXH
2AAH
2AAH
2AAH
555H
555H
555H
xxAAH
xxAAH
xxAAH
xxB0H
xx30H
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Erase resume valid only after erase-suspend operation
Erase resume valid only after erase-suspend operation
Erase suspend valid during sector-erase operation
Erase suspend valid during sector-erase operation
2AAH
2AAH
2AAH
555H
555H
555H
xx55H
xx55H
xx55H
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2AAH 2AAH 2AAH 555H 555H 555H xxA0H xx80H xx80H 2AAH 2AAH 555H 555H xxAAH xxAAH 2AAH 2AAH 555H 555H xx55H xx55H 2AAH 555H
xx30H
xx10H
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
read/reset command read reset mode activated writing either read/reset command sequences into command register. device remains this mode until another valid command sequence input command register. Memory data available read mode read with standard microprocessor read-cycle timing. power device defaults read/reset mode. read/reset command sequence required memory data available. algorithm-selection command algorithm-selection command allows access binary code that matches device with proper programming erase command operations. After writing three-bus-cycle command sequence, first byte algorithm-selection code read from address XX00h. second byte code read from address XX01h (see Table This mode remains effect until another valid command sequence written device. program command Programming four-bus-cycle command sequence. first three cycles device into program-setup state. fourth cycle loads address location data programmed into device. addresses latched falling edge while data latched rising edge fourth cycle. rising edge starts program operation. embedded programming function automatically provides needed voltage timing program verify cell margin. further commands written device during program operation ignored. Programming performed address location sequence. When erased, bits logic-high state. Logic lows programmed into device. Only erase operation change bits from logic lows logic highs. Attempting program into that been programmed previously causes internal-pulse counter exceed pulse-count limit, which sets exceed-time-limit indicator (DQ5) logic-high state. automatic-programming operation complete when data equivalent data written DQ5, which time device returns read mode addresses longer latched. Figure shows flowchart typical device-programming operation. chip-erase command Chip erase six-bus-cycle command sequence. first three cycles device into erase-setup state. next cycles unlock erase mode. sixth cycle loads chip-erase command. This command sequence required ensure that memory contents erased accidentally. rising edge starts chip-erase operation. further commands written device during chip-erase operation ignored. embedded chip-erase function automatically provides voltage timing needed program verify memory cells prior electrical erase. then erases verifies cell margin automatically without programming memory cells prior erase. Figure shows flowchart typical chip-erase operation.
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-erase command Sector-erase six-bus-cycle command sequence. first three cycles device into erase-setup state. next cycles unlock erase mode then sixth cycle loads sector-erase command sector-address location erased. address location within desired sector used. addresses latched falling edge sector-erase command (30h) latched rising edge sixth cycle. After delay from rising edge sector-erase operation begins selected sector(s). Additional sectors selected erased concurrently during sector-erase command sequence. each additional sector selected erase, another cycle issued. cycle loads next sector-address location sector-erase command. time between previous cycle start next cycle must less than otherwise, sector location loaded. time delay from rising edge last starts sector-erase operation. there falling edge within time delay, timer reset. nineteen sector-address locations loaded sequence. state delay timer monitored using sector-erase delay indicator (DQ3). logic low, time delay expired. operation status section description.
embedded sector-erase function automatically provides needed voltage timing program verify memory cells prior electrical erase then erases verifies cell margin automatically. Programming memory cells prior erase required. operation status section full description. Figure shows flowchart typical sector-erase operation. erase-suspend command erase-suspend command (B0h) allows interruption sector-erase operation read data from unaltered sectors device. Erase-suspend one-bus-cycle command. addresses erase-suspend command (B0h) latched rising edge Once sector-erase operation progress, erase-suspend command requests internal write-state machine halt operation predetermined breakpoints. erase-suspend command valid only during sector-erase operation invalid during programming chip-erase operations. sector-erase delay timer expires immediately erase-suspend command issued while delay active. After erase-suspend command issued, device takes between suspend operation. toggle must monitored determine when suspend been executed. When toggle stops toggling, data read from sectors that selected erase. Reading from sector selected erase result invalid data. operation status section full description. Once sector-erase operation suspended, reading from programming sector that being erased performed. This command applicable only during sector-erase operation. other command written during erase-suspend mode suspended sector ignored.
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command other than erase suspend (B0h) sector erase (30h) written device during sector-erase operation causes device exit sector-erase mode contents sector(s) selected erase longer valid. complete sector-erase operation, re-issue sector-erase command sequence.
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
erase-resume command erase-resume command (30h) restarts suspended sector-erase operation from point where halted. Erase resume one-bus-cycle command. addresses erase-resume command (30h) latched rising edge When erase-suspend/erase-resume command combination written, internal-pulse counter (exceed timing limit) reset. erase-resume command valid only erase-suspend state. After erase-resume command executed, device returns valid sector-erase state further writes erase-resume command ignored. After device resumed sector-erase operation, another erase-suspend command issued device.
operation status
status device during automatic-programming algorithm, chip-erase, automatic-erase algorithm determined three ways:
DQ7: Data polling DQ6: Toggle Ready busy
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status-bit definitions During operation automatic embedded program erase functions, status device determined reading data state designated outputs. data-polling (DQ7) toggle (DQ6) require multiple successive reads observe change state designated output. Table defines values status flags.
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status-bit definitions (continued) Table Operation Status Flags
DEVICE OPERATION Programming Program/erase auto-erase progress Erase-suspend Erase suspend mode Program erase suspend Programming Exceeded time limits Program/erase auto erase Program erase suspend Successful operation complete Programming complete Sector-/chip-erase complete Erase-sector address Non-erase sector address RY/BY
data-polling (DQ7) data-polling-status function outputs complement data latched into data register while write-state machine (WSM) engaged program erase operation. Data changes from complement true indicate operation. Data-polling available only during programming, chip-erase, sector-erase, sector-erase-timing delay. Data-polling valid after rising edge last cycle command sequence loaded into command register. Figure shows flowchart data-polling. During program operation, reading outputs complement data programmed selected address location. Upon completion, reading outputs true data loaded into program-data register. During erase operations, reading outputs logic low. Upon completion, reading outputs logic high. Also, data-polling must performed sector address that within sector that being erased. Otherwise, status invalid. When using data-polling, address should remain stable throughout operation. During data-polling read, while logic low, data change asynchronously. Depending read timing, system read valid data DQ7, while other pins still invalid. subsequent read device valid. Figure data-polling timing diagram. toggle (DQ6) toggle-bit status function outputs data DQ6, which toggles between logic high logic while engaged program erase operation. When stops toggling after consecutive reads same address, operation complete. toggle available only during programming, chip erase, sector erase, sector-erase-timing delay. Toggle-bit data valid after rising edge last cycle command sequence loaded into command register. Figure shows flowchart toggle-bit status-read algorithm. Depending read timing, stop toggling while other pins still invalid subsequent read device valid. Figure toggle-bit timing diagram.
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toggle, data, Tog= toggle DQ4, DQ1, reserved future use. toggled when sector address applied erasing sector. cannot toggled when sector address applied non-erasing sector. used determine which sectors erasing which not. Status flags apply when outputs read from address non-erase-suspend operation. high (exceeded timing limits), successive reads from problem sector causes toggle.
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
exceed time limit (DQ5) Program erase operations internal-pulse counter limit number pulses applied. pulse-count limit exceeded, logic-high data state. This indicates that program erase operation failed. does change from complemented data true data does stop toggling when read. continue operation, device must reset. exceed-time-limit condition occurs when attempting program logic-high state into that been programmed previously logic low. Only erase operation change bits from logic logic high. After reset, device functional erased reprogrammed. sector-load-timer (DQ3) sector-load-timer status bit, DQ3, used determine whether time load additional sector addresses expired. After completion sector-erase command sequence, remains logic This indicates that another sector-erase command sequence issued. logic high, indicates that delay expired attempts issue additional sector-erase commands ignored. sector-erase command section description. data-polling toggle valid during 100-µs time delay used determine valid sector-erase command been issued. ensure additional sector-erase commands have been accepted, status should read before after each additional sector-erase command. logic both reads, additional sector-erase command accepted. toggle (DQ2) state determines whether device algorithmic-erase mode erase-suspend mode. toggles successive reads issued erasing erase-suspended sector, assuming case latter that device erase-suspend-read mode. also toggles when becomes logic high timer-exceed limit, reads issued failed sector. does toggle other sector failure. When device erase-suspend-program mode, successive reads from non-erase-suspended sector causes logic high DQ2. ready/ busy (RY/ indicates when device accept commands after performing algorithmic operations. (open-drain output) low, device busy with either program erase operation does accept other commands except erase suspend. While erase-suspend mode, remains high. program mode, valid (logic low) after fourth pulse. erase mode, valid after sixth pulse. After delay period, tbusy, becomes valid. Figure timing waveform. Since open-drain output, several such bits combined parallel with pullup resistor VCC. hardware-reset (RESET) When RESET driven logic low, forces device currently active mode into reset state. also avoids contention placing outputs into high-impedance state duration RESET pulse. During program erase operation, RESET asserted logic low, remains logic until reset operation complete. Since this take from used sense reset completion user allow maximum RESET asserted during read mode, then reset operation complete within Figure Figure timing specifications. RESET also used drive device into deep power-down (standby) mode applying ICC4 reads typical, maximum CMOS inputs. Standby mode entered anytime, regardless condition
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
hardware-reset (RESET) (continued) Asserting RESET during program erase leave erroneous data address locations. These locations need updated after device resumes normal operations. minimum must allowed after RESET goes high before valid read take place.
RESET
RY/BY
Figure Device Reset During Program Erase Operation
RY/BY
Figure Device Reset During Read Mode
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RESET
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
word- byte-mode configuration BYTE used device configuration. BYTE logic device word mode with data outputs valid DQ15 output representing DQ15. Similarly, BYTE logic device byte mode with only valid. remaining outputs high-impedance mode DQ15 used input least significant (A1) address function. Figure Figure timing specifications.
tELFH BYTE
DQ14
DQ14 tFHQV
DQ14
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DQ15/A
DQ15
Figure Word-Mode Configuration
tELFL BYTE
DQ14
DQ14 tFLQV
DQ14
DQ15/A
DQ15
Figure Byte-Mode Configuration temporary hardware-sector unprotect feature This feature temporarily enables both programming erase operations combination nineteen sectors that were previously protected. unprotect feature enabled using high voltage (11.5 12.5 RESET pin, using standard command sequences. Normally, device delivered with sectors unprotected.
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-protect programming sector-protect programming mode activated when VIL, address control forced VID. Address VIH.The sector-select address pins A12-A18 used select sector protected. Address pins A0-A11 pins must stable either VIH. Once addresses stable, pulsed causing programming begin falling edge terminate rising edge Figure flowchart sector-protect algorithm Figure shows timing diagram sector-protect operation. Commands program erase protected sector change data contained sector. Attempts program erase protected sector cause data-polling (DQ7) toggle (DQ6) operate from then return valid data. sector-protect verify Verification sector-protection programming activated when VIH, VIL, VIL, address VID. Address pins VIL, VIH. sector-address pins A12-A18 select sector that verified. other addresses VIL. sector that selected protected, output 01h. sector protected, output 00h. Sector-protect verify also read using algorithm-selection command. After issuing three-bus-cycle command sequence, sector-protection status read DQ0. address pins VIL, VIH, VIL, then sector address pins A12-A18 select sector verified. remaining addresses VIL. sector selected protected, outputs logic-high state. sector selected protected, outputs logic-low state. This mode remains effect until another valid command sequence written device. Figure flowchart sector-protect algorithm Figure shows timing diagram sector-protect operation. sector unprotect Prior sector unprotect, sectors must protected using sector-protect programming mode. sector unprotect activated when address control forced VID. Address pins while VIL. sector-select address pins A12-A18 VIH. sectors unprotected parallel once inputs stable, pulsed causing unprotect operation begin falling edge terminate rising edge Figure flowchart sector-unprotect algorithm Figure shows timing diagram sector-unprotect operation. sector-unprotect verify Verification sector unprotect accomplished when VIH, VIL, =VIL, address VID, then select sector verified. Address pins VIH, VIL. other addresses VIL. sector selected protected, output 01h. sector protected, output 00h. Sector unprotect also read using algorithm-selection command. write lockout During power-up power-down operations, write cycles locked less than VLKO. VLKO, command input disabled device reset read mode. power VIL, VIL, VIH, device does accept commands rising edge device automatically powers read mode. glitching Pulses less than (typical) issue write cycle. power supply considerations Each device should have 0.1-µF ceramic capacitor connected between suppress circuit noise. Printed circuit traces should appropriate handle current demand minimize inductance.
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PRODUCT PREVIEW
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range: inputs except (see Note 13.5 Output voltage range (see Note Ambient temperature range during read erase program, 70°C 40°C 85°C 40°C 125°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect VSS. voltage input undershoot periods less than (see Figure voltage input output overshoot periods less than (see Figure
recommended operating conditions
PRODUCT PREVIEW
UNIT Supply voltage High-level High level input voltage level input voltage Low-level CMOS CMOS *VCC -0.5 -0.5 11.5 VCC+0.5 VCC+0.5 VLKO Algorithm-selection sector-protect input voltage lock-out voltage Ambient temperature 12.5 version version version
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
electrical characteristics over recommended ranges supply voltage ambient temperature
capacitance over recommended ranges supply voltage ambient temperature
PARAMETER Input capacitance (All inputs except Input capacitance (A9, Output capacitance TEST CONDITIONS UNIT
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PRODUCT PREVIEW
PARAMETER TEST CONDITIONS UNIT TTL-input level High-level output voltage Low-level output voltage Input current (leakage) CMOS-input level CMOS-input level MIN, MIN, MIN, MIN, -2.5 VCC-0.4 0.85 0.45 Output current (leakage) High-voltage current (standby) supply current (standby) supply current (see Note Note MAX, VCC, VIH, 0.2, VIL, VIL, ICC1 ICC2 ICC3 ICC4 TTL-input level Byte CMOS-input level Word supply current (see Note supply current (standby during reset) MAX, RESET ICC5 Automatic sleep mode (see Note Note NOTES: current read mode, switching current while erase program operation progress Automatic sleep mode entered when addresses remain stable IOUT
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
PARAMETER MEASUREMENT INFORMATION
Output Under Test (see Note Note
0.45
PRODUCT PREVIEW
NOTES: includes probe fixture capacitance. testing inputs driven logic high 0.45 logic low. Timing measurements made logic high logic both inputs outputs. Each device should have 0.1-µF ceramic capacitor connected between closely possible device pins.
Figure Test Output Load Circuit
+0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
Figure Maximum Positive Overshoot Waveform
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switching characteristics over recommended ranges supply voltage ambient temperature, read-only operation
th(D) ten(E) ten(G) tdis(E) tdis(G) ta(E) ta(G) tc(R) ta(A) Hold time, output from address change Enable time, impedance Enable time, impedance Disable time, high impedance Disable time, high impedance Access time, Access time, Access time, address Cycle time, read PARAMETER ALTERNATE SYMBOL tGHQZ tELQX tAXQX tGLQX tGLQV tEHQZ tAVAV tAVQV tELQV '29F800-80 '29F800-90
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'29F800-100 '29F800-120 UNIT
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
PRODUCT PREVIEW
PRODUCT PREVIEW
TMS29F800T, TMS29F800B 8-BIT 524288 16-BIT FLASH MEMORIES
switching characteristics over recommended ranges supply voltage ambient temperature, controlled
PARAMETER tc(W) tsu(A) th(A) tsu(D) th(D) tsu(E) th(E) tw(WL) tw(WH) trec(R) Cycle time, write Setup time, address Hold time, address Setup time, data Hold time, data valid after high Setup time, Hold time, Pulse duration, Pulse duration, high Recovery time, read before write Hold time, read Hold time, toggle, data Setup time, Transition time, (see Note Note Pulse duration, (see Note Pulse duration, (see Note Setup time, (see Note Setup time, (see Notes tc(W)PR (W)PR Cycle time, programming operation Byte Word SYMBOL tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tWHEH tWLWH1 tWHWL tGHWL tWHGL1 tWHGL2 tVCEL tHVT tWLWH2 tWLWH3 tEHVWL tGHVWL tWHWH1 tRPD tRPD tBUSY tELFL tELFH '29F800-80 '29F800-90 '29F800-100 '29F800-120 UNIT
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Template Release Date: 7-11-94
Write recovery time from RESET time RESET high time before read RESET power-down time RESET CE/WE Program/erase valid delay BYTE switching high NOTES: Sector-protect timing Sector-unprotect timing
switching characteristics over recommended ranges supply voltage ambient temperature, controlled (continued)
PARAMETER BYTE switching output 3-state BYTE switching high output active tc(W)ER Cycle time, sector-erase operation Cycle time, chip-erase operation SYMBOL tFLQZ tFHQV tWHWH2 tWHWH3 '29F800-80 '29F800-90 '29F800-100 '29F800-120 UNIT
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TMS29F800T, TMS29F800B 8-BIT 524288 16-BIT FLASH MEMORIES
PRODUCT PREVIEW
PRODUCT PREVIEW
TMS29F800T, TMS29F800B 8-BIT 524288 16-BIT FLASH MEMORIES
switching characteristics over recommended ranges supply voltage ambient temperature, controlled
PARAMETER tc(W) tsu(A) th(A) tsu(D) th(D) tsu(W) th(W) tw(EL) tw(EH) trec(R) th(C) Cycle time, write Setup time, address Hold time, address Setup time, data Hold time, data Setup time, Hold time, Pulse duration, Pulse duration, high Recovery time, read before write Setup time, Hold time, read Hold time, toggle, data Programming operation Byte Word ALTERNATE SYMBOL tAVAV tAVEL tELAX tDVEH tEHDX tWLEL tEHWH tELEH1 tEHEL tGHEL tGLEL tEHGL1 tEHGL2 tEHEH1 tEHEH2 tEHEH3 tFLQZ '29F800-80 '29F800-90 '29F800-100 '29F800-120 UNIT
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Template Release Date: 7-11-94
Cycle time, sector-erase operation Cycle time, chip-erase operation BYTE switching output 3-state
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
erase program performance
PARAMETER Sector-erase time Program word time Program byte time Chip-programming time TEST CONDITIONS Excludes programming prior erasure Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead 5200 UNIT
Erase/program cycles cycles internal algorithms allow 2.5-ms byte-program time. only after byte takes theoretical maximum time program. minimal number bytes require signficantly more programming pulses than typical byte. majority bytes program within pulses. This demonstrated typical maximum programming time listed above. 25°C, VCC, cycles, typical pattern Under worst-case conditions: 90°C, VCC, cycles
latchup characteristics (see Note
PARAMETER Input voltage with respect pins except pins (including Input voltage with respect pins Current NOTE Includes pins except test conditions: time UNIT
capacitance, packages (see Note
PARAMETER COUT CIN2 Input capacitance Output capacitance Control capacitance TEST CONDITIONS VOUT UNIT
NOTE Test conditions: 25°C,
data retention
PARAMETER Minimum pattern data retention time TEST CONDITIONS 150°C 125°C UNIT Years
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PRODUCT PREVIEW
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
read operation
tAVAV Addresses Valid Addresses
tAVQV tEHQZ tELQV tGHQZ tGLQV
PRODUCT PREVIEW
tGLQX tAXQX tELQX
Valid Data
Figure Waveform Read Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
write operation
Start
Write Cycle 2AAH/AAH 555H XXAAH Write Cycle 555H/55H 2AAH XX55H
Write Cycle 2AAH/A0H 555H XXA0H Write Cycle Program Address Program Data
Poll Device Status
Operation Complete
Next Address
Last Address
Figure Program Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
write operation (continued)
tAVAV Addresses 555H tWLAX tAVWL tELWL tWHEH tGHWL tWLWH1 tWHDX tWHWL 2AAH 555H
PRODUCT PREVIEW
tWHWH1 tDVWH NOTES: xxAAH xx55H xxA0H DOUT
Address programmed Data programmed Complement data written Timing diagram shown word-mode operation.
Figure Waveform Program Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
write operation (continued)
tAVAV Addresses 555H tAVEL tELEH tGHEL tDVEH tWLEL tEHDX NOTES: xxAAH xx55H xxA0H DOUT tEHWH tWHWH1 tEHEL tELAX 2AAH 555H
PA=Address programmed Data programmed Complement data written Timing diagram shown word-mode operation.
Figure Alternate CE-Controlled Write Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
chip-erase operation
Start
Write Cycle 2AAH/AAH 555H XXAAH Write Cycle 555H/55H 2AAH XX55H Write Cycle 2AAH/80H 555H XX80H Write Cycle 2AAH/AAH 555H XXAAH
PRODUCT PREVIEW
Write Cycle 555H/55H 2AAH XX55H Write Cycle 2AAH/10H 555H XX10H
Poll Device Status
Operation Complete
Figure Chip-Erase Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
chip-erase operation (continued)
tAVAV Addresses 555H 555H 2AAH tWLAX tAVWL tELWL tWHEH tWHDX tGHWL tWHWL tWLWH1 tWHWH3 tDVWH xx80H xxAAH xx55H xx10H DQ7=0 DOUT=FFH 555H
NOTES: valid address Figure details last four cycles six-bus-cycle operation. Timing diagram shown word-mode operation.
Figure Waveform Chip-Erase Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-erase operation
Start
Write Cycle 2AAH/AAH 555H XXAAH Write Cycle 555H/55H 2AAH XX55H Write Cycle 2AAH/80H 555H XX80H Write Cycle 2AAH/AAH 555H/XXAAH
PRODUCT PREVIEW
Write Cycle 555H/55H 2AAH XX55H Write Cycle Sector Address (Byte)/xx30H (Word)
Load Additional Sectors Poll Device Status
Operation Complete
Figure Sector-Erase Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-erase operation (continued)
tAVAV Addresses 555H tWLAX tAVWL tELWL tWHEH tGHWL tWLWH1 tWHWH2 tDVWH xx80H xxAAH xx55H xx30H DQ7=0 DOUT=FFH tWHDX tWHWL 555H 2AAH
NOTES: Sector address erased Figure details last four cycles six-bus-cycle operation. Timing diagram shown word-mode operation.
Figure Waveform Sector-Erase Operation
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PRODUCT PREVIEW
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
data-polling operation
Start
Read Addr
Data
PRODUCT PREVIEW
Read Addr
Data
Fail Pass
NOTES: Polling status bits change asynchronously. Read after changes states. Program address byte-programming Selected sector address sector erase valid address chip erase
Figure Data-Polling Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
data-polling operation (continued)
Addresses tAVQV tELQV tGLQV tWHGL1 tGHQX tWHWH1, NOTES: DOUT DOUT tGHQZ tAXQX tAVQV tELQV
tGLQV
Last command data written device Complement data written Valid data output Valid address byte-program, sector-erase, chip-erase operation
Figure Waveform Data-Polling Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
toggle-bit operation
Start
Read Addr
Read Addr
Toggle
PRODUCT PREVIEW
Read
Toggle
Fail Pass
NOTE Polling status bits change asynchronously. Read after changes states.
Figure Toggle-Bit Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
toggle-bit operation (continued)
Addresses
tELQV
tAVQV tELQV
tGLQV tGLQV
tWHGL2 tWHWH1,
TOGGLE TOGGLE TOGGLE STOP TOGGLE
DOUT
NOTES:
DOUT
Last command data written device Toggle output Valid data output Valid address byte-program, sector-erase, chip-erase operation
Figure Waveforms Toggle-Bit Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-protect operation
Start
Select Sector Address
VID, VIL,
Apply 100-µs Pulse VIL, VIH,
PRODUCT PREVIEW
Read Data
Data
Sector Protect Failed
Protect Additional Sectors Write Reset Command
Figure Sector-Protect Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-protect operation (continued)
tHVT tAVQV Sector Address Sector Address
tHVT tGLQV NOTE DOUT selected sector protected, sector protected DOUT tGHVWL tWLWH2 tHVT
Figure Waveform Sector-Protect Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-unprotect operation
Start
Protect Sectors
VID, VIL,
Apply 10-ms Pulse VIL, VIH,
PRODUCT PREVIEW
Select Sector Address
Read Data
1000
Data
Next Sector Address
Sector Unprotect Failed
Last Sector Write Reset Command
Figure Sector-Unprotect Algorithm
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
sector-unprotect operation (continued)
tHVT tAVQV Sector Address
tHVT tWLWH3 tGLQV NOTE DOUT selected sector protected, sector protected DOUT tGHVWL tHVT
Figure Waveform Sector-Unprotect Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
temporary sector-unprotect operation
Start
RESET (see Note Perform Erase Program Operations
RESET
Temporary SectorGroup-Unprotect Completed (see Note NOTES: protected sectors unprotected previously protected sectors protected once again
PRODUCT PREVIEW
Figure Temporary Sector-Unprotect Algorithm
RESET
tVLHT
Program Erase Command Sequence
Figure Temporary Sector-Unprotect Timing Diagram
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
PARAMETER MEASUREMENT INFORMATION
BYTE tELFL, tELFH DQ14 Data Output (DQ0 DQ14) Data Output (DQ0 DQ7)
DQ15
DQ15 Output
Address Input
tFLQZ
Figure BYTE Timing Diagram Read Operation
Falling Edge Last Signal
BYTE tSET (tAS) tHOLD (tAH)
Figure BYTE Timing Diagram Write Operation
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
PARAMETER MEASUREMENT INFORMATION
Rising Edge Last Signal
Entire Programming Erase Operations
tBUSY
Figure Timing Diagram During Program/Erase Operations
PRODUCT PREVIEW
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TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
(R-PDSO-G44)
1,27 0,45 0,35
PLASTIC SMALL-OUTLINE PACKAGE
0,16
13,40 13,20
16,10 15,90
0,15 28,30 28,10
Gage Plane 0,25 0,95 0,65
Seating Plane 2,63 0,50 0,10
4073325 09/95 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion.
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PRODUCT PREVIEW
TMS29F800T, TMS29F800B 1048576 8-BIT/ 524288 16-BIT FLASH MEMORIES
(R-PDSO-G**)
SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27)
0.012 (0,30) 0.004 (0,10) 0.728 (18,50) 0.720 (18,30)
0.008 (0,21)
PRODUCT PREVIEW
0.795 (20,20) 0.780 (19,80) 0.041 (1,05) 0.037 (0,95)
0.006 (0,15)
0.047 (1,20)
Seating Plane 0.028 (0,70) 0.020 (0,50) 0.004 (0,10)
0.010 (0,25)
PINS**
0.402 (10,20) 0.386 (9,80)
0.476 (12,10) 0.469 (11,90)
0.555 (14,10) 0.516 (13,10) 4073307/B 11/96
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice.
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

Single Power Supply Supports Read/Write Operation Organization 048576

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