2526-5 Features Word-organized programmable nonvolatile memo

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2526-5 Features Word-organized programmable nonvolatile memo

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Nonvolatile Memory 2-Kbit E2PROM with
2526-5
Features
Word-organized programmable nonvolatile memory
n-channel floating-gate technology (E2PROM) 8-bit organization Supply voltage Serial 2-line data input output (I2C Bus) Reprogramming mode, erase/write cycle Reprogramming means on-chip control (without external control) Check programming process Data retention years More than reprogramming cycles address Compatible with 2526. Exceptions: Conditions total erase current consumption Ordering Code Q67100-H5095
P-DIP-8-1
Type 2526-5
Package P-DIP-8-1
Circuit Description Interface bidirectional 2-line transfer data between various integrated circuits. consists serial data line serial clock line SCL. data line requires external pull-up resistor (open drain output stage). possible operational states shown figure quiescent state, both lines high, i.e. output stage data line disabled. long remains "1", information changes data indicate start data transfer between components. transition from start condition, transition from stop condition. During data transfer information data will only change while clock line "0". information valid long "1". conjunction with system, memory component operate receiver transmitter (slave receiver slave transmitter). Between start stop condition, information always transmitted byte-organized form. Between falling edge eighth clock pulse ninth acknowledge clock pulse, memory component sets SDA-line confirmation reception, chip select conditions have been met. During output data, data output memory high impedance during ninth clock pulse (acknowledge master). signal timing required operation summarized figure
Semiconductor Group
07.94
2526-5
Control Functions memory component controlled controller (master) operating modes: read-out cycle, reprogramming cycle, including erase write memory address. both operating modes, controller, transmitter, provide bytes additional acknowledge clock pulse after start condition. During memory read, least nine additional clock pulses required accept data from memory acknowledge master, before stop condition follow. case programming, active programming process only started stop condition after data input (see figure chip select word contains chip select bits CS0, CS2, thus allowing memory chips connected parallel. Chip select achieved when three control bits logically correspond selected conditions select inputs. Check Programming Abortion Programming Process chip addressed during active reprogramming entering CS/E, programming process terminated. however, addressed entering CS/A, entry will ignored. Only after programming been terminated will chip respond CS/A. This allows user check whether programming process been reached (see figure Memory Read After input first control words CS/E resetting start condition input third control word CS/A, memory ready read. During acknowledge clock nine, memory information transferred parallel mode shift register. Subsequent falling edge acknowledge clock, data output impedance first data sampled (see figure With every shift clock, additional reaches output. After reading byte, internal address counter automatically incremented when master receiver switches data line "low" during ninth clock (acknowledge master). number memory locations thus read after other. address 256, overflow address initiated. With stop condition, data output returns high-impedance mode. internal sequence control memory component reset from read quiescent state with stop condition.
Semiconductor Group
2526-5
Memory Reprogramming reprogramming cycle memory word comprises erase subsequent write process. During erase, eight bits selected word into state. During write, states generated according information internal data register, i.e. according third input control word. After 27th last clock control word input, active programming process started stop condition. active reprogramming process executed under on-chip control. time required reprogramming depends component deviation data patterns. Therefore, with rated supply voltage, erase/write process extends over max. more typically, case data word input without write request (write request defined data data register "0"), write process suppressed programming time shortened. During subsequent programming already erased memory address, erase process suppressed again, that reprogramming time also shortened. Important: Switch-On Mode Chip Reset After supply voltage been connected, data output will high-impedance mode. rule, first operating mode entered, should read process word address. result built-in "power-on reset" circuit, programming requests will accepted immediately after supply voltage been switched Total Erase Enter control word CS/E, load address register with address data register with (hex) erase entire contents memory. Switch input "open" immediately prior generating stop condition. subsequent stop condition triggers total erase. Upon termination "total erase", must reconnected either
Semiconductor Group
2526-5
Configuration (top view)
Definitions Functions Symbol Function Ground Chip select Chip select Chip select open, condition delete complete memory Data line Clock line Test Supply voltage
Semiconductor Group
2526-5
Block Diagram
Semiconductor Group
2526-5
Absolute Maximum Ratings Parameter Supply voltage Input voltage Power dissipation Storage temperature Thermal resistance (system-air) Junction temperature Operating Range Supply voltage Ambient temperature Symbol min. Limit Values max. Unit
Tstg
4.75
5.25
Semiconductor Group
2526-5
Characteristics Parameter Supply voltage Supply current Inputs Input voltages SDA/SCL Input voltages SDA/SCL Input currents Output Output current Leakage current Inputs Input voltages CS0/CS1/CS2 Input voltages CS0/CS1/CS2 Input currents CS0/CS1/CS2 Clock frequency Reprogramming duration Input capacity Total erase Symbol min. Limit Values typ. max. 5.25 4.75 Unit Test Condition
5.25
fSCL tprog
open erase write
5.25
Semiconductor Group
2526-5
Test Circuit
Application Circuit Semiconductor Group
2526-5
Diagrams
Figure Operation States
Semiconductor Group
2526-5
Figure Timing Conditions (high-speed mode)
Parameter Minimum time must free before transmission start Start condition hold time Clock period Clock high period Start condition set-up time, only valid repeated start code Data set-up time Rise time both SDA- SCL-line Fall time both SDA- SCL-line Stop condition set-up time Hold time data
falling edge SCL.
Symbol min.
Limit Values max.
Unit
tBUF tHD;STA tLOW tHIGH tSU;STA tSU;DAT tSU;STO tHD;DAT
Note that transmitter must internally provide least hold time bridge undefined region (max.
Semiconductor Group
2526-5
Figure Programming Control word input CS/E (the reprogramming starts after this stop condition)
Check program
CS/A
when programming finished when programming finished
Program interruption
CS/E
Figure Read Control word input read complete (with word address input) CS/E CS/A bytes Last byte
Automatic incrementation word address shortened: last adapted word address keep unchanged
CS/A
bytes
Last byte
Autoincrement before stop condition
Semiconductor Group
2526-5
Control Word Table Clock CS/E CS/A (Acknowledge) through memory through memory through memory through memory through master
Control Word Input CS/E CS/A CS0, CS1, Chip select data input into memory Chip select data output memory Memory word address Data word memory Data word read memory Data bits Start condition Stop condition Acknowledge from memory Acknowledge from master Chip select bits Memory word address bits
Semiconductor Group

2526-5 Features Word-organized programmable nonvolatile memo

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