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Am29F040B
There change this datasheet result offering device Spansion product. changes that have been made result normal datasheet improvement noted document revision summary, where supported. Future routine revisions will occur when appropriate, changes will noted revision summary.
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Fujitsu continue support existing part numbers beginning with "Am" "MBM". order these products, please only Ordering Part Numbers listed this document.
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Publication Number 21445 Revision
Amendment Issue Date July 2005
July 2005
Am29F040B
Megabit (512 8-Bit) CMOS Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
read write operations Minimizes system level power requirements Manufactured 0.32 process technology Compatible with Am29F040 device High performance Access times fast power consumption typical active read current typical program/erase current typical standby current (standard access time active mode) Flexible sector architecture uniform sectors Kbytes each combination sectors erased Supports full chip erase Sector protection: hardware method locking sectors prevent program erase operations within that sector Embedded Algorithms Embedded Erase algorithm automatically preprograms erases entire chip combination designated sectors Embedded Program algorithm automatically writes verifies bytes specified addresses Minimum 1,000,000 program/erase cycles sector guaranteed 20-year data retention 125°C Reliable operation life system Package options 32-pin PLCC, TSOP, PDIP Compatible with JEDEC standards Pinout software compatible with single-power-supply Flash standard Superior inadvertent write protection Data# Polling toggle bits Provides software method detecting program erase cycle completion Erase Suspend/Erase Resume Suspends sector erase operation read data from, program data non-erasing sector, then resumes erase operation
This Data Sheet states AMD's current technical specifications regarding Products described herein. This Data Sheet revised subsequent versions modifications changes technical specifications.
Publication# 21445 Rev: Amendment/2 Issue Date: July 2005
GENERAL DESCRIPTION
Am29F040B Mbit, volt-only Flash memory organized 524,288 Kbytes bits each. Kbytes data divided into eight sectors Kbytes each flexible erase capability. bits data appear DQ0-DQ7. Am29F040B offered 32-pin PLCC, TSOP, PDIP packages. This device designed programmed in-system with standard system volt supply. 12.0 volt required write erase operations. device also programmed standard EPROM programmers. This device manufactured using AMD's 0.32 process technology, offers features benefits Am29F040, which manufactured using process technology. addtion, Am29F040B second toggle bit, DQ2, also offers ability program Erase Suspend mode. standard Am29F040B offers access times 120, allowing high-speed microprocessors operate without wait states. eliminate contention device separate chip enable (CE#), write enable (WE#) output enable (OE#) controls. device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. device entirely command compatible with JEDEC single-power-supply Flash standard. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from other Flash EPROM devices. Device programming occurs executing program command sequence. This initiates Embedded Program algorithm-an internal algorithm that automatically times program pulse widths verifies proper cell margin. Device erasure occurs executing erase command sequence. This initiates Embedded Erase algorithm-an internal algorithm that automatically preprograms array already programmed) before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. host system detect whether program erase operation complete reading (Data# Polling) (toggle) status bits. After program erase cycle been completed, device ready read array data accept another command. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved programming equipment. Erase Suspend feature enables user erase hold period time read data from, program data sector that selected erasure. True background erase thus achieved. system place device into standby mode. Power consumption greatly reduced this mode. AMD's Flash technology combines years Flash memory manufacturing experience produce highest levels quality, reliability cost effectiveness. device electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. data programmed using electron injection.
Am29F040B
July 2005
TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Configuration Logic Symbol Ordering Information Device Operations Requirements Reading Array Data Writing Commands/Command Sequences Program Erase Operation Status Standby Mode Output Disable Mode.
Figure Maximum Positive Overshoot Waveform.
Operating Ranges Characteristics TTL/NMOS Compatible CMOS Compatible. Test Conditions.
Figure Test Setup. Table Test Specifications
Table Am29F040B Device Operations
Switching Waveforms. Characteristics Read Only Operations
Figure Read Operation Timings
Erase Program Operations.
Figure Program Operation Timings. Figure Chip/Sector Erase Operation Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms). Figure DQ6.
Table Sector Addresses Table
Autoselect Mode.
Table Am29F040B Autoselect Codes (High Voltage Method).10
Sector Protection/Unprotection. Hardware Data Protection
Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit
Characteristics Erase Program Operations.
Alternate Controlled Writes Figure Alternate Controlled Write Operation Timings
Command Definitions Reading Array Data Reset Command. Autoselect Command Sequence Byte Program Command Sequence.
Figure Program Operation
Chip Erase Command Sequence Sector Erase Command Sequence Erase Suspend/Erase Resume Commands.
Figure Erase Operation.
Command Definitions
Table Am29F040B Command Definitions.14
Write Operation Status DQ7: Data# Polling.
Figure Data# Polling Algorithm
DQ6: Toggle DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Figure Toggle Algorithm. Table Write Operation Status.19
Erase Programming Performance Latchup Characteristics TSOP Capacitance PLCC PDIP Capacitance. Data Retention. Physical Dimensions 032-32-Pin Plastic 032-32-Pin Plastic Leaded Chip Carrier 032-32-Pin Standard Thin Small Package. TSR032-32-Pin Reversed Thin Small Outline Package. Revision Summary Revision (May 1997) Revision (January 1998) Revision (January 1998) Revision (April 1998). Revision (January 1999) Distinctive Characteristics. Revision (February 1999) Revision (May 1999) Revision (November 1999) Revision (November 2000). Revision (September 2004).
Absolute Maximum Ratings
Figure Maximum Negative Overshoot Waveform
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Am29F040B
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option -120 -150 Am29F040B
access time, (tACC) access time, (tCE) access time, (tOE)
Note: Characteristics" section more information.
BLOCK DIAGRAM
DQ0-DQ7
Erase Voltage Generator
Input/Output Buffers
State Control Command Register Voltage Generator Chip Enable Output Enable Logic Data Latch
Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A18
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CONNECTION DIAGRAMS
PDIP
PLCC
32-Pin Standard TSOP
32-Pin Reverse TSOP
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Am29F040B
CONFIGURATION
A0-A18 Address Inputs Data Input/Output Chip Enable Write Enable Output Enable Device Ground DQ0-DQ7
LOGIC SYMBOL
A0-A18 DQ0-DQ7
=+5.0 single power supply (see Product Selector Guide device speed ratings voltage supply tolerances)
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July 2005
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination following:
Am29F040B
TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C) Extended (-55°C +125°C) Commercial (0°C +70°C) Pb-free Package Industrial (-40°C +85°C) Pb-free Package Extended (-55°C +125°C) Pb-free Package PACKAGE TYPE 32-Pin Plastic 032) 32-Pin Rectangular Plastic Leaded Chip Carrier 032) 32-Pin Thin Small Outline Package (TSOP) Standard Pinout 032) 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION Product Selector Guide Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F040B Megabit (512 8-Bit) CMOS Volt-only Sector Erase Flash Memory Read, Program, Erase
Valid Combinations AM29F040B-55 AM29F040B-70 AM29F040B-90 AM29F040B-120 AM29F040B-150
Voltage
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
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Am29F040B
DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memor location. register composed latches that store commands, along with address data infor-
mation needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. appropriate device operations table lists inputs control levels required, resulting output. following subsections describe each these operations further detail.
Table
Operation Read Write CMOS Standby Standby Output Disable
Am29F040B Device Operations
A0-A20 DQ0-DQ7 DOUT High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 12.0 Don't Care, Data DOUT Data Out, Address Note: "Sector Protection/Unprotection" section. more information.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain VIH. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. device remains enabled read access until command register contents altered. "Reading Array Data" more information. Refer Read Operations table timing specifications Read Operations Timings diagram timing waveforms. ICC1 Characteristics table represents active current specification reading array data.
indicate address space that each sector occupies. "sector address" consists address bits required uniquely select sector. "Command Definitions" section details erasing sector entire chip, suspending/resuming erase operation. After system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ7-DQ0. Standard read cycle timings apply this mode. Refer "Autoselect Mode" "Autoselect Command Sequence" sections more information. ICC2 Characteristics table represents active current specification write mode. Characteristics" section contains timing specification tables timing diagrams write operations.
Program Erase Operation Status
During erase program operation, system check status operation reading status bits DQ7-DQ0. Standard read cycle timings read specifications apply. Refer "Write Operation Status" more information, each Characteristics section timing diagrams.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive VIL, VIH. erase operation erase sector, multiple sectors, entire device. Sector Address Tables
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced,
Am29F040B
July 2005
outputs placed high impedance state, independent input. device enters CMOS standby mode when held (Note that this more restricted voltage range than VIH.) device enters standby mode when held VIH. device requires standard access time (tCE) before ready read data.
device deselected during erasure programming, device draws active current until operation completed. ICC3 Characteristics tables represents standby current specification.
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
Table
Sector
Sector Addresses Table
Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh
Note: sectors Kbytes size.
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Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires (11.5 12.5 address Address pins must shown Autoselect Codes (High Voltage Method) table. addition, when verifying sector protection, sector address must appear appropriate highest order address bits. Refer corresponding Sector Address Tables. Command Definitions table shows remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. access autoselect codes in-system, host system issue autoselect command command register, shown Command Definitions table. This method does require VID. "Command Definitions" details using autoselect mode.
Table
Description Manufacturer Device Am29F040B Sector Protection Verification
Am29F040B Autoselect Codes (High Voltage Method)
A15-A10 A8-A7 A5-A2 Identifier Code DQ7-DQ0 (protected) (unprotected)
A18-A16 Sector Address
Sector Protection/Unprotection
hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. Sector protection/unprotection must implemented using programming equipment. procedure requires high voltage (VID) address control pins. Details this method provided supplement, publication number 19957. Contact representative obtain copy appropriate document. device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. "Autoselect Mode" details.
gramming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, VIH. initiate write cycle, must logical zero while logical one. Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset reading array data power-up.
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Command Definitions table). addition, following hardware data protection measures prevent accidental erasure pro-
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COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Command Definitions table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer appropriate timing diagrams Characteristics" section. however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return reading array data (also applies autoselect during Erase Suspend). goes high during program erase operation, writing reset command returns device reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer devices codes, determine whether sector protected. Command Definitions table shows address data requirements. This method alternative that shown Autoselect Codes (High Voltage Method) table, which intended PROM programmers requires address autoselect command sequence initiated writing unlock cycles, followed autoselect command. device then enters autoselect mode, system read address number times, without initiating another command sequence. read cycle address XX00h retrieves manufacturer code. read cycle address XX01h returns device code. read cycle containing sector address (SA) address returns that sector protected, unprotected. Refer Sector Address tables valid sector addresses. system must write reset command exit autoselect mode return reading array data.
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. device also ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, device enters Erase Suspend mode. system read array data using standard read timings, except that reads address within erase-suspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. "Erase Suspend/Erase Resume Commands" more information this mode. system must issue reset command re-enable device reading array data goes high, while autoselect mode. "Reset Command" section, next. also "Requirements Reading Array Data" "Device Operations" section more information. Read Operations table provides read parameters, Read Operation Timings diagram shows timing diagram.
Byte Program Command Sequence
Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verify programmed cell margin. Command Definitions take shows address data requirements byte program command sequence. When Embedded Program algorithm complete, device then returns reading array data addresses longer latched. system determine status program operation using DQ6. "Write Operation Status" information these status bits.
Reset Command
Writing reset command device resets device reading array data. Address bits don't care this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets device reading array data. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets device reading array data (also applies programming Erase Suspend mode). Once programming begins, July 2005
Am29F040B
commands written device during Embedded Program Algorithm ignored. Programming allowed sequence across sector boundaries. cannot programmed from back "1". Attempting halt operation "1", cause Data# Polling algorithm indicate operation successful. However, succeeding read shows that data still "0". Only erase operations convert "1".
rithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Command Definitions table shows address data requirements chip erase command sequence. commands written chip during Embedded Erase algorithm ignored. system determine status erase operation using DQ7, DQ6, DQ2. "Write Operation Status" information these status bits. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. Figure illustrates algorithm erase operation. Erase Program Operations tables Characteristics" parameters, Chip/ Sector Erase Operation Timings timing waveforms.
START
Write Program Command Sequence
Sector Erase Command Sequence
Data Poll from System
Embedded Program algorithm progress
Verify Data?
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed address sector erased, sector erase command. Command Definitions table shows address data requirements sector erase command sequence. device does require system preprogram memory prior erase. Embedded Erase algorithm automatically programs verifies sector zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out begins. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise last address command might accepted, erasure begin. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. time between additional sector erase commands assumed less than system need monitor DQ3. command other than Sector Erase Erase Suspend during time-out period resets device reading array data. system must rewrite command sequence additional sector addresses commands.
Increment Address
Last Address?
Programming Completed
Note: appropriate Command Definitions table program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase six-bus-cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algo-
Am29F040B
July 2005
system monitor determine sector erase timer timed out. (See "DQ3: Sector Erase Timer" section.) time-out begins from rising edge final pulse command sequence. Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2. Refer "Write Operation Status" information these status bits. Figure illustrates algorithm erase operation. Refer Erase/Program Operations tables Characteristics" section parameters, Sector Erase Operations Timing diagram timing waveforms.
non-suspended sectors. system determine status program operation using status bits, just standard program operation. Operation Status" more information. system also write autoselect command sequence when device Erase Suspend mode. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. "Autoselect Command Sequence" more information. system must write Erase Resume command (address bits "don't care") exit erase suspend mode continue sector erase operation. Further writes Resume command ignored. Another Erase Suspend command written after device resumed erasing.
Erase Suspend/Erase Resume Commands
Erase Suspend command allows system interrupt sector erase operation then read data from, program data sector selected erasure. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. Writing Erase Suspend command during Sector Erase time-out immediately terminates time-out period suspends erase operation. Addresses "don't-cares" when writing Erase Suspend command. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. After erase operation been suspended, system read array data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Normal read write timings command definitions apply. Reading address within erase-suspended sectors produces status data DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. "Write Operation Status" information these status bits. After erase-suspended program operation complete, system once again read array data within
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: appropriate Command Definitions table erase command sequence. "DQ3: Sector Erase Timer" more information.
Figure
Erase Operation
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Am29F040B
Command Definitions
Table
Cycles
Command Sequence (Note Read (Note Reset (Note Manufacturer Autoselect (Note Device Sector Protect Verify (Note Program Chip Erase Sector Erase Erase Suspend (Note Erase Resume (Note
Am29F040B Command Definitions
Cycles (Notes 2-4)
First Addr Data
Second Addr Data
Third Addr Data
Fourth Addr Data
Fifth Addr Data
Sixth Addr Data
Legend: Don't care Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later. Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A18-A16 select unique sector.
Notes:
Table description operations. values hexadecimal. Except when reading array autoselect data, cycles write operations. Address bits A18-A11 don't cares unlock command cycles, unless required. unlock command cycles required when reading array data. Reset command required return reading array data when device autoselect mode, goes high (while device providing status data). fourth cycle autoselect command sequence read cycle. data unprotected sector protected sector.See "Autoselect Command Sequence" more information. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation. Erase Resume command valid only during Erase Suspend mode.
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WRITE OPERATION STATUS
device provides several bits determine status write operation: DQ2, DQ3, DQ5, DQ6, DQ7. Table following subsections describe functions these bits. each offer method determining whether program erase operation complete progress. These three bits discussed first. rithms) figure Characteristics" section illustrates this. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Algorithm progress completed, whether device Erase Suspend. Data# Polling valid after rising edge final pulse program erase command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then device returns reading array data. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, device enters Erase Suspend mode, Data# Polling produces DQ7. This analogous complement/true datum output described Embedded Program algorithm: erase function changes bits sector "1"; prior this, device outputs "complement," "0." system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then device returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. When system detects changed from complement true data, read valid data DQ7-DQ0 following read cycles. This because change asynchronou with DQ0-DQ6 while Output Enable (OE#) asserted low. Data# Polling Timings (During Embedded Algo-
START
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address address within sector selected erasure. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure
Data# Polling Algorithm
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Am29F040B
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. (The system either control read cycles.) When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erasesuspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection "DQ7: Data# Polling"). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete. Write Operation Status table shows outputs Toggle DQ6. Refer Figure toggle algorithm, Toggle Timings figure Characteristics" section timing diagram. figure shows differences between graphical form. also subsection "DQ2: Toggle II".
sure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also "DQ6: Toggle subsection. Refer Toggle Timings figure toggle timing diagram. figure shows differences between graphical form.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ7-DQ0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ7-DQ0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device complete operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected era-
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1." This failure condition that indicates program erase cycle successfully completed. July 2005
Am29F040B
failure condition appear system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when operation exceeded timing limits, produces "1." Under both these conditions, system must issue reset command return device reading array data.
START
Read DQ7-DQ0
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erase operation begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire timeout also applies after each additional sector erase command. When time-out complete, switches from "1." system ignore system guarantee that time between additional sector erase commands always less than also "Sector Erase Command Sequence" section. After sector erase command sequence written, system should read status (Data# Polling) (Toggle ensure device accepted command sequence, then read DQ3. "1", internally controlled erase cycle begun; further commands (other than Erase Suspend) ignored until erase operation complete. "0", device accepts additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows outputs DQ3.
Read DQ7-DQ0
(Note
Toggle Toggle?
Read DQ7-DQ0 (Notes Twice
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Notes: Read toggle twice determine whether toggling. text. Recheck toggle because stop toggling changes "1". text.
Figure
Toggle Algorithm
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Am29F040B
Table
Operation Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Suspend Reading within Non-Erase Suspended Sector Mode Erase-Suspend-Program Reading within Erase Suspended Sector
Write Operation Status
Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data
(Note DQ7# Data DQ7#
Notes: require valid address when reading status information. Refer appropriate subsection further details. switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. "DQ5: Exceeded Timing Limits" more information.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +125°C Ambient Temperature with Power Applied. -55°C +125°C Voltage with Respect Ground (Note -2.0 (Note -2.0 12.5 other pins (Note -2.0 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs undershoot -2.0 periods Figure Maximum voltage input pins During voltage transitions, input pins overshoot periods Figure Minimum input voltage -0.5 During voltage transitions, undershoot -2.0 periods Figure Maximum input voltage 12.5 which overshoot 13.5 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure device absolute maximum rating conditions extended periods affect device reliability. +2.0 +0.5 +0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) +70°C Industrial Devices Ambient Temperature (TA) -40°C +85°C Extended Devices Ambient Temperature (TA) -55°C +125°C Supply Voltages devices .+4.75 +5.25
devices +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
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Am29F040B
CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VLKO Parameter Description Input Load Current Input Load Current Output Leakage Current Test Description VCC, Max, 12.5 VOUT VCC, -0.5 5.25 -2.5 10.5 ±1.0 ±1.0 12.5 0.45 Unit
Active Read Current (Notes VIL, Active Write (Program/Erase) Current (Notes Standby Current (Note Input Level Input High Level Voltage Autoselect Sector Protect Output Voltage Output High Voltage Lock-Out Voltage VIL,
CMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VOH1 VOH2 VLKO Lock-out Voltage Parameter Description Input Load Current Input Load Current Output Leakage Current Active Read Current (Notes Active Program/Erase Current (Notes Standby Current (Notes Input Level Input High Level Voltage Autoselect Sector Protect Output Voltage Output High Voltage 5.25 12.0 -2.5 -100 0.85 -0.4 Test Description VCC, Max, 12.5 VOUT VCC, VIL, VIL, -0.5 10.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes Characteristics (both tables): current listed includes both operating current frequency dependent component MHz). frequency component typically less than mA/MHz, with VIH. Maximum specifications tested with VCCmax. active while Embedded Algorithm (program erase) progress. 100% tested. CMOS mode only, ICC3 extended temperatures +85°C).
Am29F040B
July 2005
TEST CONDITIONS
Table
Test Condition
Test Specifications
others Unit gate 0.0-3.0 0.45-2.4 0.8, 0.8,
Device Under Test
Output Load Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels
Note: Diodes IN3064 equivalent
Figure
Test Setup
Output timing measurement reference levels
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
July 2005
Am29F040B
CHARACTERISTICS Read Only Operations
Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tACC tOEH Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Read Output Enable Hold Time (Note Toggle Data# Polling VIL, Test Setup Speed Options (Note -120 -150 Unit
tEHQZ tGHQZ tAXQX
Chip Enable Output High (Notes Output Enable Output High (Notes Output Hold Time from Addresses, OE#, Whichever Occurs First
Notes: Figure Table test conditions. Output driver disable time. 100% tested.
Addresses tOEH HIGH Outputs Output Valid HIGH Addresses Stable tACC
Figure
Read Operation Timings
Am29F040B
July 2005
CHARACTERISTICS Erase Program Operations
Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tWPH tWHWH1 tWHWH2 tVCS Notes: 100% tested. "Erase Programming Performance" section more information. Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recover Time Before Write (OE# high low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note Sector Erase Operation (Note Time (Note Speed Options -120 -150 Unit
July 2005
Am29F040B
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data tVCS
Note: program address, program data, DOUT true data program address.
Read Status Data (last cycles)
tWHWH1
tWPH Status DOUT
Figure
Program Operation Timings
Erase Command Sequence (last cycles) Addresses 2AAh
555h chip erase
Read Status Data
tWPH
tWHWH2
Data
Chip Erase Progress Complete
tVCS
Note: Sector Address. Valid Address reading status data.
Figure
Chip/Sector Erase Operation Timings
Am29F040B
July 2005
CHARACTERISTICS
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle
Figure
Data# Polling Timings (During Embedded Algorithms)
Addresses tACC tOEH DQ6/DQ2
High
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Toggle Timings (During Embedded Algorithms)
July 2005
Am29F040B
CHARACTERISTICS
Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
toggle with
Note: Both toggle with CE#. text section "Write Operation Status" more information.
Figure
Am29F040B
July 2005
CHARACTERISTICS Erase Program Operations
Alternate Controlled Writes
Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note Sector Erase Operation (Note Speed Options -120 -150 Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
July 2005
Am29F040B
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
tBUSY
DQ7#
DOUT
Notes: Program Address, Program Data, Sector Address, DQ7# Complement Data Input, DOUT Array Data. Figure indicates last cycles command sequence.
Figure
Alternate Controlled Write Operation Timings
Am29F040B
July 2005
ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note (Note (Note 10.8 Unit Excludes programming prior erasure (Note Excludes system-level overhead (Note Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, (4.75 -55), 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum byte program time listed. maximum byte program time given exceeded, only then does device section further information. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute four-bus-cycle command sequence programming. Table further information command definitions. device guaranteed minimum erase program cycle endurance 1,000,000 cycles. Comments
LATCHUP CHARACTERISTICS
Input Voltage with respect pins Current Includes pins except VCC. Test conditions: time. -1.0 -100 +100
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
July 2005
Am29F040B
PLCC PDIP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
Am29F040B
July 2005
PHYSICAL DIMENSIONS 032-32-Pin Plastic
10/99
July 2005
Am29F040B
PHYSICAL DIMENSIONS (continued) 032-32-Pin Plastic Leaded Chip Carrier
10/99
Am29F040B
July 2005
PHYSICAL DIMENSIONS (continued) 032-32-Pin Standard Thin Small Package
10/99
July 2005
Am29F040B
PHYSICAL DIMENSIONS (continued) TSR032-32-Pin Reversed Thin Small Outline Package
10/99
Am29F040B
July 2005
REVISION SUMMARY Revision (May 1997)
Initial release. ICC3: Deleted VCCMax.
Revision (February 1999)
Command Definitions Command Definitions table: Deleted "XX" from fourth cycle data column Sector Protect Verify command.
Revision (January 1998)
Global Formatted consistency with other volt-only data sheets.
Revision (January 1998)
Characteristics, Erase Program Operations Added Note references tWHWH1. Corrected parameter symbol Set-up Time specification minimum. Deleted last table.
Revision (May 1999)
Test Specifications Table Corrected input output measurement entries "All others" column.
Revision (November 1999)
Characteristics-Figure Program Operations Timing Figure Chip/Sector Erase Operations Deleted tGHWL changed waveform start high. Physical Dimensions Replaced figures with more detailed illustrations.
Revision (April 1998)
Distinctive Characteristics Changed minimum 100K write/erase cycles guaranteed 1,000,000. Ordering Information Added extended temperature availability speed options. Characteristics Erase Program Operations; Erase Program Operations Alternate Controlled Writes: Corrected These parameters 100% tested. Corrected note reference tVCS. This parameter 100% tested. Erase Programming Performance Changed minimum 100K program erase cycles guaranteed 1,000,000.
Revision (November 2000)
Added table contents. Ordering Information Deleted burn-in option.
Revision (October 2004)
Added PB-Free option Standard Ordering Matrix. Updated Valid Combinations
Revision (January 1999)
Global Updated CS39S process technology.
Revision (July 2005)
Ordering Information valid combinations list, added following: Pb-free options speed options; Pb-free options -90, -120, -150 speed options.
Distinctive Characteristics
Added 20-year data retention bullet. Characteristics-TTL/NMOS Compatible VOH: Changed parameter description "Output High Voltage" from Output High Level". Characteristics-TTL/NMOS Compatible CMOS Compatible ICC1, ICC2, ICC3: Added Note "Maximum specifications tested with VCCmax".
July 2005
Am29F040B
Colophon products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated that includes fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), where chance failure intolerable (i.e., submersible repeater artificial satellite). Please note that Spansion will liable and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, Export Administration Regulations applicable laws other country, prior authorization respective government entity will required export those products. Trademarks contents this document subject change without notice. This document contain information Spansion product under development Spansion LLC. Spansion reserves right change discontinue work product without notice. information this document provided without warranty guarantee kind accuracy, completeness, operability, fitness particular purpose, merchantability, non-infringement third-party rights, other warranty, express, implied, statutory. Spansion assumes liability damages kind arising information this document. Copyright ©2004-2005 Spansion LLC. rights reserved. Spansion, Spansion logo, MirrorBit trademarks Spansion LLC. Other company product names used this publication identification purposes only trademarks their respective companies
Am29F040B
July 2005

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