Serial E2PROM with Precision Low-VCC Lockout Circuit Volt Systems
|
|
|
Top Searches for this datasheet
S24VP02
Serial E2PROM with Precision Low-VCC Lockout Circuit Volt Systems
FEATURES Voltage Precision Low-VCC Write Lockout Write Operations Inhibited When Falls below VLOCK 3Volt 5Volt System Versions VLOCK 2.6V+.1V/-.05V VLOCK 4.25V +.25V/-0.0V VLOCK 4.50 +.25V/-0.0V 100% Compatible with Industry Standard I2CDevices Bi-directional data transfer protocol Standard 100kHz 400kHz Transfer Rates 16-Byte Page-Write Mode Minimizes total write time byte 1,000,000 Program/Erase Cycles Year Data Retention Commercial Industrial Temperature Range
OVERVIEW S24VP02 2K-bit serial E2PROM memory integrated with precision sense circuit. sense circuit will disable write operations whenever falls below VLOCK voltage. fabricated using SUMMIT's advanced CMOS E2PROM technology suitable both volt systems. S24VP02 internally organized features serial interface software protocol allowing operation simple two-wire bus. DESCRIPTIONS Serial Clock (SCL) input used clock data into device. WRITE mode, data must remain stable while HIGH. READ mode, data clocked falling edge SCL.
BLOCK DIAGRAM
5KHz Oscillator
RESET PULSE GENERATOR
1.26V
VTRIP
RESET CONTROL
MODE DECODE
DATA
ADDRESS DECODER
WRITE CONTROL
E2PROM MEMORY ARRAY
2007 ILL2
SUMMIT
Orchard City Drive, Suite
Campbell, 95008
Telephone 408-378-6461
408-378-6586
www.summitmicro.com
SUMMIT MICROELECTRONICS, Inc. 1998 2007 5/15/98
Characteristics subject change without notice
S24VP02
CONFIGURATIONS
Plastic Dual-in-line Package
ENDURANCE DATA RETENTION S24VP02 designed applications requiring 1,000,000 erase/write cycles unlimited read cycles. provides years secure data retention, with without power applied, after execution 1,000,000 erase/write cycles. DEVICE OPERATION APPLICATIONS S24VP02 designed specifically applications where integrity stored data paramount. recent years, operating voltage range serial E2PROMs widened, most semiconductor manufacturers have arbitrarily eliminated their sense circuits. S24VP02 will protect your data guaranteeing write lockout below selected Lockout voltage. Lockout S24VP02 on-board precision sense circuit. Whenever below VLOCK, S24VP02 will disable internal write circuitry. lockout circuit will ensure higher level data integrity than expected from industry standard devices that have either very loose specification lockout specification. During power-on sequence writes will inhibited below VLOCK level will continue held write inhibit state approximately 200ms after reaches, then stays above VLOCK. 200ms delay provides buffer space microcontroller complete power-on initialization routines (reading while still protecting against inadvertent writes. During power-down sequence initiation writes will inhibited whenever falls below VLOCK. This will guard against system's microcontroller performing inadvertent write within `danger zone'. (see AN001) CHARACTERISTICS General Description designed two-way, two-line serial communication between different integrated circuits. lines are: serial data line (SDA), serial clock line (SCL). line must connected positive supply pull-up resistor, located somewhere (See Figure Data transfer between devices initiated with START condition only when HIGH (bus busy).
JEDEC Small Outline Package
2007 ILL1
NAMES Address Inputs Serial Data Serial Clock Input Don't Care Ground Supply Voltage
Serial Data (SDA) bidirectional used transfer data into device. Data change only when LOW, except START STOP conditions. open-drain output wireORed with number open-drain open-collector outputs. Address Inputs (A0, Device Address Inputs These inputs unused S24VP02; however, ensure proper operation they should left unconnected tied ground. They should tied high.
2007 5/15/97
S24VP02
Master Transmitter/ Receiver Slave Receiver Slave Transmitter/ Receiver
RESET
Master Transmitter
Master Transmitter/ Receiver
(24VP02)
(µC/
2007
FIGURE TYPICAL SYSTEM CONFIGURATION
Data must remain stable while clock HIGH.
Change data allowed
Data must remain stable while clock HIGH.
tHD:DAT tSU:DAT tHD:DAT
2007 ILL4
FIGURE INPUT DATA PROTOCOL
START Condition STOP Condition
2007 ILL5
FIGURE START STOP CONDITIONS
2007 5/15/98
S24VP02
from Master Data Output from Transmitter Data Output from Receiver Start Condition
ACKnowledge
2007 ILL6
FIGURE ACKNOWLEDGE RESPONSE FROM RECEIVER
Input Data Protocol data transferred during each clock pulse. data line must remain stable during clock HIGH time, because changes data line while HIGH will interpreted start stop condition (See Figure START STOP Conditions When both data clock lines HIGH, said busy. HIGH-to-LOW transition data line, while clock HIGH, defined "START" condition. LOW-to-HIGH transition data line, while clock HIGH, defined "STOP" condition (See Figure DEVICE OPERATION S24VP02 2,048-bit serial E2PROM. device supports bidirectional data transmission protocol. protocol defines device that sends data onto "transmitter" device which receives data "receiver." device controlling data transmission called "master" controlled device called "slave." cases, S24VP02 will "slave" device, since never initiates data transfers. Acknowledge (ACK) Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line ACKnowledge that received eight bits data (See Figure S24VP02 will respond with ACKnowledge after recognition START condition slave address byte. both device write operation selected, S24VP02 will respond with ACKnowledge after receipt each subsequent 8-bit word.
2007 5/15/97
READ mode, S24VP02 transmits eight bits data, then releases line, monitors line ACKnowledge signal. ACKnowledge detected, STOP condition generated master, S24VP02 will continue transmit data. ACKnowledge detected, S24VP02 will terminate further data transmissions awaits STOP condition before returning standby power mode. Device Addressing Following start condition master must output address slave accessing. most significant four bits slave address device type identifier (see figure S24VP02 this fixed 1010[B]. next three bits don't care. S24VP02 will respond commands device 1010. Read/Write last data stream defines operation performed. When "1," read operation selected; when "0," write operation selected.
DEVICE IDENTIFIER
HIGH ORDER WORD ADDRESS
2007 ILL7
FIGURE SLAVE ADDRESS BYTE
S24VP02
WRITE OPERATIONS S24VP02 allows types write operations: byte write page write. byte write operation writes single byte during nonvolatile write period (tWR). page write operation allows bytes same page written during tWR. Byte WRITE After slave address sent identify slave device, specify high order word address read write operation), second byte transmitted which contains addresses words array. Upon receipt word address, S24VP02 responds with ACKnowledge. After receiving next byte data, again responds with ACKnowledge. master then terminates transfer generating STOP condition, which time S24VP02 begins internal write cycle. While internal write cycle progress, S24VP02 inputs disabled, device will respond requests from master. Refer Figure address, ACKnowledge data transfer sequence. Page WRITE S24VP02 capable 16-byte page write operation. initiated same manner byte-write operation, instead terminating write cycle after first data word, master transmit more bytes data. After receipt each byte, S24VP02 will respond with ACKnowledge. S24VP02 automatically increments address subsequent data words. After receipt each word, order address bits internally incremented one. high order five bits address byte remain constant. Should master transmit more than bytes, prior generating STOP condition, address counter will "roll over," previously written data will overwritten. with byte-write operation, inputs disabled during internal write cycle. Refer Figure address, ACKnowledge data transfer sequence.
Acknowledges Transmitted from 24VP02 Master Receiver
single byte-write only, Stop issued here.
Acknowledges Transmitted from 24VP02 Master Receiver
Activity
1010
Word Address
Data Byte
Data Byte
Data Byte n+15
Device S2,S1,S0 Type Address Read/Write Write
Slave Address
Master Sends Read Request Slave Master Writes Word Address Slave Master Writes Data Slave Master Writes Data Slave Master Writes Data Slave
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver Slave Transmitter Master Receiver
2007 ILL8
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Shading Denotes 24VP02 Output Active
FIGURE PAGE/BYTE WRITE MODE
2007 5/15/98
S24VP02
Acknowledge Polling When S24VP02 performing internal WRITE operation, will ignore START conditions. Since device will only return acknowledge after accepts START, part continuously queried until acknowledge issued, indicating that internal WRITE cycle complete. poll device, give START condition, followed slave address WRITE operation (See Figure
Internal WRITE Cycle Progress; Begin Polling
READ OPERATIONS Read operations initiated with identification field "1." There four different read options: Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read
Issue Start
Issue Slave Address
Issue Stop
Current Address Byte Read S24VP02 contains internal address counter which maintains address last word accessed, incremented one. last address accessed (either read write) address location next read operation would access data from address location increment current address pointer. When S24VP02 receives slave address field with "1," issues acknowledge transmits 8-bit word stored address location n+1. current address byte read operation only accesses single byte data. master does acknowledge transfer, does generate stop condition. this point, S24VP02 discontinues data transmission. Figure address acknowledge data transfer sequence.
Returned?
(Internal WRITE Cycle completed) Next operation WRITE? Issue Byte Address Issue Stop
Proceed with WRITE
Await Next Command
2007 ILL9
FIGURE ACKNOWLEDGE POLLING
Activity
Data Byte
Device Type S2,S1,S0 Address Read/Write Read
Slave Address
Master sends Read request Slave
Lack (low) from Master determines last data byte read Slave sends Data Master Slave Transmitter Master Receiver
Master Transmitter Slave Receiver
Shading Denotes 24VP02 Output Active
2007
FIGURE CURRENT ADDRESS BYTE READ MODE
2007 5/15/97
S24VP02
Random Address Byte Read Random address read operations allow master access memory location random fashion. This operation involves two-step process. First, master issues write command which includes start condition slave address field (with WRITE) followed address word read. This procedure sets internal address counter S24VP02 desired address. After word address acknowledge received master, master immediately reissues start condition followed another slave address field with READ. S24VP02 will respond with acknowledge then transmit 8-data bits stored addressed location. this point, master does acknowledge transmission does generate stop condition. S24VP02 discontinues data transmission reverts standby power mode. Figure address, acknowledge data transfer sequence.
Activity
Word Address
Data Byte
Device S2,S1,S0 Type Address Read/Write Write
Device S2,S1,S0 Type Address Read/Write Read
Slave Address
Master sends Read request Slave Master Writes Word Address Slave
Slave Address
Master Requests Data from Slave
Lack (low) from Master determines last data byte read
Slave sends Data Master
Master Transmitter Slave Receiver Shading Denotes 24VP02 Output Active
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
2007 ILL11
FIGURE RANDOM ADDRESS BYTE READ MODE
2007 5/15/98
S24VP02
Sequential READ Sequential READs initiated either current address READ random access READ. first word transmitted with other byte read modes (current address byte READ random address byte READ); however, master responds with ACKnowledge, indicating that requires additional data from S24VP02. S24VP02 continues output data each ACKnowledge received. master terminates sequential READ operation responding with ACKnowledge, issues STOP conditions. During sequential read operation, internal address counter automatically incremented with each acknowledge signal. read operations, address bits incremented, allowing entire array read using single read command. After count last memory address, address counter will `roll-over' memory will continue output data. Figure address, acknowledge data transfer sequence.
Acknowledges from 24VP02
Acknowledge from Master Receiver
Lack Acknowledge from Master Receiver
Activity
Device Type Address
Word Address
First Data Byte
Last Data Byte
S2,S1,S0
Read/Write Write
Device Type S2,S1,S0 Address Read/Write
Read
Slave Address
Master sends Read request Slave Master Writes Word Address Slave
Slave Address
Master Requests Data from Slave Slave sends Data Master
Lack (low) determines last data byte read
Slave sends Data Master
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver
Master Transmitter Slave Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Slave Transmitter Master Receiver
Master Transmitter Slave Receiver
2007
Shading Denotes 24VP02 Output Active FIGURE SEQUENTIAL READ OPERATION (starting with Random Address READ)
2007 5/15/97
S24VP02
ABSOLUTE MAXIMUM RATINGS Temperature Under Bias -40°C +85°C Storage Temperature -65°C +125°C Soldering Temperature (less than seconds) 300°C Supply Voltage 6.5V Voltage -0.3V VCC+0.3V Voltage (JEDEC method) 2,000V
NOTE: These STRESS ratings only. Appropriate conditions operating these devices given elsewhere this specification. Stresses beyond those listed here permanently damage part. Prolonged exposure maximum ratings affect device reliability.
ELECTRICAL CHARACTERISTICS S24VP02, -40°C +85°C, S24VP02-3, -40°C +85°C, 2.7V 5.5V
Symbol Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Voltage Input High Voltage Output Voltage Conditions CMOS Levels 100KHz Open other inputs other inputs VOUT SCL, SDA, RESET SCL, 0.7xVCC =5.5V =3.3V =5.5V =3.3V 0.3xVCC Units
2007
ELECTRICAL CHARACTERISTICS S24VP02, -40°C +85°C, S24VP02-3, -40°C +85°C, 2.7V 5.5V
Symbol Parameter Clock Frequency Clock Period Clock High Period Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Output Data Hold Time Rise Time Fall Time Data Setup Time Data Hold Time Noise Spike Width SCL, Inputs Write Cycle Time Noise Suppression Time Constant Data Valid Data Change Before Transmission Conditions
2.7V 4.5V 1000
4.5V 5.5V Units
fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT
2007
2007 5/15/98
S24VP02
CAPACITANCE 25°C, 100KHz
Symbol COUT Parameter Input Capacitance Output Capacitance Units
2007
tLOW
tSU:STO
tSU:SDA tHD:SDA tHD:DAT tSU:DAT tBUF
2007
FIGURE TIMING
VLOCK CIRCUIT ELECTRICAL CHARACTERISTICS -40°C +85°C
Symbol VLOCK tPUW tLDLY tGLITCH Parameter Write Lockout Voltage Level Power-Up Write Delay Delay VLOCKOUT Glitch Filter 2.55
S24VP02-2.7 2.70 4.25
S24VP02-A 4.50
S24VP02-B 4.50 4.75 Unit
2007
2007 5/15/97
S24VP02
tGLITCH
VLOCK
tPUW
tLDLY
tPUW
tLDLY
Internal Action
VLOCKOUT
VLOCKOUT
VLOCKOUT
2007
FIGURE VLOCK OUTPUT TIMING
SOIC (Type Package JEDEC (150 body width)
.050 (1.27) TYP. .050 (1.270) TYP. Places
.157 (4.00) .150 (3.80)
.275 (6.99) TYP.
.196 (5.00) .189 (4.80)
.030 (.762) TYP. Places
FOOTPRINT
.061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25)
.0192 (.49) .0138 (.35)
.0098 (.25) .004 (.127) (1.27) TYP.
.035 (.90) .016 (.40)
.244 (6.20) .228 (5.80)
JEDEC SOIC ILL.2
2007 5/15/98
S24VP02
PDIP (Type Package
.375 (9.525)
INDICATOR
.250 (6.350) .300 (7.620)
.070 (1.778) .0375 (0.952) .015 (.381) Min. SEATING PLANE .130 (3.302) .060 .005 (1.524) .127 TYP. .100 (2.54) TYP. .130 (3.302) .018 (.457) TYP.
5°-7°TYP. PLCS) 0°-15°
.350 (8.89)
.009 .002 (.229 .051)
PDIP/P ILL.3
ORDERING INFORMATION
S24VP02
-2.7
Tape Reel Option 500/reel TE13 2000/reel Operating Voltage Range 4.5V 5.5V VLOCK Min. 4.25V 4.5V 5.5V VLOCK Min. 4.50V 2.7V 5.5V VLOCK Min. 2.55V
Base Part Number
Package Lead PDIP Lead 150mil SOIC
Operating Temperature Range Blank +70°C -40°C +85°C
2007 ILL15
NOTICE SUMMIT Microelectronics, Inc. reserves right make changes products contained this publication order improve design, performance reliability. SUMMIT Microelectronics, Inc. assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained herein reflect representative operating parameters, vary depending upon user's specific application. While information this publication been carefully checked, SUMMIT Microelectronics, Inc. shall liable damages arising result error omission. SUMMIT Microelectronics, Inc. does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless SUMMIT Microelectronics, Inc. receives written assurances, satisfaction, that: risk injury damage been minimized; user assumes such risks; potential liability SUMMIT Microelectronics, Inc. adequately protected under circumstances. trademark Philips Corporation. Copyright 1998 SUMMIT Microelectronics, Inc.
2007 5/15/97
Other recent searches
SX18AC - SX18AC SX18AC Datasheet
SOP-4MF - SOP-4MF SOP-4MF Datasheet
OD-880WJ - OD-880WJ OD-880WJ Datasheet
LH75400 - LH75400 LH75400 Datasheet
LH30220 - LH30220 LH30220 Datasheet
FS6131-01 - FS6131-01 FS6131-01 Datasheet
CR5ACS - CR5ACS CR5ACS Datasheet
BB302C - BB302C BB302C Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
