DS80C390 Dual High-Speed Microprocessor FEATURES 80C52 compa

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DS80C390 Dual High-Speed Microprocessor FEATURES 80C52 compa

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DS80C390 Dual High-Speed Microprocessor
FEATURES
80C52 compatible 8051 instruction-set compatible Four 8-bit ports Three 16-bit timer/counters bytes scratchpad High-Speed Architecture clocks/machine cycle (8051=12) Runs clock rates Frequency multiplier reduces Single-cycle instruction 16/32-bit math coprocessor internal SRAM usable program/data/stack memory Enhanced memory architecture Addresses external Defaults true 8051 memory compatibility User-enabled 22-bit program/data counter 16-Bit/22-bit paged/22-bit contiguous modes User-selectable multiplexed nonmultiplexed memory interface Optional stack pointer full-function 2.0B controllers message centers controller Standard 11-bit extended 29-bit identification modes Supports DeviceNet, SDS, higher layer protocols Disables transmitter during autobaud SIESTA power mode
full-duplex hardware serial ports Programmable IrDA clock High integration controller includes Power-fail reset Early-warning power-fail interrupt Programmable watchdog timer Oscillator-fail detection total interrupt sources with external Available 64-pin QFP, 68-pin PLCC
ASSIGNMENT
DS80C390
64-Pin
DS80C390
68-Pin PLCC
Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, click here:
110199
DS80C390
DESCRIPTION
DS80C390 fast 8051-compatible microprocessor. redesigned processor core executes 8051 instructions times faster than original same crystal speed. DS80C390 supports maximum crystal speed MHz, resulting apparent execution speeds (approximately 2.5X). optional internal frequency multiplier allows microprocessor operate full speed with reduced crystal frequency, reducing EMI. hardware math accelerator further increases speed multiply divide operations, well high-speed shift, normalization accumulate functions. DS80C390 features full-function Controller Area Network (CAN) 2.0B controllers. Status control registers distributed between SFRs bytes internal MOVX memory maximum flexibility. addition standard 11-bit 29-extended message identifiers, device supports separate 8-bit media masks media arbitration fields support higher-level protocols such DeviceNet SDS. standard 8051 resources such three timer/counters, serial port, four 8-bit ports (plus 8-bit ports dedicated memory interfacing) included DS80C390. addition includes second hardware serial port, seven additional interrupts, programmable watchdog timer, brown-out monitor, power-fail reset, programmable output clock that supports IRDA interface. device provides dual data pointers with increment/decrement features speed block data memory moves. also adjust speed MOVX data memory access from twelve machine cycles flexibility addressing external memory peripherals. device incorporates SRAM, which configured various combinations MOVX memory, program memory, optional stack memory. 22-bit program counter supports access maximum external program memory external data memory. 10-bit stack pointer addresses MOVX memory increased code efficiency. Power Management Mode (PMM) useful portable power-conscious applications. This feature allows software switch from standard machine cycle rate clocks cycle 1024 clocks cycle. example, standard operation machine cycle rate MHz. Power Management Mode same external clock speed, software select 11.7 machine cycle rate. There corresponding reduction power consumption when processor runs slower. reduction feature allows software select reduced electromagnetic interference (EMI) mode disabling signal when unneeded. device also incorporates active current control address data buses, reducing minimizing transients when interfacing external circuitry.
ORDERING INFORMATION
Part Number DS80C390-QCR DS80C390-FCR DS80C390-QNR DS80C390-FNR Package 68-pin PLCC 64-pin LQFP 68-pin PLCC 64-pin LQFP Max. Clock Speed Temperature Range +70°C +70°C -40°C +85°C -40°C +85°C
DS80C390
DS80C390 BLOCK DIAGRAM Figure
DS80C390
DESCRIPTION Table
LQFP PLCC SIGNAL NAME DESCRIPTION Digital Circuit Ground Address Latch Enable Output. When low, this outputs clock latch external address from multiplexed address/data Port This signal commonly connected latch enable external transparent latch. pulse width XTAL1 cycles period four XTAL1 cycles. When high, will toggle continuously ALEOFF cleared. forced high when device Reset condition ALEOFF while high. Program Store Enable Output. This signal chip enable external memory. PSEN provides active pulse driven high when external being accessed. External Access Enable Input. This must tied proper operation. Multiplex/Demultiplex Select Input. This selects address/data operates multiplexed demultiplexed mode. Reset Input. input contains Schmitt voltage input recognize external active high Reset inputs. also employs internal pulldown resistor allow combination wired external Reset sources. circuit required power-up, device provides this function internally. Reset Output Output. This active signal will asserted: When processor entered reset pin, During crystal warm-up period following power-on Stop mode, During watchdog timer reset cycles duration), During oscillator failure OFDE=1), Whenever VRST XTAL1, XTAL2 Crystal oscillator pins support fundamental mode, parallel resonant, crystals. XTAL1 input external clock source used place crystal. XTAL2 output crystal amplifier. AD0-7 (Port I/O. When tied low, Port multiplexed address/data bus. While high, memory address presented. While falls, port transitions bi-directional data bus. When tied high, Port functions bi-directional data bus. Port cannot modified software. reset condition Port pins high. pullup resistors needed.
PSEN
RSTOL
XTAL2, XTAL1
DS80C390
58-64,
2-8,
P1.0-P1.7
4-7, 10-13
13-16, 19-22
(P2.0) (P2.1) (P2.2) (P2.3) (P2.4) (P2.5) (P2.6) (P2.7) P3.0-P3.7
Port I/O. Port function 8-bit bi-directional port, non-multiplexed signals (when =1), alternate interface internal resources. Setting SP1EC relocates RXD1 TXD1 Port reset condition Port bits logic weak pullup. logic state also serves input mode, since external circuits writing port overdrive weak pullup. When software clears port strong pulldown activated that remains until either written port reset occurs. Writing after port been will activate strong transition driver, followed weaker sustaining pullup. Once momentary strong driver turns off, port once again becomes output (and input) high state. Port Alternate Function P1.0 External Timer/Counter P1.1 T2EX Timer/Counter Capture/Reload Trigger P1.2 RXD1 Serial Port Input P1.3 TXD1 Serial Port Output P1.4 INT2 External Interrupt (Pos. Edge Detect) P1.5 INT3 External Interrupt (Neg. Edge Detect) P1.6 INT4 External Interrupt (Pos. Edge Detect) P1.7 INT5 External Interrupt (Neg. Edge Detect) A15-A8 (Port Output. Port serves external addressing. port automatically asserts address during external access. Although Port exists, value will never appear pins (due memory access). Therefore accessing Port only useful MOVX MOVX @Ri, instructions, which Port external address MSB. Port I/O. Port functions 8-bit bi-directional port, alternate interface several resources found traditional 8051. reset condition Port bits logic weak pullup. logic state also serves input mode, since external circuits writing port overdrive weak pullup. When software clears port device activates strong pulldown that remains until either written port reset occurs. Writing after port been will activate strong transition driver, followed weaker sustaining pullup. Once momentary strong driver turns off, port once again becomes output (and input) high state. Port Alternate Function P3.0 RXD0 Serial Port Input P3.1 TXD0 Serial Port Output P3.2 INT0 External Interrupt P3.3 INT1 External Interrupt P3.4 Timer External Input P3.5 T1/XCLK Timer External Input/External Clock Output P3.6 External Data Memory Write Strobe P3.7 External Data Memory Read Strobe
DS80C390
34-27
42-37
P4.0-P4.7
21-14
31-27, 25-23
P5.0-P5.7
Port I/O. Port function 8-bit bi-directional port, source external address chip enable signals program data memory. Port pins configured memory signals P4CNT register. reset condition Port bits logic weak pullup. logic state also serves input mode, since external circuits writing port overdrive weak pullup. When software clears port device activates strong pulldown that remains until either written port reset occurs. Writing after port been will activate strong transition driver, followed weaker sustaining pullup. Once momentary strong driver turns off, port once again becomes output (and input) high state. Port Alternate Function P4.0 Program Memory Chip Enable P4.1 Program Memory Chip Enable P4.2 Program Memory Chip Enable P4.3 Program Memory Chip Enable P4.4 Program/Data Memory Address P4.5 Program/Data Memory Address P4.6 Program/Data Memory Address P4.7 Program/Data Memory Address Port I/O. Port function 8-bit bi-directional port, interface, peripheral enable signals. Setting SP1EC will relocate RXD1 TXD1 functions P5.3P5.2 described User's Guide. reset condition Port bits logic weak pullup. logic state also serves input mode, since external circuits writing port overdrive weak pullup. When software clears port device activates strong pulldown that remains until either written port reset occurs. Writing after port been will activate strong transition driver, followed weaker sustaining pullup. Once momentary strong driver turns off, port once again becomes output (and input) high state. Port Alternate Function P5.0 C0TX CAN0 Transmit Output P5.1 C0RX CAN0 Receive Input P5.2 C1RX CAN1 Receive Input (optional RXD1) P5.3 C1TX CAN1 Transmit Output (optional TXD1) P5.4 PCE0 Peripheral Chip Enable P5.5 PCE1 Peripheral Chip Enable P5.6 PCE2 Peripheral Chip Enable P5.7 PCE3 Peripheral Chip Enable Reserved. These pins reserved with future devices this family should connected.
DS80C390
80C32 COMPATIBILITY
DS80C390 CMOS 80C32-compatible microcontroller designed high performance. Every effort been made keep core device familiar 80C32 users while adding many features. Because device runs standard 8051 instruction set, general software written existing 80C32based systems will work DS80C390. primary exceptions related timing-critical issues, since high-performance core microcontroller executes instructions much faster than original. Memory interfacing performed identically standard 80C32. high-speed nature DS80C390 core will slightly change interface timing, designers advised consult timing diagrams this data sheet more information. DS80C390 provides same timer/counter resources, full duplex serial port, bytes scratchpad ports standard 80C32. Timers will default clocks machine cycle operation keep timing compatible with original 8051 systems, programmed faster clocks machine cycle desired. hardware functions accessed using Special Function Registers that overlap with standard 80C32 locations. This data sheet provides only summary overview DS80C390. Detailed descriptions available corresponding user's guide. This data sheet assumes familiarity with architecture standard 80C32. addition basic features that device, DS80C390 incorporates many features.
PERFORMANCE OVERVIEW
DS80C390's higher performance comes just from increasing clock frequency, from more efficient design. This updated core removes dummy memory cycles that present standard, clocks machine cycle 8051. DS80C390, same machine cycle takes clocks. Thus fastest instruction, machine cycle, executes times faster same crystal frequency. majority instructions DS80C390 will full speed improvement, while will execute between times faster. Regardless specific performance improvements, instructions faster than original 8051. Improvement individual programs will depend actual instructions used. Speed sensitive applications should make most instructions that times faster. However, large number improved opcodes makes dramatic speed improvements likely arbitrary combination instructions. These architecture improvements sub-micron CMOS design produce peak instruction cycle MIPs). Dual Data Pointer feature also allows user eliminate wasted instructions when moving blocks memory.
INSTRUCTION SUMMARY
instructions perform exactly same functions their 8051 counterparts. Their effect bits, flags, other status functions identical. However, timing instructions different, both absolute relative number clocks. absolute timing software loops calculated using table user's guide. However, counter/timers default traditional clocks increment. this way, timer-based events occur standard intervals with software executing higher speed. Timers optionally faster clocks increment take advantage faster processor operation. relative time DS80C390 instructions might differ from traditional 8051. example, original architecture "MOVX @DPTR" instruction "MOV direct, direct" instruction required same amount time: machine cycles oscillator cycles. DS80C390,
DS80C390
MOVX instruction takes little machine cycles oscillator cycles "MOV direct, direct" uses three machine cycles oscillator cycles. While both faster than their original counterparts, they have different execution times. This because device usually uses instruction cycle each instruction byte. Examine timing each instruction familiarity with changes. Note that machine cycle requires just clocks, provides pulse cycle. Many instructions require only cycle, some require five. Refer user's guide details individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features microcontroller. This allows device have many features same instruction 8051. When writing software feature, equate statement defines assembler compiler. This only change needed access function. DS80C390 duplicates SFRs contained standard 80C52. Table shows register addresses locations. Many standard 80C52 registers. user's guide contains full description SFRs.
SPECIAL FUNCTION REGISTER LOCATION Table
Register
DPL1 DPH1 PCON TCON TMOD CKCON EXIF P4CNT DPX1 C0RMS0 C0RMS1 SCON0 SBUF0 ACON C0TMA0 C0TMA1 P5CNT C0IR
Bit7
P4.7
Bit6
P4.6
Bit5
P4.5
Bit4
P4.4
Bit3
P4.3
Bit2
P4.2
Bit1
P4.1
Bit0
P4.0
ADDRESS
SMOD_0 GATE
SMOD0
OFDF
OFDE
GATE
STOP
IDLE
INT5/P1.7 INT4/P1.6 INT3/P1.5 INT2/P1.4 TXD1/P1.3 RXD1/P1.2 T2EX/P1.1 CKRY RGMD RGSL SBCAN P4CNT.5 P4CNT.4 P4CNT.3 P4CNT.2 P4CNT.1
T2/P1.0 P4CNT.0
SM0/FE_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0 ESP.1
RI_0 ESP.0
P2.7 P2.6 P5.7 P5.6 CAN1BA CAN0BA ERIE STIE EC96/128 INTIN7 INTIN6
P2.5 P5.5 SP1EC INTIN5
P2.4 P5.4 C1_I/O SIESTA INTIN4
P2.3 P5.3 C0_I/O CRST INTIN3
P2.2 P5.2 P5CNT.2 AUTOB INTIN2
P2.1 P5.1 P5CNT.1 ERCS INTIN1
P2.0 P5.0 P5CNT.0 SWINT INTIN0
C0TE C0RE SADDR0 SADDR1 C0M1C C0M2C C0M3C C0M4C C0M5C C0M6C C0M7C C0M8C C0M9C C0M10C SADEN0 SADEN1 C0M11C C0M12C C0M13C C0M14C C0M15C SCON1 SBUF1 STATUS MCON T2CON T2MOD RCAP2L RCAP2H MCNT0 MCNT1 C1RMS0 C1RMS1 WDCON C1TMA0 C1TMA1 C1IR C1TE C1RE MXAX
MSRDY MSRDY MSRDY MSRDY MSRDY P3.7 MSRDY MSRDY MSRDY MSRDY MSRDY
P3.6
INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ
EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ INT1 EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ
MTRQ MTRQ MTRQ MTRQ MTRQ INT0 MTRQ MTRQ MTRQ MTRQ MTRQ
ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH TXD0 ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH
DTUP DTUP DTUP DTUP DTUP RXD0 DTUP DTUP DTUP DTUP DTUP
MSRDY MSRDY MSRDY MSRDY MSRDY SM0/FE_1 IDM1
SM1_1 IDM0 EXF2
SM2_1 RCLK
INTRQ INTRQ INTRQ INTRQ INTRQ REN_1 CTCLK D13T1
EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ TB8_1 SPTA1 PDCE3 EXEN2 D13T2
MTRQ MTRQ MTRQ MTRQ MTRQ RB8_1 ALEOFF SPRA1 PDCE2
ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH TI_1 SPTA0 PDCE1 T2OE
DTUP DTUP DTUP DTUP DTUP RI_1 SPRA0 PDCE0 DCEN
IRDACK
LSHIFT
C1BPR7
C1BPR6
C0BPR7 MAS4
C0BPR6 MAS3
COD1 MAS2
COD0 MAS1
CLKOE MAS0
SMOD_1
EPFI
WDIF
WTRF
ERIE INTIN7
STIE CECE INTIN6
INTIN5
SIESTA INTIN4
CRST INTIN3
AUTOB INTIN2
ERCS INTIN1
SWINT INTIN0
CANBIE
C0IE
C1IE
EWDI
DS80C390
C1M1C C1M2C C1M3C C1M4C C1M5C C1M6C C1M7C C1M8C C1M9C C1M10C C1M11C C1M12C C1M13C C1M14C C1M15C
MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY MSRDY CANBIP MSRDY MSRDY MSRDY MSRDY MSRDY
C0IP
C1IP
INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ INTRQ PWDI INTRQ INTRQ INTRQ INTRQ INTRQ
EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ EXTRQ
MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ MTRQ
ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH ROW/TIH
DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP DTUP
DS80C390
*Shaded bits Timed Access protected.
ON-CHIP ARITHMETIC ACCELERATOR
on-chip math accelerator allows microcontroller perform 16-bit multiplication, division, shifting, normalization using dedicated hardware. Math operations performed sequentially loading three special registers. mathematical operation determined sequence which three dedicated SFRs (MA, accessed, eliminating need special step choose operation. normalize function facilitates conversion 4-byte unsigned binary integers into floating point format. following table shows operations supported math accelerator their time execution.
ARITHMETIC ACCELERATOR EXECUTION TIMES Table
Operation 32-bit/16-bit divide 16-bit/16-bit divide 16-bit/16-bit multiply 32-bit shift left/right 32-bit normalize Result 32-bit quotient, 16-bit remainder 16-bit quotient, 16-bit remainder 32-bit product 32-bit result 32-bit mantissa, exponent Execution Time tCLCL tCLCL tCLCL tCLCL tCLCL
following table demonstrates procedure perform mathematical operations using hardware math accelerator. registers must loaded read order shown proper operation, although accesses other registers performed between access registers. access registers sequence will corrupt operation, requiring software clear restart math accelerator state machine. Consult description MCNT0 details shift normalize functions operate.
DS80C390
ARITHMETIC ACCELERATOR SEQUENCING
Divide (32/16 16/16) Load with dividend LSB. Load with dividendLSB+1* Load with dividend LSB+2* Load with dividend MSB. Load with divisor LSB. Load with divisor MSB. Poll until cleared machine cycles). Read retrieve quotient MSB. Read retrieve quotient LSB+2. Read retrieve quotient LSB+1. Read retrieve quotient LSB. Read retrieve remainder MSB. Read retrieve remainder LSB. *Not performed numerator. Shift Right/Left Load with data LSB. Load with data LSB+1. Load with data LSB+2. Load with data MSB. Configure MCNT0 register required Poll until cleared. machine cycles) Read result MSB. Read result LSB+2. Read result LSB+1. Read result LSB. Multiply (16x16) Load with multiplier LSB. Load with multiplier MSB. Load with multiplicand LSB. Load with multiplicand MSB. Poll until cleared machine cycles). Read product MSB. Read product LSB+2. Read product LSB+1. Read product LSB.
Normalize Load with data LSB. Load with data LSB+1. Load with data LSB+2. Load with data MSB. Configure MCNT0 register required. Poll until cleared machine cycles). Read mantissa MSB. Read mantissa LSB+2. Read mantissa LSB+1. Read mantissa LSB. Read MCNT0.4-MCNT0.0 exponent.
40-BIT ACCUMULATOR
accelerator also incorporates automatic accumulator function, permitting implementation multiply-and-accumulate divide-and-accumulate functions without additional delay. Each time accelerator used multiply divide operation, result transparently added 40-bit accumulator. This greatly increase speed other high-level math operations. accumulator accessed time Multiply/Accumulate Status Flag (MCNT1;D2h) cleared. accumulator initialized performing five writes Multiplier Register (MC;D5h), first. 40-bit accumulator read performing five reads Multiplier Register, first.
DS80C390
MEMORY ADDRESSING
DS80C390 incorporates three internal memory areas: bytes scratchpad direct) SRAM configurable various combinations MOVX data memory, stack memory, MOVC program memory bytes reserved message centers. external memory addressed multiplexed demultiplexed 20-bit address bus/8-bit data four chip enable (active during program memory access) four peripheral enable (active during data memory access) signals. Three different addressing modes supported, selected AM1, bits ACON SFR. 16-bit address mode 16-bit address mode accesses memory similarly traditional 8051. opcode compatible with 8051 microprocessor identical byte cycle count Dallas Semiconductor High-Speed Microcontroller family. device operating this mode access program data memory. device defaults this mode following reset. 22-bit paged address mode 22-bit paged address mode retains binary code compatibility with 8051 instruction set, adds machine cycle ACALL, LCALL, RETI instructions with respect Dallas Semiconductor High-Speed Microcontroller family timing. This transparent standard 8051 compilers. Interrupt latency also increased machine cycle. this mode, interrupt vectors fetched from 0000xxh. 22-bit contiguous address mode 22-bit contiguous addressing mode uses full 22-bit program counter, modified branching instructions automatically save restore entire program counter. 22-bit branching instructions such ACALL, AJMP, LCALL, LJMP, DPTR, RETI instructions require assembler, compiler linker that specifically supports these features. DPTR lengthened cycle remains byte count compatible with standard 8051 instruction set. Internally, device uses 22-bit program counter. lowest order bits used memory addressing, with special 23rd used SRAM above memory space bootstrap loader applications. Address bits 16-23 22-bit addressing modes generated additional SFRs dependent type instruction shown below.
EXTENDED ADDRESS GENERATION: Table
MOVX instructions using DPTR MOVX instructions using DPTR1 MOVX instructions using Addressing program memory 22-bit paged mode 10-bit stack pointer mode Address bits 23-16 DPX;93h DPX1;95h MXAX;EAh AP;9Ch -Address bits 15-8 DPH;83h DPH1;85h P2;A0h -ESP;9Bh Address bits DPL;82h DPL1;84h -SP;81h
DS80C390
INTERNAL MOVX SRAM
DS80C390 contains SRAM that configured user accessible MOVX memory, program memory, optional stack memory. specific configuration locations governed Internal Data Memory Configuration bits (IDM1, IDM0) Memory Control Register (MCON;C6h). Note that when (ACON.2) set, first MOVX data memory reserved 10-bit expanded stack. Internal memory accesses will generate PSEN strobes. DS80C390 configure internal SRAM combined program data memory. This allows application software execute self-modifiable code. technique loads SRAM with bootstrap loader software, then modifies IDM1 IDM0 bits starting memory location 40000h. This allows system bootstrap loader without disturbing external memory bus, making device in-system reprogrammable Flash RAM.
INTERNAL MOVX SRAM CONFIGURATION Table
Message Memory 00F000h-00FFFFh 00EE00h-00EFFFh 00F000h-00FFFFh 401000h-4011FFh 000000h-000FFFh 00EE00h-00EFFFh 000000h-000FFFh 401000h-4011FFh 400000h-400FFFh 00EE00h-00EFFFh 400000h-400FFFh 401000h-4011FFh -00EE00h-00EFFFh -401000h-4011FFh *10-bit expanded stack available Shared Program /Data Memory mode. IDM1 IDM0 MOVX Data Memory Shared Program /Data Memory -400000h-400FFFh* 400000h-400FFFh*
EXTERNAL MEMORY ADDRESSING
enabling mapping chip enable signals done Port Control Register (P4CNT;92h) Memory Control Register (MCON; 96h); Extended Address Chip Enable Generation Table shows which chip enable address line signals active Port Following reset, device will configured with P4.7-P4.4 address lines P4.3-P4.0 configured with first program fetch being performed from 00000h with active. following tables illustrate which memory ranges controlled each chip enable function which address lines enabled.
EXTERNAL MEMORY ADDRESSING ASSIGNMENTS Table
Address/Data Multiplexed Demultiplexed
PCE3 PCE0
P4.3-P4.0 P4.3-P4.0
P5.7-P5.4 P5.7-P5.4
Addr 19-16 Addr 15-8 P4.7-P4.4 P4.7-P4.4
Addr
Data
EXTENDED ADDRESS CHIP ENABLE GENERATION Table
Port Function P4CNT.5-3 P4.7 P4.6 P4.5 P4.4 111(default) P4CNT.2-0 111(default)
Port Function P4.3 P4.2 P4.1 P4.0
DS80C390
PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table
P4CNT.5-3 111(default)
0h-7FFFh 0h-1FFFFh 0h-3FFFFh 0h-7FFFFh 0-FFFFFh
8000h-FFFFh 20000h-3FFFFh 40000h-7FFFFh 80000h-FFFFFh 100000h-1FFFFFh
10000h-17FFFh 18000h-1FFFFh 40000h-5FFFFh 60000h-7FFFFh 80000h-BFFFFh C0000h-FFFFFh 100000h-17FFFFh 180000h-1FFFFFh 200000h-2FFFFFh 300000h-3FFFFFh
DS80C390 incorporates feature allowing signals combined. This useful when incorporating modifiable code memory part bootstrap loader in-system reprogrammability. Setting PDCE3 (MCON.3-0) bits causes corresponding chip enable signal function both MOVC MOVX operations. Write access combined program data memory blocks controlled signal, read access controlled PSEN signal. This feature especially useful design achieves in-system reprogrammability external Flash memory, which single device accessed both MOVC instructions (program fetch) MOVX Write operations (updates code memory). this case, internal SRAM placed program/data configuration loaded with small bootstrap loader program stored external Flash memory. device then executes internal bootstrap loader routine modify/update program memory located external Flash memory.
STRETCH MEMORY CYCLES
DS80C390 allows user application software select number machine cycles takes execute MOVX instruction, allowing access both fast slow off-chip data memory and/or peripherals without glue logic. High-speed systems often include memory-mapped peripherals such LCDs UARTs with slow access times, necessary desirable access external devices full speed. microprocessor perform MOVX instruction little machine cycles many twelve machine cycles. Accesses internal MOVX SRAM always cycles. Note that stretch cycle settings affect external MOVX memory operations only that there slow accesses program memory other than slower crystal external clock). External MOVX timing governed selection Stretch cycles, controlled MD2-MD0 bits Clock Control Register (CKCON.2-0). Stretch zero will result two-machine cycle MOVX instruction. Stretch seven will result MOVX twelve machine cycles. Software dynamically change Stretch value depending particular memory peripheral being accessed. default Stretch cycle allows commonly available SRAMs without dramatically lengthening memory access times. Stretch cycle settings affect external MOVX timing three gradations. Changing Stretch value from adds additional clock cycle each data setup hold times. When Stretch value above selected, interface timing changes dramatically allow very slow peripherals. First, signal lengthened machine cycle. This increases address setup time into peripheral this amount. Next, address held additional machine cycle increasing address hold time this amount. signals then lengthened machine cycle. Finally, during MOVX write data held additional machine cycle, thereby increasing data hold time this amount. every Stretch value greater than setup hold times remain constant, only width read write signal increased. These three gradations reflected Electrical characteristics, where eight MOVX timing specifications represented only three timing diagrams.
DS80C390
reset default Stretch cycle results three cycle MOVX external access. Therefore, default off-chip access full speed. This convenience existing designs that utilize slower RAM. When maximum speed desired, software should select Stretch value zero. When using very slow peripherals, application software select larger Stretch value. specific timing MOVX instructions function Stretch settings provided Electrical Specifications section this data sheet. example, Table shows read write strobe widths corresponding each Stretch value.
DATA MEMORY CYCLE STRETCH VALUES Table
Pulse Width oscillator clocks) tMCS tMCS tMCS tMCS (4X/ (4X/ (4X/ (4X/ CD1:0 CD1:0 CD1:0 CD1:0 tCLCL tCLCL tCLCL 2048 tCLCL tCLCL tCLCL tCLCL 4096 tCLCL tCLCL tCLCL tCLCL 8192 tCLCL tCLCL tCLCL tCLCL 12288 tCLCL tCLCL tCLCL tCLCL 16384 tCLCL tCLCL tCLCL tCLCL 20480 tCLCL tCLCL tCLCL tCLCL 24576 tCLCL tCLCL tCLCL tCLCL 28672 tCLCL *All internal MOVX operations execute Stretch setting. Default Stretch setting external MOVX operations following reset. Stretch Cycle Count MOVX Machine Cycles
EXTENDED STACK POINTER
DS80C390 supports both traditional 8-bit extended 10-bit stack pointer that improves performance large programs written high-level languages such 10-bit stack pointer feature enabled setting Stack Address Mode bit, (ACON.2). cleared following reset, forcing device 8-bit stack located Scratchpad area. When set, device will address stack memory first internal MOVX memory. 10-bit stack pointer address generated concatenating lower bits Extended Stack Pointer (ESP;9Bh) traditional 8051 Stack Pointer (SP;81h). 10-bit stack pointer cannot enabled when SRAM mapped both program data memory.
DS80C390
ENHANCED DUAL DATA POINTERS
DS80C390 contains data pointers, DPTR0 DPTR1, designed improve performance applications that require high data throughput. Incorporating second data pointer allows software greatly speed block data (MOVX) moves using data pointer source register other destination register. DPTR0 located same address original 8051 data pointer, allowing DS80C390 execute standard 8051 code with modifications. second data pointer, DPTR1, split between DPH1 DPL1 SFRs, similar DPTR0 configuration. active data pointer selected with data pointer select (DPS.0). instructions that reference DPTR (i.e., MOVX @DPTR), will select DPTR0 SEL=0, DPTR1 SEL=1. Because bits adjacent implemented, state (and thus active data pointer) quickly toggled instruction without disturbing other bits register. Unlike standard 8051, DS80C390 ability decrement well increment data pointers without additional instructions. When DPTR instruction executed, active DPTR increments decrements according ID1, (DPS.7-6), (DPS.0) bits shown. inactive DPTR affected.
DATA POINTER AUTOINCREMENT/DECREMENT CONFIGURATION Table
Result DPTR Increment DPTR0 Decrement DPTR0 Increment DPTR1 Decrement DPTR1
Another useful feature device ability automatically switch active data pointer after DPTR-based instruction executed. This feature greatly reduce software overhead associated with data memory block moves, which toggle between source destination registers. When Toggle Select (TSL;DPS.5) (DPS.0) automatically toggled every time following DPTR related instructions executed. DPTR DPTR, #data16 MOVC @A+DPTR MOVX @DPTR MOVX @DPTR, brief example, then both data pointers updated with DPTR instructions. Assume that SEL=0, making DPTR active data pointer. first DPTR increments DPTR toggles second instruction increments DPTR1 toggles back DPTR DPTR
CLOCK CONTROL POWER MANAGEMENT
DS80C390 includes number unique features that allow flexibility selecting system clock sources operating frequencies. support inexpensive crystals while allowing full speed operation, clock multiplier included processor's clock circuit. Also, addition standard 80C32 Idle power down (Stop) modes, DS80C390 provides Power Management Mode.
DS80C390
This mode allows processor continue instruction execution, very speed significantly reduce power consumption (below even Idle mode). DS80C390 also features several enhancements Stop mode that make this extremely power mode more useful. Each these features discussed detail below.
SYSTEM CLOCK CONTROL
mentioned previously, microcontroller contains special clock control circuitry that simultaneously provides maximum timing flexibility maximum availability economy crystal selection. logical operation system clock divide control function shown Figure multiplexer, controlled CD1, (PMR.7-6), selects three sources internal system clock: Crystal oscillator external clock source (Crystal oscillator external clock source) divided (Crystal oscillator external clock source) frequency multiplied times.
SYSTEM CLOCK CONTROL DIAGRAM Figure
system clock control circuitry generates clock signals that used microcontroller. internal system clock provides timebase timers internal peripherals. system clock through divide circuit generate machine cycle clock that provides timebase operations. instructions execute five machine cycles. important note distinction between these clock signals, they sometimes confused, creating errors timing calculations. Setting CD1, enables frequency multiplier, either doubling quadrupling frequency crystal oscillator external clock source. controls multiplying factor, selecting twice four times frequency when respectively. Enabling frequency multiplier results apparent instruction execution speeds clocks. Regardless configuration frequency multiplier, system clock microcontroller never operated faster than MHz. This means that maximum crystal oscillator external clock source when using setting, when using setting. primary advantage clock multiplier that allows microcontroller slower crystals achieve same performance level. This reduces cost, slower crystals generally more available thus less expensive.
DS80C390
SYSTEM CLOCK CONFIGURATION Table
Name Frequency Multiplier (2X) Frequency Multiplier (4X) Reserved Divide-by-four (Default) Power Management Mode
Clocks/MC 1024
Max. External Frequency
system clock machine cycle rate changes machine cycle after instruction changing control bits. Note that change will affect aspects system operation, including timers baud rates. switchback feature, described later, eliminate many problems associated with Power Management Mode. Changing system clock/machine cycle clock frequency microcontroller incorporates special locking sequence ensure "glitch-free" switching internal clock signals. changes CD1, bits must pass through (divide-by-four) state. example, change from (frequency multiplier) (PMM), software must change bits following sequence: Attempts switch between invalid states will fail, leaving CD1, bits unchanged. following sequence must followed when switching frequency multiplier internal time source. This sequence only performed when device divide-by-four operation. steps must followed this order, although possible have other instructions between them. deviation from this order will cause CD1, bits remain unchanged. Switching from frequency multiplier non-multiplier mode requires steps other than changing CD1, bits. Ensure that CD1, bits RGMD (EXIF.2) Clear C(Crystal Multiplier Enable) bit. appropriate state. C(Crystal Multiplier Enable) bit. Poll CKRDY (EXIF.4), waiting until This will take approximately 65536 cycles external crystal clock source. CD1, frequency multiplier will engaged machine cycle following write these bits.
OSCILLATOR FAIL DETECT
microprocessor contains safety mechanism called on-chip Oscillator Fail Detect circuit. When enabled, this circuit causes processor held reset oscillator frequency falls below kHz. operation, this circuit complements Watchdog timer. Normally, watchdog timer initialized that will time-out will cause processor reset event that processor loses control. event crystal external oscillator failure, however, watchdog timer will function there potential processor fail uncontrolled state. oscillator fail detect circuit forces processor known state (i.e., reset) even oscillator stops. oscillator fail detect circuitry enabled when software sets enable OFDE (PCON.4) Please note that software must "Timed Access" procedure (described later) write this bit. OFDF (PCON.5) will also when circuitry detects oscillator failure, processor forced into reset state. This only cleared power fail reset software. oscillator fail detect circuitry will activated when oscillator stopped processor entering Stop mode.
DS80C390
POWER MANAGEMENT MODE (PMM)
Crystal Speed 11.0592 Machine Cycle Rate Full Operation clocks (1024 clocks machine cycle) machine cycle) 2.765 10.8 15.6 6.25 24.4 8.25 32.2 10.0 39.1 Operating Current Estimates Full Operation clocks (1024 clocks machine cycle) machine cycle) 13.1 17.2 25.7 32.8
Note that power consumption less than Idle mode. While both modes leave power-hungry internal timers running, runs clocked functions such timers rate crystal divided 1024, rather than crystal divided Even though instruction execution continues (albeit reduced speed), still consumes less power than Idle mode. result there little reason Idle mode designs.
SWITCHBACK
When enabled, Switchback feature allows serial ports interrupts automatically switch back from divide 1024 (PMM) divide (standard speed) operation. This feature makes very convenient Power Management Mode real-time applications. Software simply clock control bits clocks cycle mode exit PMM. However, microcontroller provides hardware alternatives automatic Switchback standard speed (divide operation. Switchback feature enabled setting (PMR.5) Once enabled, when selected, possible events cause automatic Switchback divide four mode. First, interrupt occurs acknowledged, system clock will revert from divide four mode. example, INT0 enabled servicing higher priority interrupt, then Switchback will occur INT0 However, INT0 enabled servicing higher priority interrupt, then activity INT0 will cause Switchback occur. Switchback also occur when enabled UART detects start indicating beginning incoming serial character when SBUF register loaded initiating serial transmission. Note that serial character's start does generate interrupt. interrupt occurs only reception complete serial word. automatic Switchback detection start allows timer hardware return divide operation (and correct baud rate) time proper serial reception transmission. with Switchback enabled serial port enabled, automatic switch divide operation occurs time receive transmit complete serial character nothing special happened.
STATUS
Status register (STATUS;C5h) provides information about interrupt serial port activity assist determining possible enter PMM. microprocessor supports three levels interrupt priority: Power-fail, High, Low. (Power-fail Priority Interrupt Status; STATUS.7), (High Priority Interrupt Status; STATUS.6), (Low Priority Interrupt Status; STATUS.5) status bits, when logic one, indicate corresponding level service.
DS80C390
Software should rely lower-priority level interrupt source remove (Switchback) when higher level service. Check current priority service level before entering PMM. current service level locks desired Switchback source, then would advisable wait until this condition clears before entering PMM. Alternately, software prevent undesired exit from intentionally entering priority interrupt service level before entering PMM. This will prevent other priority interrupts from causing Switchback. Entering during ongoing serial port transmission reception corrupt serial port activity. prevent this, hardware lockout feature ignores changes clock divisor bits while serial ports active. Serial port activity monitored Serial Port Activity bits located Status register.
IDLE MODE
Setting IDLE (PCON.0) invokes Idle mode. Idle will leave internal clocks, serial ports timers running. Power consumption drops because memory being accessed instructions being executed. Since clocks running, Idle power consumption function crystal frequency. should approximately operational power given frequency. exit Idle mode with interrupt reset. Because Power Management Mode (PMM) consumes less power than Idle mode, well leaving timers operating, Idle mode longer recommended designs, included backward software compatibility only.
STOP MODE
Setting STOP Power Control register (PCON.1) invokes Stop mode. Stop mode lowest power state (besides power off) since turns internal clocking. standard Stop mode approximately (consult Electrical Specifications section full details). processor operation ceases instruction that sets STOP bit. exit Stop mode external interrupt, enabled, reset condition. Internally generated interrupts (timer, serial port, watchdog) cannot cause exit from Stop mode because internal clocks active Stop mode.
BAND-GAP SELECT
DS80C390 provides enhancements Stop mode. described below, device provides band-gap reference determine Power-fail Interrupt Reset thresholds. band-gap reference controlled Band-Gap Select bit, (RCON.0). Setting will keep band-gap reference enabled during Stop mode. default reset condition logic which disables band-gap during Stop mode. This control reference during full power, PMM, Idle modes. With band-gap reference enabled, Power-fail reset interrupt valid means leaving Stop mode. This allows software detect compensate power supply brownout, even when Stop mode. Stop mode with band-gap enabled, will approximately compared with with band-gap disabled. user does require Power-fail Reset Interrupt while Stop mode, band-gap remain disabled. Only most power sensitive applications should disable band-gap reference Stop mode, this results uncontrolled power down condition.
RING OSCILLATOR
second enhancement Stop mode reduces power consumption allows device restart instantly when exiting Stop mode. ring oscillator internal clock that optionally provide clock source microcontroller when exiting Stop mode response interrupt.
DS80C390
During Stop mode crystal oscillator halted maximize power savings. Typically required external crystal begin oscillating again once device receives exit stimulus. ring oscillator, contrast, free-running digital oscillator that startup delay. ring oscillator feature enabled setting Ring Oscillator Select bit, RGSL (EXIF.1). enabled, microcontroller uses ring oscillator clock source exit Stop mode, resuming operation less than After 65536 oscillations external clock source (not ring oscillator), device will clear Ring Oscillator Mode bit, RGMD (EXIF.2) indicate that device switched from ring oscillator external clock source. ring oscillator runs approximately MHz, varies over temperature voltage. result, serial communication precision timing should attempted while running from ring oscillator since operating frequency precise. default state exits Stop mode without using ring oscillator.
TIMED ACCESS PROTECTION
Selected bits critical operation, making desirable protect them against accidental write operation. Timed Access procedure prevents errant processor from accidentally altering bits that would seriously affect processor operation. Timed Access procedure requires that write protected immediately preceded following instructions: 0C7h, #0AAh 0C7h, #55h Writing followed Timed Access register (location C7h), opens three-cycle window that allows software modify protected bits. instruction that seeks modify protected immediately preceded these instructions, write will ignored. protected bits are: WDCON.6 WDCON.3 WDCON.1 WDCON.0 RCON.0 ACON.2 ACON.1-0 MCON.7-6 MCON.5 MCON.3-0 C0C.3 C1C.3 P4CNT.6 P4CNT.5-0 P5CNT.2-0 COR.7 COR.6-5 COR.4-3 COR.2-1 COR.0 WDIF AM1-AM0 IDM1-IDM0 PDCE3-PDCE.0 CRST CRST SBCAN P5.7-P5.5 IRDACK C1BPR7-C1BPR6 C0BPR7-C0BPR6 COD1-COD0 CLKOE Power-On Reset Flag Watchdog Interrupt Flag Watchdog Reset Enable Reset Watchdog Timer Band-Gap Select Stack Address Mode Address Mode Select bits Internal Memory Configuration Location bits Data Memory Assignment Program/Data Chip Enables Reset Reset Single Port Configuration Control Bits Configuration Control Bits IRDA Clock Output Enable Baud Rate Pre-scale Bits Baud Rate Pre-scale Bits Clock Output Divide Clock Output Enable
DS80C390
REDUCTION
major contributors radiated noise 8051-based system toggling ALE. microcontroller allows software disable when used setting ALEOFF (PMR.2) When ALEOFF will automatically toggle during off-chip MOVX. However, will remain static when performing on-chip memory access. default state ALEOFF normally toggles frequency XTAL/4.
PERIPHERAL OVERVIEW
DS80C390 provides several most commonly needed peripheral functions microcomputerbased systems. functions include second serial port, power-fail reset, power-fail interrupt flag, programmable watchdog timer. addition, microcontroller contains Controller Area Network (CAN) modules industrial communication applications. Each these peripherals described below, more details available User's Guide.
SERIAL PORTS
microcontroller provides serial port (UART) that identical 80C52. addition includes second hardware serial port that full duplicate standard one. This second port optionally uses pins P1.2 (RXD1) P1.3 (TXD1). duplicate control functions included locations. second serial port alternately mapped P5.2 P5.3 allow both serial ports nonmultiplexed mode. Both ports operate simultaneously different baud rates even different modes. second serial port similar control registers (SCON1, SBUF1) original. serial port only Timer baud rate generation. SCON0 register provides control serial port while buffer SBUF0. registers SCON1 SBUF1 provide same functions second serial port. full description operation both serial ports found User's Guide.
WATCHDOG TIMER
Watchdog free running, programmable timer that flag, cause interrupt, and/or reset microcontroller allowed reach preselected time-out. restarted software. typical application uses watchdog timer reset source prevent software from losing control. watchdog timer initialized, selecting time-out period enabling reset and/or interrupt functions. After enabling reset function, software must then restart timer before expiration hardware will reset CPU. this code execution goes awry software does reset watchdog scheduled, processor known good state: reset. Software select four time-out values controlled bits. Time-out values precise since they function crystal frequency. When Watchdog times out, sets Watchdog Timer Reset Flag (WTRF=WDCON.2) which generates reset enabled Enable Watchdog Timer Reset (EWT=WDCON.1) bit. Both Enable Watchdog Timer Reset Reset Watchdog Timer control bits protected Timed Access circuitry. This prevents errant software from accidentally clearing disabling Watchdog. Watchdog interrupt useful systems that require reset circuit. will WDIF (Watchdog interrupt) flag clocks before setting reset flag. Software optionally enable this interrupt source, which independent watchdog reset function. interrupt common used
DS80C390
during debug process determine where watchdog reset commands must located application software. interrupt also serve convenient time-base generator wake-up processor from power saving modes. Watchdog timer controlled Clock Control (CKCON) Watchdog Control (WDCON) SFRs. CKCON.7 CKCON.6 respectively, they select Watchdog time-out period. course, (PMR.3) CD1:0 (PMR.7:6) system clock control bits also affect time-out period. Selection time-out shown below.
WATCHDOG TIME-OUT VALUES Table
WATCHDOG INTERRUPT TIME-OUT WATCHDOG RESET TIME-OUT CD1:0 WD1:0=00 WD1:0=01 WD1:0=10 WD1:0=11 WD1:0=00 WD1:0=01 WD1:0=10 WD1:0=11 215+512 218+512 221+512 224+512 +512 +512 +512 225+512 +512 +512 +512 226+512 +512 +512 +512 226+512 +512 +512 +512 234+512
table demonstrates that crystal frequency Watchdog timer capable producing time-out periods from 3.97 (217 1/33 MHz) over seconds (2.034 1/33 MHz) with default setting CD1:0 (=10). This wide variation time-out periods allows very flexible system implementation. typical initialization, user selects possible counter values determine time-out. Once counter chain completed full count, hardware will interrupt flag (WDIF=WDCON.3). Regardless whether software makes this flag, there then clocks left until reset flag (WTRF=WDCON.2) set. Software enable disable reset using Enable Watchdog Timer Reset (EWT=WDCON.1) bit.
POWER FAIL RESET
microcontroller incorporates internal precision band-gap voltage reference comparator circuit which provide power-on power-fail reset function. This circuit monitors processor's incoming power supply voltage (VCC), holds processor reset while below minimum voltage level. When power exceeds reset threshold, full power-on reset will performed. this way, this internal voltage monitoring circuitry handles both power-up power-down conditions without need additional external components. Once risen above VRST, device will automatically restart oscillator external crystal count 65,536 clock cycles before program execution begins location 0000h. This helps system maintain reliable operation only permitting processor operation when supply voltage known good state. Software determine that power-on reset occurred checking Power-On Reset flag (POR;WDCON.6). Software should clear after reading
POWER FAIL INTERRUPT
band-gap voltage reference that sets precise reset threshold also generates optional early warning Power-fail Interrupt (PFI). When enabled software, processor will vector address 0033h drops below VPFW. highest priority. enable Watchdog Control (EPFI;WDCON.5). Setting this logic will enable PFI. Application software also read flag WDCON.4. condition sets this flag independent interrupt enable must cleared software.
DS80C390
EXTERNAL RESET PINS
DS80C390 both reset input (RST) reset output RSTOL pins. RSTOL supplies active Reset when microprocessor issued Reset from either high pin, time watchdog timer, crystal oscillator fail, internally detected power-fail. timing RSTOL dependent source reset.
Reset Type/Source Power-on reset External reset Power fail Watchdog timer reset Oscillator fail detect
RSTOL Duration
65536 tCLCL described Power Cycle Timing Characteristics) 1.25 machine cycles 65536 tCLCL described Power Cycle Timing Characteristics) machine cycles 65536 tCLCL described Power Cycle Timing Characteristics)
INTERRUPTS
microcontroller provides interrupt sources with three priority levels. interrupts, with exception Power Fail interrupt, controlled series combination individual enable bits global interrupt enable (IE.7). Setting allows individual interrupts enabled. Clearing disables interrupts regardless their individual enable settings. three available priority levels low, high, highest. highest priority level reserved Power Fail Interrupt only. other interrupt priority levels have individual priority bits that when establish particular interrupt high priority. addition user-selectable priorities, each interrupt also inherent natural priority, used determine priority simultaneously occurring interrupts. available interrupt sources, their flags, their enables, their natural priority, their available priority selection bits identified following table.
INTERRUPT SUMMARY Table
NAME DESCRIPTION
INT0 INT1 SCON0 SCON1 INT2 INT3 INT4 INT5 WDTI CANBUS
Power Fail Interrupt External Interrupt Timer External Interrupt Timer from serial port Timer from serial port External Interrupt External Interrupt External Interrupt External Interrupt CAN0 Interrupt CAN1 Interrupt Watchdog Timer CAN0/1 Activity
VECTOR NATURAL PRIORITY
FLAG
PFI(WDCON.4) IE0(TCON.1)** TF0(TCON.5)* IE1(TCON.3)** TF1(TCON.7)* RI_0(SCON0.0) TI_0(SCON0.1) TF2(T2CON.7) ET2(IE.5) PT2(IP.7) RI_1(SCON1.0) ES1(IE.6) PS1(IP.6) TI_1(SCON1.1) (EXIF.4) (EIE.0) (EIP.0) (EXIF.5) (EIE.1) (EIP.1) (EXIF.6) (EIE.2) (EIP.2) (EXIF.7) (EIE.3) (EIP.3) various C0IE (EIE.6) C0IP (EIP.6) various C1IE (EIE.5) C1IP (EIP.5) WDIF (WDCON.3) EWDI (EIE.4) PWDI (EIP.4) various CANBIE (EIE.7) CANBIP (EIP.7)
PRIORITY CONTROL EPFI(WDCON.5) EX0(IE.0) PX0(IP.0) ET0(IE.1) PT0(IP.1) EX1(IE.2) PX1(IP.2) ET1(IE.3) PT1(IP.3) ES0(IE.4) PS0(IP.4)
ENABLE
Unless marked, flags must cleared application software. Cleared automatically hardware when service routine entered. edge triggered, flag cleared automatically hardware when service routine entered. level triggered, flag follows state interrupt pin.
DS80C390
CONTROLLER AREA NETWORK (CAN) MODULE
DS80C390 incorporates controllers that fully compliant with 2.0B specification. highly robust, high-performance communication protocol serial communications. Popular wide range applications including automotive, medical, heating, ventilation, industrial control, architecture allows construction sophisticated networks with minimum external hardware. controllers support 11-bit standard 29-bit extended acceptance identifiers messages, with standard byte data field, each message. Fourteen fifteen message centers programmable either transmit receive modes, with fifteenth designated FIFObuffered, receive-only message center help prevent data overruns. message centers support separate 8-bit media masks media arbitration fields incoming message verification. This feature supports higher level protocols which make first and/or second byte data part acceptance layer storing incoming messages. Each message center also programmed independently test incoming data with without global masks. Global controls status registers each unit allow microcontroller evaluate error messages, generate interrupts, locate validate data, establish timing, establish identification mask bits, verify source individual messages. Each message center individually equipped with necessary status control bits establish direction, identification mode (standard extended), data field size, data status, automatic remote frame request acknowledgment, perform masked non-masked identification acceptance testing.
COMMUNICATING WITH MODULE
microcontroller interface modules divided into groups registers. global status control bits well individual message center control/status registers located Special Function Register map. remaining registers associated with message centers (data identification, identification/arbitration masks, format data) located MOVX data space. (MCON.5) allows message centers mapped either 00EE00h-00EEFFh (CMA=0 401000h-4011FFh (CMA=1), reducing possibility memory conflict with application software. Note that setting employs special twenty-third address that only used addressing MOVX memory. internal architecture DS80C390 requires that device 22-bit addressing modes when correctly utilize twenty-third access MOVX memory. special lockout feature prevents accidental software corruption control, status mask registers while operation progress. Each processor utilizes total message centers. Each message center composed four specific areas. These include: Four arbitration registers (C0MxAR0-3 C1MxAR0-3) which store either 11-bit 29-bit arbitration value. These registers located MOVX memory map. Format Register (C0MxF C1MxF) which informs processor direction (transmit receive), number data bytes message, Identification Format (standard extended), optional Identification Mask Media Mask during message evaluation. This register located MOVX memory map. Eight data bytes storage bytes data (C0MxD0-7 C1MxD0-7) located MOVX memory map. Message Control Registers (C0MxC C1MxC) located memory fast access.
DS80C390
Each message centers identical with exception message center Message center been designed receive only center also buffered through message FIFO help prevent message loss message overrun situation. receipt third message before either first read will overwrite second message, leaving first message undisturbed. Modification registers located MOVX memory protected SWINT bits, with protecting each respective module. Consult description this User's Guide more information. Each Module contains block Control/Status/Mask registers, functionally identical message centers, plus fifteenth message center which receive only incorporates buffered FIFO. following tables describe organization message centers located MOVX space.
MOVX MESSAGE CENTERS
CONTROL/STATUS/MASK REGISTERS
Register C0MID0 C0MA0 C0MID1 C0MA1 C0BT0 C0BT1 C0SGM0 C0SGM1 C0EGM0 C0EGM1 C0EGM2 C0EGM3 C0M15M0 C0M15M1 C0M15M2 C0M15M3 MID07 M0AA7 MID17 M1AA7 SJW1 ID28 ID20 ID28 ID20 ID12 ID28 ID20 ID12 MOVX Data Address1 MID06 MID05 MID04 MID03 MID02 MID01 MID00 xxxx00h M0AA6 M0AA5 M0AA4 M0AA3 M0AA2 M0AA1 M0AA0 xxxx01h MID16 MID15 MID14 MID13 MID12 MID11 MID10 xxxx02h M1AA6 M1AA5 M1AA4 M1AA3 M1AA2 M1AA1 M1AA0 xxxx03h SJW0 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 xxxx04h TSEG26 TSEG25 TSEG24 TSEG13 TSEG12 TSEG11 TSEG10 xxxx05h ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxxx06h ID19 ID18 xxxx07h ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxxx08h ID19 ID18 ID17 ID16 ID15 ID14 ID13 xxxx09h ID11 ID10 xxxx0Ah xxxx0Bh ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxxx0Ch ID19 ID18 ID17 ID16 ID15 ID14 ID13 xxxx0Dh ID11 ID10 xxxx0Eh xxxx0Fh MESSAGE CENTER
Reserved C0M1AR0 MESSAGE ARBITRATION REGISTER C0M1AR1 MESSAGE ARBITRATION REGISTER C0M1AR2 MESSAGE ARBITRATION REGISTER C0M1AR3 MESSAGE ARBITRATION REGISTER C0M1F DTBYC3 DTBYC2 DTBYC1 DTBYC0 MEME C0M1D0-7 MESSAGE DATA BYTES Reserved xxxx10h xxxx12h xxxx13h xxxx14h xxxx15h xxxx16h xxxx17h xxxx1Fh
WTOE MDME
DS80C390
MESSAGE CENTERS 2-14
MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center
MESSAGE CENTER
Reserved C0M15AR0 MESSAGE ARBITRATION REGISTER C0M15AR1 MESSAGE ARBITRATION REGISTER C0M15AR2 MESSAGE ARBITRATION REGISTER C0M15AR3 MESSAGE ARBITRATION REGISTER WTOE C0M15F DTBYC3 DTBYC2 DTBYC1 DTBYC0 MEME MDME C0M15D0CAN MESSAGE DATA BYTE C0M15D7 Reserved xxxxF0h xxxxF2h xxxxF3h xxxxF4h xxxxF5h xxxxF6h xxxxF7h xxxxFFh
xxxx20h xxxx30h xxxx40h xxxx50h xxxx60h xxxx70h xxxx80h xxxx90h xxxxA0h xxxxB0h xxxxC0h xxxxD0h xxxxE0h
Notes: first bytes MOVX memory address dependent setting (MCON.5) CMA=0, xxxx=00EE; CMA=1, xxxx=4010.
DS80C390
MOVX MESSAGE CENTERS
CONTROL/STATUS/MASK REGISTERS
Register
MOVX Data Address1
C1MID0 C1MA0 C1MID1 C1MA1 C1BT0 C1BT1 C1SGM0 C1SGM1 C1EGM0 C1EGM1 C1EGM2 C1EGM3 C1M15M0 C1M15M1 C1M15M2 C1M15M3
MID07 M0AA7 MID17 M1AA7 SJW1 ID28 ID20 ID28 ID20 ID12 ID28 ID20 ID12
MID06 MID05 MID04 MID03 MID02 MID01 MID00 M0AA6 M0AA5 M0AA4 M0AA3 M0AA2 M0AA1 M0AA0 MID16 MID15 MID14 MID13 MID12 MID11 MID10 M1AA6 M1AA5 M1AA4 M1AA3 M1AA2 M1AA1 M1AA0 SJW0 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 TSEG26 TSEG25 TSEG24 TSEG13 TSEG12 TSEG11 TSEG10 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID19 ID18 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID19 ID18 ID17 ID16 ID15 ID14 ID13 ID11 ID10 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID19 ID18 ID17 ID16 ID15 ID14 ID13 ID11 ID10
MESSAGE CENTER
xxxx00h xxxx01h xxxx02h xxxx03h xxxx04h xxxx05h xxxx06h xxxx07h xxxx08h xxxx09h xxxx0Ah xxxx0Bh xxxx0Ch xxxx0Dh xxxx0Eh xxxx0Fh
xxxx10h xxxx12h xxxx13h xxxx14h xxxx15h xxxx16h xxxx17h xxxx1Fh
C1M1AR0 C1M1AR1 C1M1AR2 C1M1AR3 C1M1F C1M1D0-7
Reserved MESSAGE ARBITRATION REGISTER MESSAGE ARBITRATION REGISTER MESSAGE ARBITRATION REGISTER MESSAGE ARBITRATION REGISTER DTBYC3 DTBYC2 DTBYC1 DTBYC0 MEME MESSAGE DATA BYTES Reserved
WTOE MDME
MESSAGE CENTERS 2-14 MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center MESSAGE CENTER REGISTERS (similar Message Center
xxxx20h xxxx30h xxxx40h xxxx50h xxxx60h xxxx70h xxxx80h xxxx90h xxxxA0h xxxxB0h xxxxC0h xxxxD0h xxxxE0h
DS80C390
MESSAGE CENTER
C1M15AR0 C1M15AR1 C1M15AR2 C1M15AR3 Reserved MESSAGE ARBITRATION REGISTER MESSAGE ARBITRATION REGISTER MESSAGE ARBITRATION REGISTER MESSAGE ARBITRATION REGISTER xxxxF0h xxxxF2h xxxxF3h xxxxF4h xxxxF5h xxxxF6h xxxxF7h xxxxFFh
WTOE MDME
C1M15F DTBYC3 DTBYC2 DTBYC1 DTBYC0 MEME C1M15D0CAN MESSAGE DATA BYTE C1M15D7 Reserved
Notes: first bytes MOVX memory address dependent setting (MCON.5) CMA=0, xxxx=00EF; CMA=1, xxxx=4011.
INTERRUPTS
DS80C390 supports interrupts associated with controllers. interrupt dedicated each controller, providing receive/transmit acknowledgments from each message centers. remaining interrupt, Activity Interrupt, used detect activity C0RX C1RX pins. message center interrupts enabled/disabled individual (transmit) (receive) enable bits corresponding Message Control Register (located memory) each message center. message center interrupts each module ORed together into their respective interrupt. successful transmission receipt message will INTRQ corresponding Message Control Register (located memory). This only cleared software. addition, Global Interrupt Enable (IE.7) specific Interrupt Enable bit, EIE.6 (CAN0) EIE.5 (CAN1) must correctly acknowledge message center interrupt. Interrupt assertion error status conditions associated with modules controlled ERIE STIE bits located Control registers, C1C.
ARBITRATION MASKING
After module ascertained that incoming message error-free, identification field that message then compared against more arbitration values determine they will loaded into message center. Each enabled message center (see MSRDY Message Control Register) tested order from 1-15. first message center successfully pass test will receive incoming message testing. masking registers allows more complex identification schemes, tests made based patterns rather than exact match between bits identification field arbitration values. Each processor also incorporates five masks allow messages with different grouped successfully loaded into message center; Note that some these masks optional bits shown Arbitration/Masking Feature Summary table. There several possible arbitration tests, varying according which message center involved. enabled tests succeed, message loaded into respective message center. most basic test, performed messages, compares either (CAN 2.0A) (CAN 2.0B) bits identification field appropriate arbitration register, based Format Register. MEME (C0MxF.1 C1MxF.1) controls whether arbitration registers
DS80C390
compared directly mask register. special arbitration registers dedicated Message center allow added flexibility filtering this location. desired, further arbitration performed comparing first bytes data field each message against 8-bit Media Arbitration register bytes. MDME Message Center Format Registers (C0MxF.0 C1MxF.0) either disables (MDME=0) arbitration, enables (MDME=1) arbitration using Media Mask Registers 0-1. 11-bit 29-bit arbitration optional Media Byte arbitration successful message loaded into respective message center. Format Register also allows microcontroller program each message center function receive transmit mode from data bytes within data field message. Note that Message Center only used receive mode. avoid priority inversion DS80C390 processors configured reload transmit buffer with message highest priority (lowest message center number) whenever arbitration lost error condition occurs.
ARBITRATION/MASKING FEATURE SUMMARY Table
Test Name Arbitration Registers
Standard 11-bit arbitration (CAN 2.0A)
Message Center Arbitration Registers (Located each Message Center, MOVX memory) Message Center Arbitration Registers (Located each Message Center, MOVX memory) Media Arbitration Registers (Located each Control/Status/Mask Register bank, MOVX memory) Message Center Arbitration Registers (Located Message Center MOVX memory)
Extended 29-bit arbitration (CAN 2.0B)
Media byte arbitration
Mask Registers Standard Global Mask Registers (Located each Control/Status/Mask Register bank, MOVX memory) Extended Global Mask Registers (Located each Control/Status/Mask Register bank, MOVX memory) Media Mask Registers (Located each Control/Status/Mask Register bank, MOVX memory)
Control bits conditions
MEME=0: Mask register ignored. arbitration register must match exactly. MEME=1: Only bits corresponding mask register compared arbitration registers. MEME=0: Mask register ignored. arbitration register must match exactly. MEME=1: Only bits corresponding mask register compared arbitration registers. MDME=0: Media byte arbitration disabled. MDME Only bits corresponding Media mask register compared between data bytes Media arbitration registers. MEME=0: Mask register ignored. arbitration register must match exactly. MEME=1: Message center mask registers ANDed with Global Mask register. Only bits corresponding resulting value compared arbitration registers. MEME=0: Mask register ignored. arbitration register must match exactly. MEME=1: Message center mask registers ANDed with Global Mask register. Only bits corresponding resulting value compared arbitration registers.
Message Center Standard 11-bit arbitration (CAN 2.0A)
Message Center Mask Registers (Located each Control/Status/Mask Register bank, MOVX memory) Message Center Mask Registers (Located each Control/Status/Mask Register bank, MOVX memory)
Message Center Extended 29-bit arbitration (CAN 2.0B)
Message Center Arbitration Registers (Located Message Center MOVX memory)
MESSAGE BUFFERING/OVERWRITE
message center configured reception previous message been read (DTUP=1), then disposition incoming message that message center will controlled WTOE (located Arbitration Register each message center). When WTOE=0, incoming message will discarded current message untouched.
DS80C390
WTOE set, incoming message will received written over existing data bytes that message center. Receiver Overwrite (ROW) will also corresponding Message Center Control Register, located memory. Message center unique that incorporates buffer that receive messages without loss. message received message center while contains unread message, incoming message held internal buffer. When processor reads message center memory location then clears DTUP=INTRQ=EXTRQ=0, contents internal buffer will automatically loaded into message center MOVX memory location. message center WTOE controls what happens third message received when both message center MOVX memory location buffer contain unread messages. WTOE=0, message will discarded, leaving message center MOVX memory location buffer untouched. WTOE=1, then third message will write over buffered message leave message center MOVX memory location untouched.
ERROR COUNTER INTERRUPT GENERATION
Each module independently configured alert microprocessor when either errors have been detected transmit receive error counters. Error Count Select bit, ERCS (C0C.1 C1C.1) selects whether limit (ERCS=0) (ERCS=1) errors. When error limit exceeded, Error Count Exceeded bit, CECE (C0S.6 C1S.6) set. ERIE, C0IE C1IE), bits configured, interrupt will generated. ERCS set, device will generate interrupt when CECE cleared, interrupt enabled.
TIMING
timing transmission adjusted 2.0B specification. Timing Register Zero (C0BT0 C1BT0), located Control/Status/Mask Register block MOVX memory, controls PHASE_SEG1 PHASE_SEG2 time segments well Baud Rate Prescaler (BPR5 BPR0). Timing Register (C0BT1 C1BT1) contains controls sampling rate number clock cycles assigned Phase Segment portions Nominal Time. values both Timing registers automatically loaded into Processor following each software change SWINT from microcontroller. timing parameters must before starting operation Processor. These registers only modifiable during software initialization, (SWINT when Processor mode, after removal system reset reset. avoid unpredictable behavior Processor, software cannot clear SWINT when TSEG1 TSEG2 both cleared
DS80C390
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Ground Voltage relative ground Operating Temperature Storage Temperature Soldering Temperature -0.3 (VCC -0.3 +125 seconds
This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL Supply Voltage Power Fail Warning VPFW Min. Operating Voltage VRST Supply Current Active Mode Supply Current Idle Mode IIDLE Supply Current Stop Mode ISTOP Supply Current Stop Mode, ISPBG Band-gap enabled Input Level Input High Level Input High Level XTAL1, VIH2 Output Voltage Port VOL1 IOL=1.6 VOL2 Output Voltage Port PCE0 RSTOL PSEN ALE, IOL=3.2 Output High Voltage Port VOH1 1,3,4,5, IOH= Output High Voltage Port VOH2 1,3,4,5 IOH= -1.5 VOH3 Output High Voltage Port 0,1,2,4, PCE0 RSTOL PSEN IOH= Input Current Port @0.45V Logic Transition Current Port Input Leakage Current Port (input mode only) Pulldown Resistance RRST VRST 4.25 4.38 4.13 4.25 UNITS
NOTES
-0.5
+0.8 +0.5 +0.5 0.45 0.45
-650 -300
+300
DS80C390
NOTES ELECTRICAL CHARACTERISTICS:
Active current measured with clock source XTAL1, VCC=RST= other pins disconnected. Idle mode current measured with clock source XTAL1, VCC= RST= =VSS, other pins disconnected. Stop mode current measured with XTAL1 VSS, VCC= other pins disconnected. This value guaranteed. Users sensitive this specification should contact Dallas Semiconductor more information. When these pins used address external memory interface signals. This measurement reflects port during transition mode. During this period oneshot circuit drives ports hard clock cycles. Port pins will have stronger than normal pullup drive oscillator period following transition either from transition. This current required from external circuit hold logic level while corresponding port latch This only current required hold level; transitions from will also have overcome transition current. Ports 1(in mode), source transition current when being pulled down externally. reaches maximum approximately During external addressing mode, weak latches maintain previously driven value from processor Port until such time that Port driven external memory source; Port XTAL1 cycle prior change output address from Port RST= VCC. This condition mimics operation pins mode.
TYPICAL VERSUS FREQUENCY
XTAL FREQUENCY
DS80C390
ELECTRICAL CHARACTERISTICS (Multiplexed address/data bus)
SYMBOL (Ext. Osc) tCLCL (Ext. Crystal) Pulse Width tLHLL Port Instruction Address tAVLL Valid Address Hold after tLLAX1 Valid Instruction tLLIV tLLPL PSEN tPLPH PSEN Pulse Width tPLIV PSEN Valid Instruction tPXIX Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN Port Address Valid Instruction tAVIV1 Port Address Valid tAVIV2 Instruction tPLAZ PSEN Address Float PARAMETER Oscillator Freq. VARIABLE CLOCK 0.375 tMCS 0.125 tMCS UNITS
0.125 tMCS 0.625 tMCS 0.125 tMCS tMCS tMCS 0.25 tMCS 0.75 tMCS 0.875 tMCS
NOTES ELECTRICAL CHARACTERISTICS:
parameters apply both commercial industrial temperature operation unless otherwise noted. value tMCS function machine cycle clock terms processor's input clock frequency. These relationships described "Stretch Value Timing" table. signals characterized with load capacitance except Port ALE, PSEN with Interfacing memory devices with float times (turn times) over cause contention. This will damage parts, will cause increase operating current. Specifications assume duty cycle oscillator. Port timing will change relation duty cycle variation. Some timing characteristic drawings contain references signal. This waveform provided assist determining relative occurrence events, cannot used determine timing signals relative external clock.
DS80C390
MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE
MOVX CHARACTERISTICS (Multiplexed address/data bus)
PARAMETER SYMBOL UNITS STRETCH VALUES (MD2:0) tMCS 0.25 tMCS 0.5tMCS tMCS 0.625 tMCS
MOVX Pulse Width
tLHLL2 tAVLL2 tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV
Port MOVX Address, PCE0 Valid Address Hold after MOVX Read/Write
Pulse Width Pulse Width Valid Data
0.375 tMCS tMCS tMCS 0.125 tMCS 0.25tMCS 1.25 tMCS 0.125 tMCS 1.125 tMCS tMCS tMCS
Data Hold after Read Data Float after Read
Valid Data
DS80C390
Port Address, Port Port Valid Data Port Address Valid Data Port Address, Port Port Port Address Data Valid Transition Data hold after high
tAVDV1 tAVDV2 tLLWL tAVWL1
tAVWL2 tQVWX tWHQX
0.75 tMCS 0.875 tMCS 0.125 tMCS 0.125 tMCS 0.25tMCS 0.25tMCS 1.25 tMCS 1.25 tMCS 0.25 tMCS 0.5tMCS tMCS 0.375 tMCS 0.625tMCS 2.625 tMCS 0.25 tMCS 0.5tMCS tMCS 0.25 tMCS 1.25 tMCS -(0.125 tMCS 0.25 tMCS 1.25 tMCS
Address Float High ALE, Port Port High
tRLAZ tWHLH
NOTES MOVX CHARACTERISTICS:
parameters apply both commercial industrial temperature operation unless otherwise noted. stretch cycle value determined MD2, MD1, bits CKCON register. tMCS time period determined stretch cycle value, shown following table.
tMCS TIME PERIODS
System Clock Selection tMCS tCLCL tCLCL tCLCL 1024 tCLCL
DS80C390
DS80C390
DS80C390
MULTIPLEXED CYCLE DATA MEMORY PCE0 READ WRITE
MULTIPLEXED CYCLE DATA MEMORY READ
DS80C390
MULTIPLEXED CYCLE DATA MEMORY WRITE
MULTIPLEXED CYCLE DATA MEMORY PCE0 READ WRITE
DS80C390
MULTIPLEXED CYCLE DATA MEMORY READ
MULTIPLEXED CYCLE DATA MEMORY WRITE
DS80C390
MULTIPLEXED CYCLE DATA MEMORY PCE0 READ WRITE
MULTIPLEXED CYCLE DATA MEMORY READ
DS80C390
MULTIPLEXED CYCLE DATA MEMORY WRITE
ELECTRICAL CHARACTERISTICS (Non-multiplexed address/data bus)
PARAMETER SYMBOL Oscillator Freq. (Ext. Osc) tCLCL (Ext. Crystal) tPLPH PSEN Pulse Width tPLIV PSEN Valid Instruction tPXIX Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN VARIABLE CLOCK tMCS tMCS MOVX characteristics 0.75 tMCS UNITS
Port Address, Port Valid Instruction Port Address Valid Instruction
tAVIV1 tAVIV2
0.875 tMCS
NOTES ELECTRICAL CHARACTERISTICS:
parameters apply both commercial industrial temperature operation unless otherwise noted. value tMCS function machine cycle clock terms processor's input clock frequency. These relationships described "Stretch Value Timing" table. signals characterized with load capacitance except Port ALE, PSEN with Interfacing memory devices with float times (turn times) over cause contention. This will damage parts, will cause increase operating current. Specifications assume duty cycle oscillator. Port timing will change relation duty cycle variation.
DS80C390
NON-MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE
DS80C390
MOVX CHARACTERISTICS (Non-multiplexed address/data bus)
PARAMETER SYMBOL UNITS STRETCH VALUES (MD2:0)
Input Instruction Float after
PSEN PSEN High Data Address,
tPXIZ tPHAV tRLRH tWLWH tRLDV tRHDX tRHDZ tPHWL
tMCS 0.75 tMCS 2.75 tMCS 0.25 tMCS tMCS tMCS
Port Port Valid Pulse Width
tMCS tMCS 0.75tMCS 1.75 tMCS tMCS 0.75tMCS 2.75 tMCS tMCS 0.75tMCS 2.75 tMCS 0.75 tMCS (CST+0. 0.875 tMCS
Pulse Width Valid Data
Data Hold after Read Data Float after Read
PSEN High
Data Float after Read
tPHRL tAVDV1 tAVDV2 tAVWL1 tAVWL2 tQVWX tWHQX 0.25 tMCS 0.5tMCS tMCS 0.375 tMCS 0.625tMCS 2.625 tMCS 0.25 tMCS 0.5tMCS tMCS 0.25 tMCS 1.25 tMCS
Port Address, Port Port Valid Data Port Address Valid Data Port Address, Port Port Port Address Data Valid Transition Data hold after high
High ALE, Port Port High
tWHCEH
0.25 tMCS 1.25 tMCS
DS80C390
DS80C390
DS80C390
NON-MULTIPLEXED CYCLE DATA MEMORY PCE0 READ WRITE
NON-MULTIPLEXED CYCLE DATA MEMORY READ
DS80C390
NON-MULTIPLEXED CYCLE DATA MEMORY CE0-3 WRITE
NON-MULTIPLEXED CYCLE DATA MEMORY PCE0 READ WRITE
DS80C390
NON-MULTIPLEXED CYCLE DATA MEMORY READ
NON-MULTIPLEXED CYCLE DATA MEMORY WRITE
DS80C390
NON-MULTIPLEXED CYCLE DATA MEMORY PCE0 READ WRITE
NON-MULTIPLEXED CYCLE DATA MEMORY READ
DS80C390
NON-MULTIPLEXED CYCLE DATA MEMORY WRITE
tMCS TIME PERIODS
System Clock Selection tMCS tCLCL tCLCL tCLCL 1024 tCLCL UNITS
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock high time Clock time Clock rise time Clock fall time SYMBOL tCHCX tCLCX tCLCH tCHCL
EXTERNAL CLOCK DRIVE
DS80C390
SERIAL PORT MODE TIMING CHARACTERISTICS
PARAMETER Serial port clock cycle time SM2=0:2 clocks cycle SM2=1:4 clocks cycle Output data setup clock rising SM2=0:12 clocks cycle SM2=1:4 clocks cycle Output data hold from clock rising M2=0:12 clocks cycle SM2=1:4 clocks cycle Input data hold after clock rising SM2=0:12 clocks cycle SM2=1:4 clocks cycle Clock rising edge input data valid SM2=0:12 clocks cycle SM2=1:4 clocks cycle SYMBOL tXLXL TYPICAL UNITS
tCLCL tCLCL tQVXH tCLCL tCLCL tXHQX tCLCL tCLCL tXHDX tCLCL tCLCL tXHDV tCLCL tCLCL
DS80C390
SERIAL PORT (SYNCHRONOUS MODE)
HIGH-SPEED OPERATION, XTAL/4 (SM2
TRADITIONAL 8051 OPERATION, CLOCK=XTAL/12 (SM2=0)
DS80C390
EXPLANATION SYMBOLS
This microcontroller uses timing parameters symbols similar original 8051 family. following list timing symbols provided understanding timing diagrams. Time Address Clock Chip Enable Input data Logic level high Logic level Instruction
PSEN
Output data signal Valid signal longer valid logic level Tristate
POWER CYCLE TIMING CHARACTERISTICS
PARAMETER Crystal start-up time Power-on reset delay SYMBOL tCSU tPOR
65536
UNITS NOTE tCLCL
NOTES POWER CYCLE TIMING CHARACTERISTICS
Start-up time crystals varies with load capacitance manufacturer. Time shown 11.0592 crystal manufactured Electronics. Reset delay synchronous counter crystal oscillations during crystal start-up. Counting begins when level XTAL1 input meets VIH2 criteria. MHz, this time approximately 1.64
POWER CYCLE TIMING
DS80C390
68-PIN PLCC
DS80C390
64-PIN LQFP
DS80C390
DATA SHEET REVISION SUMMARY
following represent differences between 092499 101999 version DS80C390 data sheet. Please review this summary carefully. Corrected P5.2 P5.3 descriptions. Corrected description sequence activate crystal frequency multiplier. Corrected references PQFP read LQFP. Added RSTOL timing information.
following represent differences between 062299 090799 version DS80C390 data sheet. Please review this summary carefully. Clarifies that unused/unimplemented bits MOVX SRAM will read Corrected tMCS time periods tables. Corrected multiplexed 2-cycle date memory CEO-3 read figure show inactive.

DS80C390 Dual High-Speed Microprocessor FEATURES 80C52 compa

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