MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105) data delay devi
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3D7105
MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105)
data delay devices, inc.
PACKAGES
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs 3D7105Z SOIC Vapor phase, wave (150 Mil) solderable 3D7105M Auto-insertable (DIP pkg.) 3D7105H Gull-Wing (300 Mil) ground bounce noise Leading- trailing-edge accuracy Delay range: through 80ns Delay tolerance: Temperature stability: typical (0C-70C) stability: typical (4.75V-5.25V) Minimum input pulse width: total delay 14-pin 16-pin SOIC available drop-in 3D7105S SOIC replacements hybrid delay lines (300 Mil)
3D7105 3D7105G Gull-Wing 3D7105K Unused pins removed (300 Mil)
FUNCTIONAL DESCRIPTION
3D7105 5-Tap Delay Line product family consists fixed-delay CMOS integrated circuits. Each package contains single delay line, tapped buffered points spaced uniformly time. Tap-to-tap (incremental) delay values range from 0.75ns through 8.0ns. input reproduced outputs without inversion, shifted time user-specified dash number. 3D7105 TTL- CMOScompatible, capable driving 74LS-type loads, features both rising- falling-edge accuracy.
DESCRIPTIONS
Delay Line Input Output (20%) Output (40%) Output (60%) Output (80%) Output (100%) Volts Ground Connection
all-CMOS 3D7105 integrated circuit been designed reliable, economic alternative hybrid fixed delay lines. offered standard 8-pin auto-insertable space saving surface mount 8-pin SOIC.
TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
DIP-8 3D7105M 3D7105H SOIC-8 3D7105Z DIP-14 3D7105 3D7105G 3D7105K SOIC-16 3D7105S
TOLERANCES
TOTAL DELAY (ns) TAP-TAP DELAY (ns) Operating Frequency
INPUT RESTRICTIONS
Absolute Oper. Freq. Operating Pulse Width Absolute Oper. P.W.
-.75 -.75 -.75 -.75 41.7 1.0* 0.75 37.0 1.0* -1.5 -1.5 -1.5 -1.5 30.3 1.0* 25.6 1.0* -2.5 -2.5 -2.5 -2.5 22.2 10.0 1.0* 15.9 16.0 1.0* 13.3 25.0 9.52 40.0 Total delay referenced Tap1 output; Input-to-Tap1 5.0ns 1.0ns NOTE: dash number between shown also available.
166.7 166.7 166.7 166.7 133.3 83.3 66.7 41.7
12.0 13.5 16.5 19.5 22.5 31.5 37.5 52.5
3.00 3.00 3.00 3.00 3.75 6.00 7.50 12.0
©1996 Data Delay Devices
#96006
12/2/96
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7105
APPLICATION NOTES
OPERATIONAL DESCRIPTION
3D7105 five-tap delay line architecture shown Figure delay line composed number delay cells connected series. Each delay cell produces output replica signal present input, shifted time. delay cells matched share same compensation signals, which minimizes tap-totap delay deviations over temperature supply voltage variations. guarantee Table delay accuracy input frequencies higher than Maximum Operating Frequency, 3D7105 must tested user operating frequency. Therefore, facilitate production device identification, part number will include custom reference designator identifying intended frequency operation. programmed delay accuracy device guaranteed, therefore, only user specified input frequency. Small input frequency variation about selected frequency will only marginally impact programmed delay accuracy, all. Nevertheless, strongly recommended that engineering staff DATA DELAY DEVICES consulted.
INPUT SIGNAL CHARACTERISTICS
Frequency and/or Pulse Width (high low) operation adversely impact specified delay accuracy particular device. reasons dependency output delay accuracy input signal characteristics varied complex. Therefore Maximum Absolute Maximum operating input frequency Minimum Absolute Minimum operating pulse width have been specified.
OPERATING PULSE WIDTH
Absolute Minimum Operating Pulse Width (high low) specification, tabulated Table determines smallest Pulse Width delay line input signal that reproduced, shifted time device output, with acceptable pulse width distortion. Minimum Operating Pulse Width (high low) specification determines smallest Pulse Width delay line input signal which output delay accuracy tabulated Table guaranteed. guarantee Table delay accuracy input pulse width smaller than Minimum Operating Pulse Width, 3D7105 must tested user operating pulse width. Therefore, facilitate production device identification, part number will include
OPERATING FREQUENCY
Absolute Maximum Operating Frequency specification, tabulated Table determines highest frequency delay line input signal that reproduced, shifted time device output, with acceptable duty cycle distortion. Maximum Operating Frequency specification determines highest frequency delay line input signal which output delay accuracy guaranteed.
Temp Compensation
Temp Compensation
Dash numbers
Dash numbers
Figure 3D7105 Functional Diagram
#96006
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7105
APPLICATION NOTES (CONT'D)
custom reference designator identifying intended frequency duty cycle operation. programmed delay accuracy device guaranteed, therefore, only user specified input characteristics. Small input pulse width variation about selected pulse width will only marginally impact programmed delay accuracy, all. Nevertheless, strongly recommended that engineering staff DATA DELAY DEVICES consulted. circuitry minimize delay variations induced fluctuations power supply and/or temperature. thermal coefficient reduced PPM/C, which equivalent variation over 0C-70C operating range, from room-temperature delay settings and/or 1.0ns, whichever greater. power supply coefficient reduced, over 4.75V-5.25V operating range, delay settings nominal 5.0VDC power supply and/or 1.5ns, whichever greater. essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred.
POWER SUPPLY TEMPERATURE CONSIDERATIONS
delay CMOS integrated circuits strongly dependent power supply temperature. monolithic 3D7105 programmable delay line utilizes novel innovative compensation
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 -1.0 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/tap (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
#96006
12/2/96
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7105
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 1.25 Total Delay Period: PERIN Total Delay OUTPUT: Rload: Cload: Threshold: 1.5V (Rising Falling)
Device Under Test
Digital Scope
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR
TRIG
DEVICE UNDER TEST (DUT)
OUT1 OUT2 OUT3 OUT4 OUT5
TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN PWIN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL
2.4V 1.5V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.5V
1.5V
Figure Timing Diagram
#96006
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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