Quad LVDS Driver with Flow-Through Pinout MAX9129 quad low-voltag
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19-2100; 8/01
Quad LVDS Driver with Flow-Through Pinout
MAX9129 quad low-voltage differential signaling (BLVDS) driver with flow-through pinout. This device designed drive heavily loaded multipoint with controlled transition times (1ns 100% minimum) reduced reflections. MAX9129 accepts four LVTTL/LVCMOS input levels translates them output levels 250mV 450mV (standard LVDS levels) into load speeds 200Mbps (100MHz). power-on reset ensures that four outputs disabled high impedance during power power down. outputs high impedance enable inputs, thus dropping device low-power state 11mW. enables common four drivers. flow-through pinout simplifies board layout reduces crosstalk keeping LVTTL/LVCMOS inputs BLVDS outputs separated. MAX9129 operates from single +3.3V supply specified operation from -40°C +85°C. available 16-pin TSSOP packages. Refer MAX9121 data sheet quad LVDS line receiver with flow-through pinout. Drive LVDS Levels into Load 100%) Minimum Transition Time Reduces Reflections Guaranteed 200Mbps (100MHz) Data Rate Enable Pins High-Impedance Output High-Impedance Outputs when Powered Glitch-Free Power-Up Power-Down Swappable Flow-Through Pinout Available Tiny Package (50% Smaller than TSSOP) Single +3.3V Supply
Features
MAX9129
Ordering Information
PART MAX9129EGE MAX9129EUE TEMP. RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE TSSOP
Applications
Cell Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
Functional Diagram appears data sheet. Configurations appear data sheet.
Typical Applications Circuit
CARD
MAX9129 MAX9121
CARD
MAX9129 MAX9121
CARD
MAX9129 MAX9121
CARD
MAX9129 MAX9121
MULTIPOINT FULL-DUPLEX TRANSMIT RECEIVE TERMINATION RESISTOR
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Quad LVDS Driver with Flow-Through Pinout MAX9129
ABSOLUTE MAXIMUM RATINGS
.-0.3V +4.0V IN_, GND.-0.3V (VCC 0.3V) OUT_+, OUT_- GND.-0.3V +4.0V Short-Circuit Duration (OUT_+, OUT_-) .Continuous Continuous Power Dissipation +70°C) 16-Pin (derate 18.5mW/°C above +70°C) .1481mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .755mW Storage Temperature Range .-65°C +150°C Maximum Junction Temperature .+150°C Operating Temperature Range .-40°C +85°C Protection Human Body Model, OUT_+, OUT_- .±8kV Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, ±1%, high, low, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) (Notes
PARAMETER Differential Output Voltage Change Magnitude Between Complementary Output States Offset Voltage Change Magnitude Between Complementary Output States Output High Voltage Output Voltage Differential Output Short-Circuit Current Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current Output Capacitance INPUTS (IN_, High-Level Input Voltage Low-Level Input Voltage Input Current SUPPLY CURRENT Supply Current Disabled Supply Current ICCZ channels Disabled IN_, SYMBOL IOSD IOFF COUT OUT_+ OUT_- Disabled, OUT_+ VCC, OUT_- open, OUT_+ 3.6V, OUT_- 3.6V Capacitance from OUT_+ OUT_- 0.90 Figure Figure Figure Figure 1.125 CONDITIONS 1.29 1.465 1.085 1.375 UNITS
BLVDS OUTPUTS (OUT_+, OUT_-)
Quad LVDS Driver with Flow-Through Pinout
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, ±1%, 15pF, high, low, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) (Notes
PARAMETER Differential Propagation Delay High Differential Propagation Delay High Differential Pulse Skew (Note Differential Channel-to-Channel Skew (Note Differential Part-to-Part Skew (Note Differential Part-to-Part Skew (Note Rise Time Fall Time Disable Time High Disable Time Enable Time High Enable Time Maximum Operating Frequency (Note SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figure MAX9129EGE MAX9129EUE MAX9129EGE MAX9129EUE 0.60 0.60 0.60 0.60 1.19 1.09 1.12 1.02 1.98 1.92 1.55 1.40 1.55 1.40 UNITS
MAX9129
Note Maximum minimum limits over temperature guaranteed design characterization. Devices 100% tested +25°C. Note Current into device defined positive, current device defined negative. voltages referenced ground except VOD. Note parameters guaranteed design characterization. Note includes probe capacitance. Note Signal generator conditions: VCC, 100MHz, duty cycle, (10% 90%). Note tSKD1 magnitude difference differential propagation delays. tSKD1 tPHLD tPLHD Note tSKD2 magnitude difference tPHLD tPLHD channel tPHLD tPLHD another channel same device. Note tSKD3 magnitude difference differential propagation delays between devices same within each other. Note tSKD4 magnitude difference differential propagation delays between devices operating over rated supply temperature ranges. Note Signal generator conditions: VCC, 100MHz, duty cycle, (10% 90%). MAX9129 output criteria: duty cycle 55%, 250mV, channels switching.
Quad LVDS Driver with Flow-Through Pinout MAX9129
Typical Operating Characteristics
(MAX9129EUE (TSSOP package), +3.3V, 15pF, +25°C, unless otherwise noted.) (Note
OUTPUT VOLTAGE SUPPLY VOLTAGE
MAX9129 toc02 MAX9129 toc01
OUTPUT HIGH VOLTAGE SUPPLY VOLTAGE
1.48 1.12
OUTPUT SHORT CURRENT (IOS) SUPPLY VOLTAGE
MAX9129 toc03
-14.12 OUTPUT SHORT CURRENT (mA)
OUTPUT HIGH VOLTAGE
OUTPUT VOLTAGE
1.47
1.10
-14.11
1.46
1.08
-14.10
1.45
1.06
-14.09
1.44 SUPPLY VOLTAGE
1.04 SUPPLY VOLTAGE
-14.08 SUPPLY VOLTAGE
OUTPUT HIGH-IMPEDANCE CURRENT SUPPLY VOLTAGE
MAX9129 toc04
DIFFERENTIAL OUTPUT VOLTAGE SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9129 toc05
DIFFERENTIAL OUTPUT VOLTAGE LOAD RESISTANCE
MAX9129 toc06
OUTPUT HIGH-IMPEDANCE CURRENT (pA) VOUT_
372.0
1.750 DIFFERENTIAL OUTPUT VOLTAGE 1.500 1.250 1.000 0.750 0.500 0.250
371.5
371.0
370.5
SUPPLY VOLTAGE
370.0 SUPPLY VOLTAGE
LOAD RESISTANCE
OUTPUT OFFSET VOLTAGE SUPPLY VOLTAGE
MAX9129 toc07
SUPPLY CURRENT FREQUENCY
MAX9129 toc08
SUPPLY CURRENT SUPPLY VOLTAGE
MAX9129 toc09
1.305 1.300 OUTPUT OFFSET VOLTAGE 1.295 1.290 1.285 1.280 1.275 1.270 1.265 SUPPLY VOLTAGE
57.7
SUPPLY CURRENT (mA)
57.5 SUPPLY CURRENT (mA)
57.3
57.1
56.9
FREQUENCY (MHz) 1000
56.7 SUPPLY VOLTAGE
Quad LVDS Driver with Flow-Through Pinout
Typical Operating Characteristics (continued)
(MAX9129EUE (TSSOP package), +3.3V, 15pF, +25°C, unless otherwise noted.) (Note
SUPPLY CURRENT TEMPERATURE
MAX9129 toc10
MAX9129
DIFFERENTIAL PROPAGAION DELAY SUPPLY VOLTAGE
MAX9129 toc11
DIFFERENTIAL PROPAGATION DELAY TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9129 toc12
2.10 DIFFERENTIAL PROPAGATION DELAY (ns) 2.05 tPHLD 2.00 1.95 1.90 1.85 1.80
2.20 2.10 2.00 1.90 1.80 1.70 1.60 tPLHD
SUPPLY CURRENT (mA)
tPHLD
tPLHD
TEMPERATURE (°C)
SUPPLY VOLTAGE
TEMPERATURE (°C)
DIFFERENTIAL SKEW SUPPLY VOLTAGE
MAX9129 toc13
DIFFERENTIAL SKEW TEMPERATURE
MAX9129 toc14
TRANSITION TIME SUPPLY VOLTAGE
TRANSITION TIME (ns) tTLH
MAX9129 toc15
DIFFERENTIAL SKEW (ps) SUPPLY VOLTAGE
DIFFERENTIAL SKEW (ps)
tTHL
TEMPERATURE (°C)
SUPPLY VOLTAGE
TRANSITION TIME TEMPERATURE
1.200 1.150 TRANSITION TIME (ns) 1.100 1.050 1.000 0.950 0.900 0.850 0.800 TEMPERATURE (°C) tTHL tTLH
MAX9129 toc16
1.250
Quad LVDS Driver with Flow-Through Pinout MAX9129
Description
TSSOP NAME FUNCTION LVTTL/LVCMOS Enable Input. driver disabled when low. internally pulled down. When high open, outputs active. other combinations outputs disabled high impedance. LVTTL/LVCMOS Driver Inputs Power-Supply Input. Bypass with 0.1µF 0.001µF ceramic capacitors. Ground LVTTL/LVCMOS Enable Input. driver disabled when high. internally pulled down. Inverting BLVDS Driver Outputs Noninverting BLVDS Driver Outputs
OUT_OUT_+
OUT_+
RL/2 RL/2
OUT_ GENERATOR OUT_
OUT_-
Figure Driver Test Circuit
Figure Driver Propagation Delay Transition Time Test Circuit
tPLHD OUT_ DIFFERENTIAL OUT_+ tTLH tTHL (VOUT_+) (VOUT_-) tPHLD
Figure Driver Propagation Delay Transition Time Waveforms
Quad LVDS Driver with Flow-Through Pinout MAX9129
Table Input/Output Function Table
ENABLES
OUT_+
INPUTS
OUTPUTS OUT_+ OUT_
GENERATOR
RL/2
open
+1.2V RL/2 OUT_1/4 MAX9129
other combinations
Figure Driver High-Impedance Delay Test Circuit
WHEN OPEN
WHEN tPHZ OUT_+ WHEN OUT_- WHEN 1.2V 1.2V OUT_+ WHEN OUT_- WHEN tPLZ tPZL tPZH
Figure Driver High-Impedance Delay Waveform
Detailed Description
MAX9129 200Mbps quad differential BLVDS driver designed multipoint, heavily loaded backplane applications. This device accepts LVTTL/LVCMOS input levels translates them output levels 250mV 450mV into load. flow-through pinout simplifies board layout reduces potential crosstalk between single-ended inputs differential outputs. Transition times designed reduce reflections, enable high data rates. MAX9129 used conjunction with standard quad LVDS receivers, such
MAX9121, implement full-duplex multipoint buses more efficiently than with transceivers.
Effect Capacitive Loading
characteristic impedance differential board trace uniformly reduced when equal capacitive loads attached equal intervals (provided transition time signal being driven trace longer than delay between loads). This kind loading typical multipoint buses where cards attached 0.8in intervals along length backplane.
Quad LVDS Driver with Flow-Through Pinout MAX9129
reduction characteristic impedance approximated following formula: ZDIFF-loaded ZDIFF-unloaded SQRT where: ZDIFF-unloaded unloaded differential characteristic impedance unloaded trace capacitance (pF/unit length) value each capacitive load (pF) number capacitive loads trace length example, 2.5pF/in, 10pF, 18in, ZDIFF-unloaded 120, loaded differential impedance ZDIFF-loaded SQRT [2.5pF (2.5pF 10pF/18in)] ZDIFF-loaded this example, capacitive loading reduces characteristic impedance from load seen driver located card middle because driver sees loads parallel. typical LVDS driver (rated load) would develop large enough differential signal reliably detected LVDS receiver. Maxim's BLVDS driver designed specified drive load differential voltage levels 250mV 450mV (which standard LVDS driver levels). standard LVDS receiver able detect this level differential signal. Short extensions bus, called stubs, contribute capacitive loading. Keep stubs less than good balance between ease component placement good signal integrity. MAX9129 current source driver drives larger differential signal levels into loads higher than smaller levels into loads less than (see typical operating curves). keep loading from reducing impedance below rated load, board traces designed higher unloaded characteristic impedance. minimum transition time (rated 0.6ns from 80%, about 100%) reduce reflections while being fast enough high-speed backplane data transmission.
Power-On Reset
power-on reset voltage MAX9129 typically 2.25V. When supply falls below this voltage, device disabled outputs high impedance.
Applications Information
Power-Supply Bypassing
Bypass with high-frequency, surface-mount ceramic 0.1µF 0.001µF capacitors parallel close device possible, with smaller valued capacitor closest VCC.
Termination
example above, loaded differential impedance reduced Since driven from card position, must terminated each end. parallel termination each placed across traces that make differential pair provides proper termination. total load seen driver MAX9129 drives higher differential signal levels into lighter loads. multidrop with driver receivers connected regular intervals along lowered impedance capacitive loading. Assuming same impedance calculated multidrop example above (54), multidrop terminated with single, parallel-connected resistor from driver. Only single resistor required because driver sees differential trace. signal swing larger with load. general, parallel terminate each with resistor matching differential impedance (taking into account reduced impedance loading).
Board Layout
four-layer board that provides separate power, ground, input, output signals recommended. Keep LVTTL/LVCMOS BLVDS signals separated prevent coupling shown suggested layout package (not drawn scale) (Figure
Effect Transition Time
transition times (measured from 100%) shorter than delay between capacitive loads, loads seen low-impedance discontinuities from which driven signal reflected. Reflections subtract from signal being driven cause decreased noise margin jitter. MAX9129 designed
Quad LVDS Driver with Flow-Through Pinout MAX9129
OUT1OUT1+
OUT2+ OUT2OUT3OUT3+
OUT4+ OUT4-
Figure Suggested Layout Package
Chip Information
TRANSISTOR COUNT: PROCESS: CMOS
Quad LVDS Driver with Flow-Through Pinout MAX9129
Configurations
VIEW
OUT115 OUT1+ OUT2+ OUT1- OUT1+
OUT2+ OUT2OUT3OUT3+
MAX9129
OUT212 OUT311 OUT3+ OUT4+ OUT4-
MAX9129
OUT4- OUT4+
TSSOP
(4mm 4mm) (CONTACTS UNDER QFN)
Functional Diagram
OUT1+ OUT1-
OUT2+ OUT2-
OUT3+ OUT3-
OUT4+ OUT4-
MAX9129
Quad LVDS Driver with Flow-Through Pinout
Package Information
TSSOP,NO PADS.EPS
MAX9129
Quad LVDS Driver with Flow-Through Pinout MAX9129
Package Information (continued)
16,20, QFN.EPS
Quad LVDS Driver with Flow-Through Pinout
Package Information (continued)
MAX9129
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2001 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.
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