Programmable Gain AMPLIFIER DIGITALLY PROGRAMABLE GAINS: G=1, 100
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PGA103
Programmable Gain AMPLIFIER
DIGITALLY PROGRAMABLE GAINS: G=1, 100V/V CMOS/TTL-COMPATIBLE INPUTS GAIN ERROR: ±0.05% max, G=10 OFFSET VOLTAGE DRIFT: 2µV/°C QUIESCENT CURRENT: 2.6mA COST 8-PIN PLASTIC DIP, SO-8 PACKAGES
DESCRIPTION
PGA103 programmable-gain amplifier general purpose applications. Gains digitally selected CMOS/TTL-compatible inputs. PGA103 ideal systems that must handle wide dynamic range signals. PGA103's high speed circuitry provides fast settling time, even G=100 (8µs 0.01%). Bandwidth 250kHz G=100, quiescent current only 2.6mA. operates from ±4.5V ±18V power supplies. PGA103 available 8-pin plastic SO-8 surface-mount packages, specified -40°C +85°C temperature range.
APPLICATIONS
DATA ACQUISITION SYSTEMS GENERAL PURPOSE ANALOG BOARDS MEDICAL INSTRUMENTATION
PGA103
GAIN
International Airport Industrial Park Mailing Address: 11400 Tucson, 85734 Street Address: 6730 Tucson Blvd. Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1993 Burr-Brown Corporation
PDS-1208B
Printed U.S.A. November, 1993
PGA103
SBOS031
SPECIFICATIONS
ELECTRICAL
+25°C, ±15V, unless otherwise specified. PGA103P, PARAMETER INPUT Offset Voltage, Temperature Power Supply Impedance INPUT BIAS CURRENT Initial Bias Current Temperature NOISE VOLTAGE, 10Hz 100Hz 1kHz 0.1Hz 10Hz NOISE CURRENT 10Hz 1kHz 0.1Hz 10Hz GAIN Gain Error Gain Temperature Nonlinearity OUTPUT Voltage, Positive Negative Load Capacitance, Short-Circuit Current FREQUENCY RESPONSE Bandwidth, -3dB Slew Rate Settling Time, 0.1% Settling Time, 0.01% Overload Recovery DIGITAL LOGIC INPUTS Digital Voltage Digital High Current Digital High Voltage (V+) -3.5 (V-) +3.5 100, nV/Hz nV/Hz nV/Hz µVp-p pA/Hz pA/Hz pAp-p CONDITIONS UNITS
+25°C
±200 ±100 ±100 ±100
±1500 ±500 ±500
µV/°C µV/°C µV/°C
TMIN TMAX
±4.5V ±18V
µV/V µV/V µV/V pA/°C
±150
±0.005 ±0.02 ±0.04 ±0.001 ±0.002 ±0.004 (V+) -2.5 (V-) +2.5 1000
±0.02 ±0.05 ±0.2
ppm/°C ppm/°C ppm/°C
±0.003 ±0.005 ±0.01
±10V
-5.6
V/µs
Overdrive
PGA103
SPECIFICATIONS (CONT)
ELECTRICAL
+25°C, ±15V, unless otherwise specified. PGA103P, PARAMETER POWER SUPPLY Voltage Range Current TEMPERATURE RANGE Specification Operating Package CONDITIONS ±4.5 ±2.6 ±3.5 +125 UNITS °C/W
CONFIGURATION
View
Ground
ABSOLUTE MAXIMUM RATINGS
DIP/SO-8 Supply Voltage ±18V Analog Input Voltage Range Logic Input Voltage Range Output Short Circuit ground) Continuous Operating Temperature -40°C +125°C Storage Temperature -40°C +125°C Junction Temperature +150°C Lead Temperature (soldering,10s) +300°C
PACKAGE INFORMATION
MODEL PACKAGE 8-Pin Plastic SO-8 Surface-Mount PACKAGE DRAWING NUMBER(1)
ORDERING INFORMATION
MODEL PGA103P PGA103U PACKAGE 8-Pin Plastic SO-8 Surface-Mount TEMPERATURE RANGE -40°C +85°C -40°C +85°C
PGA103P PGA103U
NOTE: detailed drawing dimension table, please data sheet, Appendix Burr-Brown Data Book.
ELECTROSTATIC DISCHARGE SENSITIVITY
integrated circuit damaged ESD. Burr-Brown recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
PGA103
DICE INFORMATION
FUNCTION Ground
3C(1) 4C(2)
Connection NOTES: Connect three indicated pads. Connect three indicated pads. Substrate Bias: Internally connected power supply.
MECHANICAL INFORMATION
MILS (0.001") Size Thickness Min. Size Backing MILLIMETERS 1.75 2.67 ±0.13 0.51 ±0.08 Gold
PGA103 TOPOGRAPHY
TYPICAL PERFORMANCE CURVES
+25°C, ±15V unless otherwise noted. VOLTAGE GAIN FREQUENCY Power Supply Rejection (dB) G=100
POWER SUPPLY REJECTION FREQUENCY G=100 G=10
Voltage Gain (dB)
100k Frequency (Hz) G=10
100k
Frequency (Hz)
PGA103
TYPICAL PERFORMANCE CURVES (CONT)
+25°C, ±15V unless otherwise noted.
1000
INPUT VOLTAGE NOISE FREQUENCY
INPUT CURRENT NOISE FREQUENCY
Voltage Noise (nV/Hz)
Current Noise (pA/Hz)
G=10 G=100 Bandwidth Limited Frequency (Hz) 100k
Gains Frequency (Hz) 100k
QUIESCENT CURRENT TEMPERATURE Quiescent Current (mA) G=10 50mV/div
SMALL SIGNAL RESPONSE
G=100
2µs/div Temperature (°C)
LARGE SIGNAL RESPONSE
G=10 5V/div G=100
2µs/div
PGA103
APPLICATION INFORMATION
Figure shows basic connections required operation PGA103. Applications with noisy high impedance power supplies require decoupling capacitors close device pins shown.
+15V 0.1µF -15V 0.1µF
Some applications select gain PGA103 with switches jumpers. Figure shows pull-up resistors connected assure noise-free logic when switch jumper open. Fixed-gain applications connect logic inputs directly ground other valid logic level) without series resistor.
PGA103
100k
PGA103
100k
GAIN Closed Closed Open Open Closed Open Closed Open
Valid
GAIN Valid
Logic (-5.6) 0.8V Logic (V+) Logic voltages referred
FIGURE Switch Jumper-Selected Gains. OFFSET TRIMMING Offset voltage laser-trimmed typically less than 200µV (referred input) three gains. input-referred offset voltage different each gain.
+15V -15V
NOTE: impedance ground connection required good gain accuracy-see text.
FIGURE Basic Connections. input output referred ground terminal, This must low-impedance connection assure good gain accuracy. resistance series with ground will cause gain G=100 decrease approximately 0.2%. DIGITAL INPUTS digital inputs, select gain according logic table Figure digital inputs interface directly common CMOS logic components. logic inputs referenced ground terminal, logic table Figure shows that logic both invalid. This logic code will cause damage, amplifier output will predictable while this code selected. output will recover when valid code selected. digital inputs latched, change logic inputs immediately selects gain. Switching time logic approximately 0.5µs. time respond gain change equal switching time plus time takes amplifier settle output voltage newly selected gain (see settling time specifications). Many applications external logic latch access gain control signals from high speed data bus. Using external latch isolates high speed digital from sensitive analog circuitry. Locate latch circuitry practical from analog circuitry avoid coupling digital noise into analog circuitry.
PGA103 VTRIM
(VIN VTRIM)
+15V OPA602
100k
±5mV Trim Range
Logic threshold voltage altered VTRIM. VTRIM 100mV.
-15V
NOTE: buffer required preserve good gain accuracy-see text.
FIGURE Offset Voltage Trim Circuit. Figure shows circuit used trim offset voltage PGA103. buffers trim voltage provide impedance ground terminal. This required maintain accurate gain. Remember that logic inputs, referenced this ground connection, logic threshold voltage will affected trim voltage. This insignificant offset adjustment used only trim offset voltage. large offset used (greater than 0.1V), sure that logic input signals provide valid logic levels when referred voltage ground terminal,
PGA103
VIN- PGA205 VIN+
True instrumentation amplifier input.
Accepts inputs ±120V. 11.3k 102k
+15V -15V
0.1, PGA103
PGA103
IN4148
GAIN
FIGURE Wide Input Voltage Range Amplifer.
FIGURE Programmable Gain Instrumentation Amplifier.
MODEL INA103 INA105 INA106 INA114 INA117 INA111 INA131
CHARACTERISTICS Noise, 1nV/Hz Difference Difference Resistor-Programmed Gain, Precision ±200V Input Range Difference Input, High Speed Precision,
VIN+
VIN-
PGA103
FIGURE Instrumentation Amplifier with Programmable Gain Output Amp.
PGA103
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2006
PACKAGING INFORMATION
Orderable Device PGA103P PGA103U
Status OBSOLETE ACTIVE
Package Type PDIP SOIC
Package Drawing
Pins Package Plan Pb-Free (RoHS)
Lead/Ball Finish Call NIPDAU
Peak Temp Call Level-3-260C-168
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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