Kbit Parallel EEPROM With Software Data Protection Fast Access Ti

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Kbit Parallel EEPROM With Software Data Protection Fast Access Ti

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M28C16B M28C17B
Kbit Parallel EEPROM With Software Data Protection
Fast Access Time: VCC=5V Single Supply Voltage: M28CxxB M28CxxB-W
Power Consumption Fast BYTE PAGE WRITE Bytes) VCC=4.5 VCC=2.7
Enhanced Write Detection Monitoring: Data Polling Toggle Page Load Timer Status
PLCC32
JEDEC Approved Bytewide Pin-Out Software Data Protection 100000 Erase/Write Cycles (minimum) Data Retention (minimum): Years
DESCRIPTION M28C16B M28C17B devices consist 2048x8 bits power, parallel EEPROM, fabricated with STMicroelectronics' proprietary single polysilicon CMOS technology. devices offer fast access time, with power dissipation, require single voltage supply.
Figure Logic Diagram
Table Signal Names
A0-A10 DQ0-DQ7 Address Input
A0-A10
DQ0-DQ7
Data Input Output Write Enable Chip Enable Output Enable Ready/Busy (M28C17B only) Supply Voltage Ground
M28C16B M28C17B (M28C17B only)
AI02816
February 1999
This preliminary information product development undergoing evaluation. Details subject change without notice.
1/17
M28C16B, M28C17B
Figure PLLC Connections
Figure PLLC Connections
M28C17B
AI02817 AI02830
M28C16B
Note: Connected
Note: Connected
M28C17B like M28C16B every way, except that extra ready/busy (RB) output. device been designed offer flexible microcontroller interface, featuring software handshaking, with Data Polling Toggle Bit. device supports byte Page Write operation. Software Data Protection (SDP) also supported, using standard JEDEC algorithm. SIGNAL DESCRIPTION external connections device summarized Table their Table Addresses (A0-A10). address inputs used select byte from memory array during read write operation. Data In/Out (DQ0-DQ7). contents data byte written read from, memory array through Data pins. Chip Enable (E). chip enable input must held enable read write operations. When Chip Enable high, power consumption reduced. Output Enable (G). Output Enable input controls data output buffers, used initiate read operations. Write Enable (W). Write Enable input controls whether addressed location read, from written Ready/Busy (RB). Ready/Busy M28C17B only) open drain output that used detect internal write cycle.
DEVICE OPERATION order prevent data corruption inadvertent write operations, internal comparator inhibits Write operations voltage lower than (see Table 4A). Once voltage applied goes over threshold CC>VWI), write access memory allowed after time-out PUW, specified Table Further protection against data corruption offered pass filters: glitch, inputs, with pulse width less than (typical) internally filtered prevent inadvertent write operations memory. Read device accessed like static RAM. When low, high, contents addressed location presented pins. Otherwise, when either high, pins revert their high impedance state. Write Write operations initiated when both high. device supports both W-controlled E-controlled write cycles shown Figure Figure 12). address latched during falling edge (which ever occurs later) data latched rising edge (which ever occurs first). After delay, tWLQ5H, that cannot shorter than value specified Table 10A, internal write cycle starts. continues, under internal timing control, until write operation complete. commencement this period detected reading Page Load Timer Status DQ5.
2/17
M28C16B, M28C17B
Table Absolute Maximum Ratings
Symbol TSTG VESD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model) Value -0.3 -0.6 VCC+0.6 -0.3 4000 Unit
Note: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also SURE Program other relevant quality documents. MIL-STD-883C, 3015.7 (100 1500
Figure Block Diagram
RESET
CONTROL LOGIC
DECODE
A6-A10 (Page Address)
ADDRESS LATCH
ARRAY
A0-A5
ADDRESS LATCH
DECODE
SENSE DATA LATCH
BUFFERS
PAGE LOAD TIMER STATUS TOGGLE DATA POLLING
AI02818
DQ0-DQ7
3/17
M28C16B, M28C17B
Table Operating Modes
Mode Stand-by Output Disable Write Disable Read Write Chip Erase DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Data Hi-Z
Note: 0=VIL; 1=VIH; VIL; V=12V
cycle detected reading status Data Polling Toggle functions DQ6. Page Write Page Write mode allows bytes written single page single This achieved through series successive Write operations, which separated more than tWLQ5H value specified Table 10A). page write initiated during byte write operation. Following first byte write instruction host send another address data with minimum data transfer rate WLQ5H. internal write cycle start instant after tWLQ5H. Once initiated, write operation internally timed, continues, uninterrupted, until completion. bytes must located same page address (A10-A6 must same bytes).
Otherwise, Page Write operation executed. with single byte Write operation, described above, DQ5, lines used detect beginning internally controlled phase Page Write cycle. Software Data Protection (SDP) device offers software-controlled write-protection mechanism that allows user inhibit write operations device. This useful protecting memory from inadvertent write cycles that occur during periods instability (uncontrolled conditions when excessive noise detected, when power supply levels outside their specified values). default, device shipped "unprotected" state: memory contents freely changed user. Once Software Data Protection Mode enabled, write commands
Table Power-Up Timing1 M28CxxB range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
Table Power-Up Timing1 M28CxxB-W range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
4/17
M28C16B, M28C17B
Figure Software Data Protection Enable Algorithm Memory Write
Write Address 555h Page Write Timing (see note Page Write Timing (see note Write Address 555h
Write Address 2AAh
Write Address 2AAh
Write Address 555h
Write Address 555h Write Enabled
Physical Page Write Instruction
Page Write bytes)
Enable Algorithm
Write Memory When
AI02819
Note: most significant address bits (A10 differ during these specific Page Write operations.
ignored, have effect memory contents. device remains this mode until valid Software Data Protection disable sequence received. device reverts "unprotected" state. status Software Data Protection (enabled disabled) represented non-volatile latch, remembered across periods power being off. Software Data Protection Enable command consists writing three specific data bytes three specific memory locations (each location being different page), shown Figure Similarly disable Software Data Protection, user write specific data bytes into dif-
ferent locations, shown Figure This complex series operations protects against chance inadvertent enabling disabling Software Data Protection mechanism.
Figure Software Data Protection Disable Algorithm
Write Address 555h
Write Address 2AAh
Figure Status Assignment
Page Write Timing
Write Address 555h
Write Address 555h PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write Address 2AAh
PLTS Hi-Z
Data Polling Toggle Page Load Timer Status High impedance
AI02815
Write Address 555h
Unprotected State
AI02820
5/17
M28C16B, M28C17B
Figure Chip Erase Waveforms
tWHEH
tGLWH tELWL tWLWH2 tWHRH
AI01484B
Table Chip Erase Characteristics1
Symbol tELWL tWHEH tWLWH2 tGLWH tWHRH Parameter Chip Enable Write Enable Write Enable High Chip Enable High Write Enable Write Enable High Output Enable Write Enable High Write Enable High Write Enable Test Condition Min. Max. Unit
Note: Sampled only, 100% tested.
When enabled, memory array still have data written sequence more complex (and hence better protected from inadvertent use). sequence shown Figure This consists unlock key, enable write action, which continues enabled. This allows enabled, data written, within single Write cycle (tWC). Software Chip Erase contents entire memory erased (set FFh) holding Chip Enable low, holding Output Enable VCC+7.0V. chip cleared when pulse applied Write Enable signal (see Figure Table details). Status Bits devices provide three status bits (DQ7, DQ5), during write operations. These allow application write time latency device getting with other work. These signals available port bits DQ7, (but only during programming cycle,
once byte more been latched into memory). Data Polling (DQ7). internally timed write cycle starts after tWLQ5H (defined Table 10A) elapsed since previous byte latched memory. value this last byte, used signal throughout this write operation: inverted while internal write operation underway, inverted back original value once operation complete. Toggle (DQ6). device offers another determining when internal write cycle completed. During internal Erase/Write cycle, toggles from (the first read value being '0') subsequent attempts read byte memory. When internal write cycle complete, toggling stopped, values read DQ7-DQ0 those addressed memory byte. This indicates that device again available Read Write operations. Page Load Timer Status (DQ5). internal timer used measure period between suc-
6/17
M28C16B, M28C17B
Table Read Mode Characteristics M28CxxB range)
Symbol ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (TTL inputs) Supply Current (CMOS inputs) Supply Current (Stand-by) Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -400 Test Condition VOUT VIL, VIL, 0.3V -0.3 Min. Max. Unit
Note: inputs outputs open circuit.
Table Read Mode Characteristics M28CxxB-W range)
Symbol ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) VIL, MHz, 3.6V Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -400 0.3V -0.3 Test Condition VOUT VIL, MHz, 3.3V Min. Max. Unit
Note: inputs outputs open circuit.
cessive Write operations, WLQ5H (defined Table 10A). line held show when this timer running (hence showing that device received write operation, waiting next). line held high when counter overflowed (hence showing that device starting internal write memory array).
7/17
M28C16B, M28C17B
Table Input Output Parameters MHz)
Symbol COUT Parameter Input Capacitance Output Capacitance Test Condition VOUT Min. Max. Unit
Note: Sampled only, 100% tested.
Table Measurement Conditions
Input Rise Fall Times Input Pulse Voltages Input Output Timing Reference Voltages
Figure Testing Input Output Waveforms
Figure Testing Equivalent Load Circuit
2.4V 2.0V 0.8V DEVICE UNDER TEST 100pF
0.4V
AI02821
includes capacitance
AI02102B
8/17
M28C16B, M28C17B
Table Read Mode Characteristics M28CxxB range)
M28CxxB Symbol Alt. Parameter Test Condition tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition VIL, VIL, Unit
Note: Output Hi-Z defined point which data longer driven.
Table Read Mode Characteristics M28CxxB-W range)
M28CxxB-W Symbol Alt. Parameter Test Condition tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition VIL, VIL, Unit
Note: Output Hi-Z defined point which data longer driven.
9/17
M28C16B, M28C17B
Table 10A. Write Mode Characteristics M28CxxB range)
M28C17B Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out After Last Byte Write Write Cycle Time Data Valid before Write Enable High Data Valid before Chip Enable High VIL, VIH, Test Condition VIL, VIH, Unit
10/17
M28C16B, M28C17B
Table 10B. Write Mode Characteristics M28CxxB-W range)
M28C17B-xxW Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out after last byte write Write Cycle Time Data Valid before Write Enable High Data Valid before Chip Enable High VIL, VIH, 1000 Test Condition VIL, VIH, 1000 Unit
11/17
M28C16B, M28C17B
Figure Read Mode Waveforms (with Write Enable, high)
A0-A10 tAVQV tGLQV tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA Hi-Z
AI02822
Note: Write Enable
Figure Write Mode Waveforms (Write Enable, controlled)
A0-A10 tAVWL tELWL tGHWL tWLDV DQ0-DQ7 DATA tDVWH tWHRL
AI02823
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWHWL
tWHDX
12/17
M28C16B, M28C17B
Figure Write Mode Waveforms (Chip Enable, controlled)
A0-A10 tAVEL tGHEL tWLEL tELDV DQ0-DQ7 DATA tDVEH tEHRL
AI02824
VALID tELAX
tELEH
tEHGL
tEHWH
tEHDX
Figure Page Write Mode Waveforms (Write Enable, controlled)
A0-A10 Addr Addr Addr Addr
tWHWL tWLWH DQ0-DQ7 (in) Byte Byte Byte Byte
(out) tWHRL
AI02825
tWLQ5H tQ5HQ5X
13/17
M28C16B, M28C17B
Figure Software Protected Write Cycle Waveforms
tWLWH tAVEL A0-A5 tWHDX A6-A10 555h tDVWH DQ0-DQ7 Byte Byte Byte
AI02826
tWHWL
tWHWH
tWLAX Byte Address
2AAh
555h
Page Address
Note: must specify same page address during each high-to-low transition must high only when both low.
Figure Data Polling Sequence Waveforms
A0-A10 Address last byte Page Write instruction
Last WRITE
Internal Write Sequence
Ready
AI02827
14/17
M28C16B, M28C17B
Figure Toggle Sequence Waveforms
A0-A10
Last WRITE
TOGGLE Internal Write Sequence
Ready
AI02828
Note: Toggle first `0'.
Table Ordering Information Scheme
Example: M28C16
Ready/Busy Connected Ready/Busy
Option Tape Reel Packing
Speed range only) range only)
Temperature Range
Operating Voltage blank
Package PLCC32
ORDERING INFORMATION Devices shipped from factory with memory content `1's (FFh). notation used device number shown Table list available options (speed, package, etc.) further information aspect this device, please contact Sales Office nearest you.
15/17
M28C16B, M28C17B
Table PLCC32 lead Plastic Leaded Chip Carrier, rectangular
Symbol 0.89 1.27 Typ. Min. 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 0.00 0.10 Max. 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.25 0.035 0.050 Typ. inches Min. 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 0.000 0.004 Max. 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 0.010
Figure PLCC
0.51 (.020)
D2/E2
1.14 (.045)
PLCC
Note: Drawing scale.
16/17
M28C16B, M28C17B
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. 1999 STMicroelectronics Rights Reserved logo registered trademark STMicroelectronics. other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http://www.st.com
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Kbit Parallel EEPROM With Software Data Protection Fast Access Ti

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