Kbit (2Kb Parallel EEPROM FAST ACCESS TIME: 150ns 250ns SINGLE SU

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Kbit (2Kb Parallel EEPROM FAST ACCESS TIME: 150ns 250ns SINGLE SU

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M28C16A M28C17A
Kbit (2Kb Parallel EEPROM
FAST ACCESS TIME: 150ns 250ns SINGLE SUPPLY VOLTAGE: M28C16A M28C17A 2.7V 3.6V M28C16-xxW POWER CONSUMPTION FAST WRITE CYCLE Bytes Page Write Operation Byte Page Write Cycle: ENHANCED WRITE DETECTION Ready/Busy Open Drain Output Data Polling Toggle PAGE LOAD TIMER STATUS HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY Endurance >100,000 Erase/Write Cycles Data Retention Years JEDEC APPROVED BYTEWIDE DESCRIPTION M28C16A M28C17Aare power Parallel EEPROM fabricatedwith STMicroelectronics proprietarysingle polysilicon CMOS technology. device offers fast access time with power dissipation requires power supply. Table Signal Names
A0-A10 DQ0-DQ7 Address Input Data Input Output Write Enable Chip Enable Output Enable Ready Busy Supply Voltage Ground
PDIP28 (BS)
PLCC32 (KA)
SO28 (MS) mils
TSOP28 (NS) x13.4mm
Figure Logic Diagram
A0-A10
DQ0-DQ7
M28C16A M28C17A
AI02109
August 1998
1/19
M28C16A, M28C17A
Figure Connections Figure Connections
M28C17A
AI02110
M28C16A M28C17A
AI02111
Warning: Connected, Don't Use.
Warning: Connected, Don't Use. Note: either M28C17A M28C16A.
Figure Connections
Figure TSOP Connections
M28C17A
M28C16A
AI02113
AI02112
Warning: Connected, Don't Use. 2/19
Warning: Connected, Don't Use.
M28C16A, M28C17A
Table Absolute Maximum Ratings
Symbol VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)
Value +0.6 3000
Unit
Notes: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification mplied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents. Depends range.
Table Operating Modes
Mode Read Write Standby Write Inhibit Write Inhibit Write Inhibit Output Disable
Note:
Data Data Hi-Z Data Hi-Z Data Hi-Z Hi-Z
DESCRIPTION (cont'd) circuit been designed offer flexible microcontroller interface featuring both hardware software handshakingmode with Ready/Busy, Data Polling Toggle Bit. M28C16A/17A supports byte page write operation. DESCRITPION Addresses (A0-A10). address inputs select 8-bit memory location during read write operation. Chip Enable (E). chip enable input must enable read/write operations. When Chip Enable high, power consumption reduced. Output Enable (G). Output Enable input controls data output buffers used initiate read operations. Data (DQ0 DQ7). Data written read from M28C16A/17A through pins.
Write Enable (W). Write Enable input controls writing data M28C16A/17A. Ready/Busy (RB). Ready/Busy open drain output that used detect internal write cycle. Ready/Busy available M28C17A PDIP, PLCC packages, M28C16A TSOP only. OPERATION order prevent data corruption inadvertent write operations during power-up, Power Reset (POR) circuit resets internal programming cicuitry. Access memory write mode allowed after power-up specified Table Read M28C16A/17Ais accessed like static RAM. When with high, data addressed presented pins. pins high impedancewhen either high.
3/19
M28C16A, M28C17A
Figure Block Diagram
RESET
CONTROL LOGIC
DECODE
A6-A10 (Page Address)
ADDRESS LATCH
ARRAY
A0-A5
ADDRESS LATCH
DECODE
SENSE DATA LATCH
BUFFERS
PAGE LOAD TIMER STATUS TOGGLE DATA POLLING
AI01520
DQ0-DQ7
OPERATION (cont'd) Write Write operations initiated when both high.The M28C16A/17Asupports both controlled write cycles. Address latched falling edge which ever occurs last Data rising edge which ever occurs first. Once initiated write operation internally timed until completion. Page Write Page write allows bytes consecutively latched into memory prior initiating Figure Status Assignment
PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
programming cycle. bytes must located single page address, that must same bytes. page write initiated during byte write operation. Following first byte write instruction host send another address data maximum tWHWH after rising edge which ever occurs first. transition detected within tWHWH, internal programming cycle will start. Microcontroller Control Interface M28C16A/17A provides write operation status bits status that used minimize system write cycle. These signals available port bits memory during programming cycle only, signal separate pin. Data Polling (DQ7). During internal write cycle, attempt read last byte written will produce complementary value previously latched bit. Once write cycle finished true logic value appears read cycle.
Data Polling Toggle PLTS Page Load Timer Status
4/19
M28C16A, M28C17A
Table Measurement Conditions
Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages
Note that Output Hi-Z defined point where data longer driven.
20ns 0.4V 2.4V 0.8V 2.0V
Figure Testing Input Output Waveforms
4.5V 5.5V Operating Voltage 2.4V 2.0V 0.8V
Figure Testing Equivalent Load Circuit
0.4V
DEVICE UNDER TEST
2.7V 3.6V Operating Voltage 0.3V
AI02101B
30pF
includes capacitance
AI02114
Table Capacitance
Symbol Parameter Input Capacitance Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested.
Table Read Mode Characteristics M28C16A M28C17A 85°C, 4.5V 5.5V)
Symbol ICC1 ICC2
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL CMOS inputs) Supply Current (Standby) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage
Test Condition VIL, 5MHz 0.3V
Unit
-0.3 -400
Note: I/O's open circuit.
5/19
M28C16A, M28C17A
Table Power Timing M28C16A M28C17A 85°C, 4.5V 5.5V)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Unit
Note: Sampled only, 100% tested.
Table Read Mode Characteristics M28C16A-W 85°C, 2.7V 3.6V)
Symbol ICC2
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL CMOS inputs) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage
Test Condition VIL, -0.3V
Unit
-0.3 -400
Note: I/O's open circuit.
Table Power Timing M28C16A-W 85°C, 2.7V 3.6V)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Unit
Note: Sampled only, 100% tested.
6/19
M28C16A, M28C17A
Table Read Mode Characteristics M28C16A M28C17A 85°C, 4.5V 5.5V)
M28C16A M28C17A Symbol Parameter Test Condition tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tACC Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition VIL, VIL, Unit
Note: Output Hi-Z defined point which data longer driven.
Table Read Mode Characteristics M28C16-W 85°C, 2.7V 3.6V)
M28C16A M28C17A Symbol Parameter Test Condition tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tACC Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition VIL, VIL, Unit
Note: Output Hi-Z defined point which data longer driven.
7/19
M28C16A, M28C17A
Figure Read Mode Waveforms
A0-A10 tAVQV tGLQV tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA Hi-Z
AI01511B
Note: Write Enable High
Toggle (DQ6). M28C16A/17A offers another determining when internal write cycle completed. During internal Erase/Write cycle, will toggle from (the first read value "0") subsequentattempts read address memory. When internalcycle completedthe togglingwill stopand device will accessible Read Write operation.
Page Load Timer Status (DQ5). Page Write mode data latched tWHWH after previous byte. bytes input. Data output (DQ5) indicates status internal Page Load Timer. read asserting Output Enable (tPLTS). indicates timer running, High
8/19
M28C16A, M28C17A
Table Write Mode Characteristics M28C16A M28C17A 85°C, 4.5V 5.5V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tWHRL tEHRL tDVWH tDVEH tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Write Enable High Ready/Busy Chip Enable High Ready/Busy Data Valid before Write Enable High Data Valid before Chip Enable High Note Note VIL, VIH, Test Condition VIL, VIH, Unit
Note: With external pull-up resistor.
9/19
M28C16A, M28C17A
Table Write Mode Characteristics M28C16-W 85°C, 2.7V 3.6V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tWHRL tEHRL tDVWH tDVEH tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Write Enable High Ready/Busy Chip Enable High Ready/Busy Data Valid before Write Enable High Data Valid before Chip Enable High Note Note VIL, VIH, Test Condition VIL, VIH, Unit
Note: With external pull-up resistor.
10/19
M28C16A, M28C17A
Figure Write Mode Waveforms Write Enable Controlled
A0-A10 tAVWL tELWL tGHWL
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWLDV DQ0-DQ7 DATA tDVWH
tWHWL
tWHDX
tWHRL
AI01512
Figure Write Mode Waveforms Chip Enable Controlled
A0-A10 tAVEL tGHEL tWLEL
VALID tELAX
tELEH
tEHGL
tELDV DQ0-DQ7 DATA tDVEH tEHDX
tEHWH
tEHRL
AI01513
11/19
M28C16A, M28C17A
Figure Page Write Mode Waveforms Write Enable Controlled
A0-A10
Addr
Addr
Addr
Addr
tPLTS tWHWL tWLWH DQ0-DQ7 Byte Byte tWHWH Byte tWHWH Byte tWHRH
tWHRL
Byte
AI01514
Figure Data Polling Waveform Sequence
A0-A10
Address last byte Page Write instruction
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI01516
12/19
M28C16A, M28C17A
Figure Toggle Waveform Sequence
A0-A10
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI01517
Note: First Toggle forced
13/19
M28C16A, M28C17A
ORDERING INFORMATION SCHEME Example: M28C16
Device Identifier available only TSOP package available
Option Tape Reel Packing
Speed
Operating Voltage blank 4.5V 5.5V write 2.7V 3.6V write
Package PDIP28 SO28 mils TSOP28 13.4mm PLCC32
Temperature Range
250ns
300ns
Notes: Available M28C16A M28C17A only. Available Operating Voltage only.
Devices shipped from factory with memory content "1's" (FFh). listof availableoptions (Speed, Package,etc. further informationon aspect this device, please contact STMicroelectronics Sales Office nearest you.
14/19
M28C16A, M28C17A
PDIP28 Plastic DIP, mils width
Symb 2.54 14.99 33.02 15.24 1.52 0.38 3.56 0.38 0.20 36.83 13.59 15.24 3.18 1.78 5.08 4.06 0.51 0.30 37.34 13.84 17.78 3.43 2.08 0.100 0.590 1.300 0.600 0.060 inches 0.015 0.140 0.015 0.008 1.450 0.535 0.600 0.125 0.070 0.200 0.160 0.020 0.012 1.470 0.545 0.700 0.135 0.082
PDIP
Drawing scale.
15/19
M28C16A, M28C17A
PLCC32 lead Plastic Leaded Chip Carrier, rectangular
Symb 0.89 1.27 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 0.00 0.10 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.25 0.035 0.050 inches 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 0.000 0.004 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 0.010
0.51 (.020)
D2/E2
1.14 (.045)
PLCC
Drawing scale.
16/19
M28C16A, M28C17A
SO28 lead Plastic Small Outline, mils body width
Symb 1.27 2.46 0.13 2.29 0.35 0.23 17.81 7.42 10.16 0.61 0.10 2.64 0.29 2.39 0.48 0.32 18.06 7.59 10.41 1.02 0.050 inches 0.097 0.005 0.090 0.014 0.009 0.701 0.292 0.400 0.024 0.004 0.104 0.011 0.094 0.019 0.013 0.711 0.299 0.410 0.040
SO-b
Drawing scale.
17/19
M28C16A, M28C17A
TSOP28 lead Plastic Thin Small Outline, 13.4mm
Symb 0.55 0.95 0.17 0.10 13.20 11.70 7.90 0.50 0.10 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 0.70 0.022 0.037 0.007 0.004 0.520 0.461 0.311 0.020 0.004 inches 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 0.028
TSOP-c
Drawing scale.
18/19
M28C16A, M28C17A
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Spec ifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. 1998 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
19/19

Kbit (2Kb Parallel EEPROM FAST ACCESS TIME: 150ns 250ns SINGLE SU

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